JPH0446483B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital AGC circuit.

Conventional technology As is well known, the AGC circuit (automatic
A gain control circuit (gain control circuit) keeps the output signal level constant even if the input signal level fluctuates.

FIG. 4 is a block diagram showing an example of such an AGC circuit. The AGC circuit shown in this figure is inserted between its control terminal 1 and the ground point.
An AGC amplifier 3 whose gain changes according to the lease-drain resistance value of the FET (field effect transistor) 2, an absolute value unit 4 that takes the absolute value of the output of this AGC amplifier 3, and an absolute value unit 4 that measures the output of this absolute value unit 4. It is composed of an integrator 5 that integrates and controls the gate voltage of the FET 2, and when the input signal (analog signal) input to the AGC amplifier 3 fluctuates, its output signal (analog signal) changes. if,
This output change is the absolute value unit 4, integrator 5, FET2
are fed back to the AGC amplifier 3 via the AGC amplifier 3, and the output level of the AGC amplifier 3 is returned to the original level.

Problems to be Solved by the Invention By the way, in the conventional AGC circuit described above, since the integrator 5 is configured by a time constant circuit consisting of a capacitor and a resistor, the gain of the AGC amplifier 3 cannot be fixed. Nakatsuta. Therefore, in a case where there is a frequency signal only when the bit indicating white color is present, such as the signal used in the G mode of a facsimile, if the bit indicating black color (zero voltage bit) is continuously supplied, the gain of AGC amplifier 3 will increase. There were problems such as saturation at the maximum value and a problem that the setting of the target gain value depended on the resistance capacitor.

Therefore, it is conceivable to configure a digital AGC circuit as shown in FIG. This AGC circuit is
LPF (low pass filter) 6 to prevent aliasing noise during A/D conversion and control terminal 7
a variable attenuator 8 that attenuates the output of the LPF 6 by an amount of attenuation according to a control signal (digital signal) DS3 supplied to the variable attenuator 8;
An A/D converter 9 A/D converts the output of the A/D converter 9 and outputs this A/D conversion result as an output signal DV3, and receives the output signal DV3 of this A/D converter 9 and sets it to a constant level. A control section 1 generates a control signal DS3 necessary for the above and supplies it to the variable attenuator 8.
0, and when a reception check completion signal output from a facsimile receiver (not shown) is input to the variable attenuator 8, a gate circuit inside the variable attenuator 8 controls the control terminal. Control signal DS3 supplied to 7
Even if the variable attenuator 8 changes, the attenuation amount of the variable attenuator 8 does not change. However, simply digitizing the conventional analog AGC circuit will not work.
The control section 10 becomes as shown in the block diagram of FIG. The control unit 10 shown in this figure includes a multiplier 12 that multiplies the output signal DV3 of the A/D converter 9 supplied to an input terminal 11 by a constant, a squarer 13 that squares the output of the multiplier 12, and a squarer 13 that squares the output of the multiplier 12. An adder 17 adds the output of the squarer 13 and the feedback signal S2, and when the square integral signal S3 which is the output of this adder 17 is higher than a predetermined upper limit value UTH, this square integral signal While S3 is higher than the upper limit value UTH, the count is increased at a predetermined period, and the adder 17
When the output of is lower than a predetermined lower limit value LTH, it counts down at a predetermined period while this squared integral signal S3 is lower than the lower limit value LTH, and outputs the obtained count result, Comparison counter 14 outputting latch signal S1
, a latch circuit 15 that latches the count result and outputs it from the output terminal 16 when the latch signal S1 is output, and a feedback loop 18 that delays the square integral signal S3 to generate a feedback signal S2. has been done. Here, the feedback loop 18
is composed of a unit delay element 19 that delays the output of the adder 17, and a multiplier 20 that multiplies the output of this unit delay element 19 by a constant and outputs the multiplication result as a feedback signal S2. The feedback loop 18 and the adder 17 integrate the output of the squarer 13. Therefore,
By adjusting each constant of the multipliers 12 and 20, desired integral characteristics can be obtained.

By the way, even if the control unit 10 is configured in this way, the amount of attenuation of the variable attenuator 8 can be fixed by supplying the reception check end signal to the variable attenuator 8, but the control unit 10 used here cannot be stabilized. In other words, in this control section 10, the response of the square integral signal S3 to a change in the A/D converter output DV3 is very slow, so that the control signal for the variable attenuator 8 is
Control the value of DS3 to change excessively,
As a result, the squared integral signal S3, which is the output of the adder 17 delayed by the feedback loop 18, may oscillate as shown in FIG.

In view of the above circumstances, it is an object of the present invention to provide a digital AGC circuit that can prevent oscillation of the control section and stabilize the operation of the circuit.

Means for Solving the Problems In order to achieve this object, the digital AGC circuit according to the present invention includes a variable attenuator that attenuates an input signal, an A/D converter that converts the output of the variable attenuator into A/D, and an A/D converter that converts the output of the variable attenuator. an adder that adds the output of the A/D converter and a feedback signal; a comparison counter that updates the count result when the output of the adder is not between a predetermined upper limit value and lower limit value; When the comparison counter does not count, a signal obtained by delaying the output of the adder is supplied as a feedback signal to the preload adder, and when the comparison counter counts, a predetermined target value is supplied as the feedback signal. and a feedback loop that supplies data to the adder, and the attenuation amount of the variable attenuator is controlled based on the count result of the comparison counter.

Operation By this means, the present invention adjusts the amount of attenuation of the variable attenuator so that when the output of the adder is not between the upper limit value and the lower limit value, the comparison counter brings the output of the variable attenuator within a predetermined range. At the same time, the feedback loop supplies the target value to the adder to pull the output of the adder back between the upper and lower limits. This makes it possible to prevent the adder from oscillating, and to set the variable attenuator to the optimum attenuation amount according to the input signal without overshooting the variable attenuator.

Embodiment FIG. 1 is a block diagram showing an embodiment of a digital AGC circuit according to the present invention. The digital AGC circuit shown in this figure includes an LPF 25, a variable attenuator 26, an A/D converter 27, and a control section 28.
It is composed of.

LPF25 converts input signal (analog signal) into A/D
This input signal is low-passed to prevent aliasing noise from occurring during conversion, and the low-passed signal is supplied to the variable attenuator 26.

The variable attenuator 26 attenuates the output of the LPF 25 by an attenuation amount according to the control signal (digital signal) DS4 supplied to the control terminal 29, and when the reception section of the facsimile etc. outputs the reception check end signal, the attenuation amount is changed. The output of this variable attenuator 26 is supplied to an A/D converter 27.

The A/D converter 27 is connected to the variable attenuator 2.
6 output is A/D converted, and this A/D
The output signal DV4 outputted from the converter 27 is supplied to an input terminal 30 of the control section 28, and is also supplied to a subsequent stage circuit (not shown) via a terminal 31.

The control section 28 generates a control signal DS4 necessary for controlling the variable attenuator 26 based on the output signal DV4, and includes a multiplier 32, a squarer 33, and an adder as shown in FIG. 34
, a comparison counter 35 , a latch circuit 36 , and a feedback loop 37 .

The multiplier 32 multiplies the output signal DV4 of the A/D converter 27 supplied to the input terminal 30 by a constant A1, and the output of this multiplier 32 is supplied to a squarer 33.

The squarer 33 squares the output of the multiplier 32, and the output of this squarer 33 is sent to the adder 34.
is supplied to

The adder 34 adds the output of the squarer 33 and the feedback signal S5 to output a squared integral signal S6, and this squared integral signal S6 is supplied to a comparison counter 35.

The comparison counter 35 counts up when the value of the square integral signal S6 becomes higher than a predetermined upper limit value UTH, and when the value of the square integral signal S6 becomes higher than a predetermined lower limit value.
Count down when it falls below LTH,
The count result obtained by this count-up or count-down is supplied to the latch circuit 36, and when the count-up or count-down is performed, the latch signal (negative logic "1") is supplied.
A signal pulse) S7 is generated and supplied to the input terminal 39 of the feedback loop 37 and the latch signal input terminal 40 of the latch circuit 36.

The latch circuit 36 latches the count result output from the comparison counter 35 when the latch signal S7 is supplied and outputs it as a control signal DS4, and this control signal DS4 is sent to the output terminal of the control section 28. 41 and supplied to the control terminal 29 of the variable attenuator 26.

The feedback loop 37 also connects the latch signal S
7 is not output, the square integral signal S6 output from the adder 34 is delayed and supplied to the adder 34 as a feedback signal S5, and when the latch signal S7 is output, a predetermined The obtained target value OTH is supplied to the adder 34 as a feedback signal S5, and the register 4
2, a multiplexer 46 made up of AND gates 43 and 44 and an inverter 45, a unit delay element 47, and a multiplier 48.

The value of the square integral signal S6 is stored in the register 42,
Upper limit value UTH and lower limit value of the comparison counter 35
A target value OTH (a value that does not excessively change the value of the control signal DS4 of the variable attenuator 26, e.g. The value of the square integral signal S6 when the output DV4 of the A/D converter is set to a constant value) is stored, and this target value OTH is supplied to the multiplexer 46.

The multiplexer 46 receives the square integral signal S
6. It selectively takes in one of the target values OTH and outputs it, and when the latch signal S7 is not provided to the input terminal 39, the square integral signal S6 is selected and is delayed by a unit. When the latch signal S7 is supplied, the target value OTH is selected and supplied to the input terminal 50 of the unit delay element 47.

The unit delay element 47 delays the signal supplied to its input terminal 50, and the output of this unit delay element 47 is multiplied by A2 in a multiplier 48, and the multiplication result is sent to the adder 34 as a feedback signal S5. Supplied.

Next, the operation of this embodiment will be explained with reference to FIG.

First, when a large input signal is supplied to the LPF 25 while the attenuation amount of the variable attenuator 6 is small, the output signal DV4 of the A/D converter 27 becomes a large value, which is shown at time t1 in FIG. As the value of the square integral signal S6 exceeds the upper limit value UTH, the comparison counter 35 detects this, counts up, and outputs the latch signal S7.
As a result, the latch circuit latches a count result that is larger than the count result held up to that point, and uses this new count result to increase the attenuation amount of the variable attenuator 26 by one step.
Also, at this time, the value of the feedback signal S5 is the value of S6 before the unit delay, which is approximately equal to UTH, so at this time the multiplexer 46 reaches the target value.
OTH is selected and supplied to the unit delay element 47, and the value of the feedback signal S5 decreases from a value approximately equal to UTH to OTH. As a result, the output of the adder 34 that adds the feedback signal S5 and the output of the squarer 33 decreases, and the current attenuation amount is maintained without updating the count value of the comparison counter. Therefore, even when a large input signal is supplied, the attenuation amount of the variable attenuator 26 can be gradually increased without increasing it excessively. and,
When the output level of the A/D converter 27 falls within a predetermined range, the comparison counter 36 stops counting up and down, and the amount of attenuation of the variable attenuator 26 becomes constant. Similarly, when the square integral signal S6 falls below the lower limit value LTH, the attenuation amount of the variable attenuator 26 monotonically decreases and converges to a constant value. Therefore,
At this time, if the amount of attenuation of the variable attenuator 26 is fixed using the reception check end signal, etc., then
Even if the magnitude of the signal input to the LPF 25 changes, the attenuation amount of the variable attenuator 26 is always kept constant.

As described above, in this embodiment, since the value of the square integral signal S6 is always between the upper limit value UTH and the lower limit value LTH, the amount of attenuation of the variable attenuator 26 is prevented from becoming too large or too small. This makes it possible to prevent an oscillation phenomenon in which the amount of attenuation of the variable attenuator 26 does not converge to a constant value.

Further, in the embodiment described above, the attenuation amount of the variable attenuator 26 is fixed by the reception check completion signal, but the comparison counter 35 and the latch circuit 36 are fixed by the reception check completion signal or other signals.
etc. may be fixed.

Furthermore, in the embodiment described above, at the start of the AGC operation, the comparison counter 3
5 does not operate, but this is a measure when applying AGC to signals used in facsimile, and when applying AGC to other signals, it is necessary to eliminate such a dead area at the start. It's okay.

Effects of the Invention As explained above, according to the present invention, the gain of the AGC circuit can be fixed at any timing, and the gain can be prevented from becoming unstable due to oscillation of the circuit.

[Brief explanation of the drawing]

FIG. 1 shows a digital system according to an embodiment of the present invention.
A block diagram of the AGC circuit. Figure 2 is a block diagram showing a detailed example of the control section shown in Figure 1. Figure 3 is a waveform diagram to explain the operation of this embodiment. Figure 4 is a diagram of the conventional analog AGC circuit. Figure 5 is a block diagram showing a circuit example when this analog AGC circuit is digitized, Figure 6 is a detailed block diagram of the control section shown in Figure 5, and Figure 7 is a block diagram showing a circuit example when this analog AGC circuit is digitized. 5
FIG. 3 is a waveform diagram for explaining the operation of the digital AGC circuit shown in the figure. 25...Low pass filter, 26...Variable attenuator, 27...A/D converter, 28...Control unit, 33...Squarer, 34...Adder, 35...
Comparison counter, 36...Latch circuit, 37...Feedback loop.

Claims (1)

[Claims] 1 a variable attenuator that attenuates an input signal with an attenuation amount according to a control signal supplied to a control terminal;
An A/D converter for the output of this variable attenuator
A D converter, a feedback loop that inputs the output signal of this A/D converter and sequentially outputs it with a delay, and an adder that adds the feedback signal from this feedback loop and the output signal of the A/D converter. , a comparison counter that updates a count result when the output of the adder is not between a predetermined upper limit value and a lower limit value, and supplies the updated count result to the variable attenuator as a control signal; and a register that stores a predetermined target value set between a predetermined upper limit value and a lower limit value, and when updating the count result, the target value stored in the register is used as a feedback signal. A digital AGC circuit characterized by input to an adder.