JPH0446404A - Delay line - Google Patents

Delay line

Info

Publication number
JPH0446404A
JPH0446404A JP15628790A JP15628790A JPH0446404A JP H0446404 A JPH0446404 A JP H0446404A JP 15628790 A JP15628790 A JP 15628790A JP 15628790 A JP15628790 A JP 15628790A JP H0446404 A JPH0446404 A JP H0446404A
Authority
JP
Japan
Prior art keywords
conductors
strip
conductor
ground
delay line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15628790A
Other languages
Japanese (ja)
Other versions
JP2937421B2 (en
Inventor
Harufumi Bandai
治文 萬代
Giichi Kodo
義一 児堂
Atsushi Tojo
淳 東條
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2156287A priority Critical patent/JP2937421B2/en
Publication of JPH0446404A publication Critical patent/JPH0446404A/en
Application granted granted Critical
Publication of JP2937421B2 publication Critical patent/JP2937421B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Waveguides (AREA)

Abstract

PURPOSE:To eliminate the need for a ground conductor between both strip conductors and to make the thickness thin by forming two strip conductors between two ground conductors and devising the approached parts to be crossed almost at a right angle to each other so as to reduce the electromagnetic coupling between both the strip lines entirely. CONSTITUTION:Both ends 7a, 7b, 8a, 8b of ground conductors 7, 8 inserted between conductors 6, 9 are formed to reach a side face of a laminator 10, one end 7a of the conductor 7 is connected to an input external electrode 11, one end 8a of the conductor 8 is connected to an output outer electrode 12 and the other ends 7b, 8b are connected via a relay (connection use) outer electrode 13. Thus, the conductors 7, 8 are connected in series between the electrodes 11, 12 electrically. The conductors 7, 8 are formed in a meandering way, and parts of both the conductors 7, 8 close to each other in plane view are formed to be crossed almost at a right angle to each other. Thus, the electromagnetic coupling hardly takes place between the conductors 7, 8 over the entire length to eliminate the need for a ground conductor between the conductors 7, 8, resulting in thin profile.

Description

【発明の詳細な説明】 主粟上勿料里立■ 本発明は、コンピュータや計測器等において信号伝達を
遅延させるために用いるデイレイラインに関する。
Detailed Description of the Invention The present invention relates to a delay line used for delaying signal transmission in computers, measuring instruments, etc.

の ′ びその量 上記デイレイラインとして、第4図に示すように、アル
ミナ基板等の低誘電率素材よりなる基板21の下表面に
、はぼ全面にわたり接地導体22が形成され、かつ、上
表面に直線状態にストリップ導体23が形成され、所謂
マイクロストリップを用いた構成のものが知られている
As shown in FIG. 4, as the above-mentioned delay line, a ground conductor 22 is formed over almost the entire lower surface of a substrate 21 made of a low dielectric constant material such as an alumina substrate, and a ground conductor 22 is formed on the upper surface. A structure in which a strip conductor 23 is formed in a straight line and uses a so-called microstrip is known.

ところで、遅延時間の長さによっては、上述の如くスト
リップ導体23を直線状になすと時間が短いため、第5
図に示すようにストリップ導体23を蛇行状態に形成し
たものもあるが、これでも時間が不足する場合には、ス
トリップ導体を直線状や蛇行状態になしたデイレイライ
ンを積層し、かつ、ストリップ導体同士を直列状態に接
続することが行われている。
By the way, depending on the length of the delay time, if the strip conductor 23 is made straight as described above, the time will be shorter.
As shown in the figure, there is a device in which the strip conductor 23 is formed in a meandering state, but if even this is not enough time, a delay line in which the strip conductor 23 is formed in a straight or meandering state is laminated, and the strip conductor 23 is formed in a meandering state. It is common practice to connect them in series.

しかしながら、後者のように積層する場合には、全体が
厚肉化するという問題がある。具体的に蛇行状態のスト
リップ導体の場合を例に挙げて説明すると、−船釣に上
から見て両ストリップ導体が重なるように積層されるた
め、第6図に示す如く、両ストリップ導体32a、32
bの片側に、この場合にはシールドをも兼ねて外側に接
地導体31a、31cを設けるだけでは足りず、両スト
リソブ導体23a、32b間に生じる電磁気的な結合を
防止すべく、両ストリップ導体32a、32b間にも接
地導体31bを必要とし、厚肉化していた。なお、直線
状のストリップ導体の場合も同様である。
However, in the latter case, there is a problem in that the entire structure becomes thick. To specifically explain the case of a meandering strip conductor as an example, - Since both strip conductors are stacked so as to overlap when viewed from above in a boat fishing, as shown in FIG. 6, both strip conductors 32a, 32
It is not enough to provide the ground conductors 31a, 31c on one side of the strip conductor 31c on the outside, which in this case also serves as a shield. , 32b, and the ground conductor 31b is also required, resulting in a thick wall. Note that the same applies to the case of a straight strip conductor.

本発明はかかる事情に鑑みてなされたものであり、スト
リップ導体を2本積層したタイプにおいて薄肉化が図れ
るデイ1ノイラインを提供することを目的とする。
The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a day 1 noise line that can be made thinner in a type in which two strip conductors are laminated.

U壬−解決y(友及Ω子−段 本発明は、複数の誘電体層を積層してなる積層体を挟ん
で両側に接地導体が形成され、前記積層体の内部に、両
接地導体から離隔し、かつ一方の接地導体に対する離隔
距離を変えた2平面上に夫々ストリップ導体が設けられ
、これらストリップ導体が相互に接近する部分をほぼ直
行させた状態で形成されている。J:共に直列状態に接
続されていることを特徴とする。
In the present invention, ground conductors are formed on both sides of a laminate formed by laminating a plurality of dielectric layers, and a ground conductor is formed inside the laminate from both ground conductors. Strip conductors are provided on two planes that are separated from each other and have different distances from one ground conductor, and the strip conductors are formed so that the portions where they approach each other are substantially orthogonal.J: Both are in series. Characterized by being connected to the state.

作〜−−−−−用− 本発明にあっては、接地導体で両側を挾まれた誘電体層
の内部6ご、2本のストリップ導体が形成され、これら
ストリップ導体の接近する部分がほぼ直行する状態で形
成されているので、両ストリップ導体間で電磁気的な結
合が発住L7がたく、この結果、両ストリップ導体間に
は接地導体が不要となる。
In the present invention, two strip conductors are formed inside a dielectric layer sandwiched on both sides by ground conductors, and the portions where these strip conductors approach each other are approximately Since they are formed in a perpendicular state, electromagnetic coupling L7 is difficult to occur between both strip conductors, and as a result, there is no need for a ground conductor between both strip conductors.

実〜−−−8゜施、−一−−例 第1図は本発明に係るデイレイラインを示す分解斜視図
、第2図はそれを一体化した状態を示す斜視図である。
Embodiment - 8 DEG -1--Example FIG. 1 is an exploded perspective view showing a delay line according to the present invention, and FIG. 2 is a perspective view showing the integrated state.

このデイレイラインは、8第1図に示す5枚の誘電率の
低い素材からなる誘電体層1〜5を積層してなる積層体
10の側面部分に、入力用外部電極11、出力用外部電
極12、中継用(接続用)外部電極13及びアース用外
部電極14が形成された構成となっており、焼成によ杓
作製されている。
This delay line consists of an input external electrode 11, an output external electrode, 12. It has a configuration in which a relay (connection) external electrode 13 and a grounding external electrode 14 are formed, and is ladle-produced by firing.

具体的には、焼成により前記誘電体層となるグリーンシ
ート1を最上層とし、その下に以下の順で、上面に接地
導体6が形成されたグリーンシート2と、上面にストリ
ップ導体7が形成された・シ゛リーンシート3と、上面
にストリップ導体8が形成されたグリーンシート4と、
上面に接地導体9が形成されたグリーンシート5とが、
積層された積層体10の4箇所の側面及びこれに緊がる
上下面部分に、」二記各外部電極11〜14が印刷等に
より形成されたものを同時焼成して作製されている。こ
の焼成によりグリーンシート1〜5は一体化憚る。なお
、外部電極11へ14は焼成した後に形成してもよい。
Specifically, a green sheet 1 that becomes the dielectric layer by firing is the top layer, and below that, in the following order, a green sheet 2 with a ground conductor 6 formed on its top surface and a strip conductor 7 formed on its top surface. a green sheet 3 having a strip conductor 8 formed on its upper surface;
A green sheet 5 having a ground conductor 9 formed on its upper surface,
The external electrodes 11 to 14 are formed by printing or the like on four side surfaces of the stacked laminate 10 and the top and bottom surfaces attached thereto, and are produced by simultaneous firing. By this firing, the green sheets 1 to 5 are integrated. Note that the external electrodes 11 and 14 may be formed after firing.

上述した接地導体6.9、ストリップ導体7.8及び各
電極11−14の材料としては、例えばCu等の導電材
l:、lを使用している。また、グリーンシート1〜5
については、g電率の低い素キイを使用するのが好まし
2い。特に、8ス[・リップ導体や電極等の電極と同時
焼成を行う場合には、低温で焼結が可能な材質、例えば
ガラスとフィラー(アルミラー12シリカなど)を組み
合わせた複合材料やガラスセラミック等を使用するとよ
い。
The ground conductor 6.9, the strip conductor 7.8, and each electrode 11-14 are made of a conductive material such as Cu, for example. Also, green sheets 1 to 5
It is preferable to use a bare key with a low g-electricity. In particular, when co-firing with electrodes such as 8-slip conductors and electrodes, use materials that can be sintered at low temperatures, such as composite materials that combine glass and filler (such as Almirror 12 silica), glass ceramics, etc. It is recommended to use

前記2つの接地導体6.9ムこは、夫々接続片6a、9
aが積層体10の側面に達する状態で形成され、これら
接続片6a、9aはアース用外部電極14と接触されて
いて、接地導体6.9はアースとして機能する。
The two ground conductors 6.9 are connected to connection pieces 6a and 9, respectively.
a reaches the side surface of the laminate 10, these connecting pieces 6a, 9a are in contact with the grounding external electrode 14, and the grounding conductor 6.9 functions as a ground.

これら接地導体6,9にて挾まれたストリップ導体7及
び8は、両端7a、7b、8a、8bが積層体10の側
面に達する状態で形成され、スト’J ツブ導体7の一
端7aは入力用外部電極11に、ストリップ導体8の一
端8aは出力用外部電極12に接続、され、ストリップ
導体7.8の他端7b8bは中継用く接続用)各部電極
13を介して接続されている。従っm−、ストリ・ノブ
導体7.8は、入力用外部電極11と出力用外部電極1
2の間において直列状態で電気的に接続されている。
The strip conductors 7 and 8 sandwiched between the ground conductors 6 and 9 are formed with both ends 7a, 7b, 8a, and 8b reaching the side surfaces of the laminate 10, and one end 7a of the strip conductor 7 is connected to the input terminal. One end 8a of the strip conductor 8 is connected to the output external electrode 11, and the other end 7b8b of the strip conductor 7.8 is connected to the output external electrode 11 via the respective electrodes 13 (for relay connection). Therefore, the strip-knob conductor 7.8 connects the input external electrode 11 and the output external electrode 1.
2 are electrically connected in series.

このように電気的に接続された両スF・リップ導体7.
8は、共に蛇行状態に形成され、第3図乙こ示す如く、
平面視で両ストリップ導体7 (実線)と8 (破線)
が接近する部分へが相互に直行するようになしである。
Both S/F lip conductors electrically connected in this way 7.
8 are both formed in a meandering state, as shown in FIG.
Both strip conductors 7 (solid line) and 8 (dashed line) in plan view
The parts that are close to each other are perpendicular to each other.

このため、両ストリ・7ブ導体7と8の間では全長に亘
、って電磁気的な結合が起こりがたい。
Therefore, electromagnetic coupling is difficult to occur between the two strip conductors 7 and 8 over the entire length.

したがって、本発明のようなデイレイラインの場合、従
来では必要であった2本のストリップ導体間の接地導体
を省略でき、薄肉とすることが可能となる。
Therefore, in the case of the delay line of the present invention, the ground conductor between the two strip conductors, which was conventionally necessary, can be omitted, and the delay line can be made thinner.

なお、上記実施例では明言していないが、各ストリップ
導体7.8は、蛇行状態となすべく湾曲させている部分
の数や、その間の直線部分の長さ寸法について、所望の
遅延時間を確保する上で必要な任意の数や長さ寸法にな
したものを用いることもできる。
Although not explicitly stated in the above embodiments, each strip conductor 7.8 is designed to ensure a desired delay time with respect to the number of curved portions to create a meandering state and the length of the straight portion between them. It is also possible to use any number or length required for this purpose.

また、ストリップ導体としては、全体的に蛇行状態とし
たものに限らず、直線部分と蛇行部分を組合わせたもの
や、なだらかな直線で形成したもの、或いは直線で形成
したものであっても適用できる。要は、2つのストリッ
プ導体が接近する部分をほぼ直行させることができる形
状であればどのような形状であっても構わない。
In addition, the strip conductor is not limited to one that has a meandering shape as a whole, but can also be a combination of straight and meandering parts, a gentle straight line, or a straight line. can. In short, any shape may be used as long as the portions where the two strip conductors approach can be made substantially perpendicular to each other.

更に、ストリップ導体7.8間の接続は、積層体10の
外表面上の外部電極13で行うものに限らず、積層体l
Oの内部にピアホールを形成し、これを用いて行っても
よい。また、接地導体6゜9間の接続についても同様に
、接続片6a、9aと外部電極14を介して行うものに
限らず、積層体の内部にピアホールを形成し、このピア
ホールを介して両接地導体6,9間を接続するようにし
てもよい。
Furthermore, the connection between the strip conductors 7 and 8 is not limited to the one made by the external electrode 13 on the outer surface of the laminate 10, but also the connection between the strip conductors 7 and 8.
It is also possible to form a pier hole inside O and use this. Similarly, the connection between the ground conductors 6.9 is not limited to the connection via the connection pieces 6a, 9a and the external electrode 14, but a pier hole is formed inside the laminate, and both ground conductors are connected through the pier hole. The conductors 6 and 9 may also be connected.

皇里坐蓋来 以上詳述した如く本発明による場合には、2つの接地導
体の間に2本のストリップ導体が形成され、しかも相互
に接近する部分がほぼ直行するようになしであるので、
両ストリップ導体間の電磁気的結合をきわめて小さくで
き、よって従来では必要であった両ストリップ導体間の
接地導体を不要にできるので、従来品よりも薄くできる
という効果を奏する。
As described in detail above, in the case of the present invention, two strip conductors are formed between two ground conductors, and the parts approaching each other are almost perpendicular, so that
The electromagnetic coupling between both strip conductors can be made extremely small, and the ground conductor between both strip conductors, which was necessary in the past, can be made unnecessary, so that the product can be made thinner than conventional products.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係るデイレイラインを示す分解図、第
2図はそれを一体化した状態を示す外観斜視図、第3図
は第1図に示す2つのストリップ導体7と8を示す平面
図、第4図及び第5図は従来のデイレイラインを示す斜
視図、第6図は積層タイプの従来のデイレイラインを示
す断面図である。 第1図 1〜5・・・誘電体層、6 ・・・ストリップ導体。 9・・・接地導体、7.8 特許出願人 : 株式会社村田製作所 第2 図 第3図 第4図 第5 図 第6 図
FIG. 1 is an exploded view showing the delay line according to the present invention, FIG. 2 is an external perspective view showing the integrated state, and FIG. 3 is a plan view showing the two strip conductors 7 and 8 shown in FIG. 1. 4 and 5 are perspective views showing conventional delay lines, and FIG. 6 is a sectional view showing a laminated type conventional delay line. 1-5...Dielectric layer, 6...Strip conductor. 9...Grounding conductor, 7.8 Patent applicant: Murata Manufacturing Co., Ltd. Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

【特許請求の範囲】[Claims] (1)複数の誘電体層を積層してなる積層体を挟んで両
側に接地導体が形成され、前記積層体の内部に、両接地
導体から離隔し、かつ一方の接地導体に対する離隔距離
を変えた2平面上に夫々ストリップ導体が設けられ、こ
れらストリップ導体が相互に接近する部分をほぼ直行さ
せた状態で形成されていると共に直列状態に接続されて
いることを特徴とするディレイライン。
(1) Ground conductors are formed on both sides of a laminate formed by laminating a plurality of dielectric layers, and are spaced from both ground conductors inside the laminate, and are spaced apart from one of the ground conductors at different distances. 1. A delay line characterized in that strip conductors are provided on two planes, and the strip conductors are formed with mutually approaching portions being substantially perpendicular to each other and are connected in series.
JP2156287A 1990-06-13 1990-06-13 Delay line Expired - Lifetime JP2937421B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2156287A JP2937421B2 (en) 1990-06-13 1990-06-13 Delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2156287A JP2937421B2 (en) 1990-06-13 1990-06-13 Delay line

Publications (2)

Publication Number Publication Date
JPH0446404A true JPH0446404A (en) 1992-02-17
JP2937421B2 JP2937421B2 (en) 1999-08-23

Family

ID=15624516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2156287A Expired - Lifetime JP2937421B2 (en) 1990-06-13 1990-06-13 Delay line

Country Status (1)

Country Link
JP (1) JP2937421B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7684764B2 (en) 2003-04-30 2010-03-23 Fujitsu Media Devices Limited Duplexer using surface acoustic wave filters and electronic device equipped with the same
JP2010273048A (en) * 2009-05-20 2010-12-02 Mitsubishi Electric Corp Real time delay line

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01143403A (en) * 1987-11-30 1989-06-06 Nec Corp Delay line
JPH0264203U (en) * 1988-11-02 1990-05-15

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01143403A (en) * 1987-11-30 1989-06-06 Nec Corp Delay line
JPH0264203U (en) * 1988-11-02 1990-05-15

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7684764B2 (en) 2003-04-30 2010-03-23 Fujitsu Media Devices Limited Duplexer using surface acoustic wave filters and electronic device equipped with the same
JP2010273048A (en) * 2009-05-20 2010-12-02 Mitsubishi Electric Corp Real time delay line

Also Published As

Publication number Publication date
JP2937421B2 (en) 1999-08-23

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