JPH0445794B2 - - Google Patents

Info

Publication number
JPH0445794B2
JPH0445794B2 JP57162833A JP16283382A JPH0445794B2 JP H0445794 B2 JPH0445794 B2 JP H0445794B2 JP 57162833 A JP57162833 A JP 57162833A JP 16283382 A JP16283382 A JP 16283382A JP H0445794 B2 JPH0445794 B2 JP H0445794B2
Authority
JP
Japan
Prior art keywords
light
circuit
output
pulse
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57162833A
Other languages
Japanese (ja)
Other versions
JPS5873889A (en
Inventor
Toshibumi Fukuyama
Norio Onchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP57162833A priority Critical patent/JPS5873889A/en
Publication of JPS5873889A publication Critical patent/JPS5873889A/en
Publication of JPH0445794B2 publication Critical patent/JPH0445794B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01VGEOPHYSICS; GRAVITATIONAL MEASUREMENTS; DETECTING MASSES OR OBJECTS; TAGS
    • G01V8/00Prospecting or detecting by optical means
    • G01V8/10Detecting, e.g. by using light barriers
    • G01V8/12Detecting, e.g. by using light barriers using one transmitter and one receiver

Description

【発明の詳細な説明】 (イ) 発明の分野 この発明は、パルス変調光形の光電スイツチ、
すなわちパルス光を投射し、このパルス光に同期
した受光信号のみを取り出して検出動作を行なう
ようにしたタイプの光電スイツチに関し、特に自
己のパルス光と周期の似通つた他の光電スイツチ
のパルス光等の周期性のある雑音光に対して誤動
作することがないように回路構成を改善したパル
ス変調光形の光電スイツチに関する。
[Detailed Description of the Invention] (a) Field of the Invention The present invention relates to a pulse modulation light type photoelectric switch,
In other words, regarding a type of photoelectric switch that projects pulsed light and performs a detection operation by extracting only the received light signal that is synchronized with this pulsed light, it is particularly sensitive to the pulsed light of another photoelectric switch whose period is similar to that of its own pulsed light. This invention relates to a pulse modulated light type photoelectric switch whose circuit configuration has been improved so that it does not malfunction in response to periodic noise light such as.

(ロ) 従来技術とその問題点 パルス変調光形の光電スイツチでは、投光パル
スに同期した受光入力だけを取り出し、その他の
期間に入つた受光入力は禁止する、いわゆる同期
ゲート方式を採用しているため、非連続的な雑音
光に対しては誤動作防止の効果がある。しかしな
がら光電スイツチを第1図aに示すように、複数
個並置して使用する場合も多い。このような場
合、光電スイツチの投光部1T,2Tの光の投射
範囲及び受光部1R,2Rの受光範囲が広いと、
光電スイツチ1の投光部1Tからの光が被検出物
体3によつて遮られているにもかかわらず、光電
スイツチ2の投光部2Tからの光が光電スイツチ
1の受光部1Rに入射する。そして投光部1T,
2Tからはそれぞれ異つた位相,周期のパルス光
が投射されるようになつているが、パルス光の周
期は似通つている場合が多く、そのため投光部1
T,2Tのパルス光のタイミングが全く重なるこ
ともあり、こうなると他の光電スイツチの投射光
の影響は同期ゲート方式だけでは排除することが
できない。
(b) Prior art and its problems Pulse-modulated light type photoelectric switches employ a so-called synchronization gate method, which extracts only the received light input synchronized with the emitted light pulse and prohibits the received light input during other periods. Therefore, it is effective in preventing malfunctions against discontinuous noise light. However, as shown in FIG. 1a, a plurality of photoelectric switches are often used side by side. In such a case, if the light projection range of the light projecting parts 1T, 2T and the light receiving range of the light receiving parts 1R, 2R of the photoelectric switch are wide,
Even though the light from the light emitting portion 1T of the photoelectric switch 1 is blocked by the object to be detected 3, the light from the light emitting portion 2T of the photoelectric switch 2 enters the light receiving portion 1R of the photoelectric switch 1. . And the light projector 1T,
Pulsed light with different phases and periods are projected from the 2T, but the periods of the pulsed lights are often similar, so the projecting unit 1
The timings of the T and 2T pulse lights may completely overlap, and in this case, the influence of the projection light of other photoelectric switches cannot be eliminated only by the synchronization gate method.

このため従来は第1図bに示すように、投光部
1T,2T及び受光部1R,2Rの投光範囲及び
受光範囲を狭くして、他の光電スイツチからの投
射光が別の光電スイツチの受光部に入射しないよ
うにすることが考えられている。しかしながらこ
うすると、対応する投光部と受光部との光軸を合
せることが因難になり、振動や衝撃等により光軸
が少しでもずれた場合、動作に不都合を来たす等
の欠点がある。
For this reason, conventionally, as shown in FIG. 1b, the light emitting range and light receiving range of the light emitting parts 1T, 2T and the light receiving parts 1R, 2R are narrowed, so that the projected light from other photoelectric switches is transmitted to another photoelectric switch. Consideration has been given to preventing the light from entering the light receiving section of the device. However, in this case, it becomes difficult to align the optical axes of the corresponding light projecting section and light receiving section, and if the optical axes are even slightly deviated due to vibrations, shocks, etc., there are disadvantages such as inconvenience in operation.

また第1図cに示すように、投光部1T,2T
と受光部1R,2Rとを交互に配置することを考
えられているが、被検出物体3の表面反射率が良
好な場合には、反射光が他の光電スイツチの受光
部に入射てしまうので不都合である。
Furthermore, as shown in FIG. 1c, the light projecting parts 1T, 2T
It has been considered to alternately arrange the light receiving sections 1R and 2R, but if the surface reflectance of the object to be detected 3 is good, the reflected light will enter the light receiving sections of other photoelectric switches. It's inconvenient.

更に投光部を複数個並置した場合、これらが同
時に投光しないように投光タイミングをずらして
順次投光し、対応したタイミングの受光信号のみ
を選択通過させるようなゲート回路を設けて相互
の影響を避けようとする考え方もある。しかしな
がら、投光タイミングをずらし順次投光していく
ための制御回路が必要となり、かつこの制御回路
ら各々の投・受光部に同期信号を伝えるための電
気的接続が必要となるため、構成が複雑化し、結
線作業が煩雑になる他、それぞれの光電スイツチ
を独立に使えない欠点がある。
Furthermore, when multiple light emitters are arranged side by side, the light emitting timing is shifted so that they do not emit light at the same time, and a gate circuit is installed to selectively pass only the received light signal at the corresponding timing. There is also a way of thinking to avoid the influence. However, a control circuit is required to shift the light emission timing and sequentially emit light, and electrical connections are required to transmit synchronization signals to each of the light emitting and receiving parts of this control circuit, so the configuration is difficult. In addition to complicating the process and making the wiring work complicated, it also has the disadvantage that each photoelectric switch cannot be used independently.

(ハ) 発明の目的 本発明は上記に鑑み、光軸調整が容易に行なえ
るような投・受光範囲をもちながら、多数並置し
た場合に相互の電気的な接続を必要とせず、他の
光電スイツチの投射光などの雑音光による影響を
除去し誤動作を防止することができる光電スイツ
チを提供することを目的とする。
(c) Purpose of the Invention In view of the above, the present invention has a light emitting/receiving range that allows easy optical axis adjustment, does not require mutual electrical connection when a large number of them are arranged side by side, and can be used to connect other photoelectric devices. It is an object of the present invention to provide a photoelectric switch that can prevent malfunctions by eliminating the influence of noise light such as light projected by the switch.

(ニ) 発明の構成と効果 本発明によれば、パルス発振器と、このパルス
発振器から出力されるパルスに応じてパルス点灯
する発光素子と、前記発光素子からの光を受けて
受光信号を生じる受光素子と、この受光信号を前
記パルス発振器からのパルスによつてゲートする
ためのゲート回路と、このゲート回路を含み、複
数段からなり、ゲート回路に入力される信号を計
数する計数回路と、前記ゲート回路の出力と前記
計数回路の最終段の出力の不一致を検出する論理
回路と、この論理回路の不一致出力に応答して、
前記パルス発振器のパルス周期を短くする制御回
路とを備えているので、受光素子に雑音光が入射
して受光信号が生じたときに、自他の投射光が何
パルスにもわたつて重なるということが避けら
れ、雑音光による誤動作を防ぐことができる。ま
た、パルス周期が短くなる結果、応答時間を早め
ることが可能となる。
(d) Structure and Effects of the Invention According to the present invention, a pulse oscillator, a light emitting element that lights up in pulses in response to a pulse output from the pulse oscillator, and a light receiving device that receives light from the light emitting element and generates a light reception signal. a gate circuit for gating the received light signal with a pulse from the pulse oscillator; a counting circuit including the gate circuit and comprising a plurality of stages and counting signals input to the gate circuit; a logic circuit that detects a mismatch between the output of the gate circuit and the output of the final stage of the counting circuit; and in response to the mismatch output of the logic circuit,
Since it is equipped with a control circuit that shortens the pulse period of the pulse oscillator, when noise light is incident on the light receiving element and a light reception signal is generated, the projected light of the self and the other will overlap over many pulses. can be avoided, and malfunctions caused by optical noise can be prevented. Furthermore, as a result of the pulse period being shortened, the response time can be shortened.

さらに投・受光範囲を狭くする必要がないの
で、光軸の合わせやすさを損うことがなく、かつ
複数個の光電スイツチを並置する場合にそれら相
互間に電気的な接続を行なう必要もない。また、
遮光状態から入光状態に、また入光状態から遮光
状態と変化する時にのみパルス周期を短くし、通
常時は、パルス周期を長くできるので、発光素子
の長寿命化、消費電力の低減も図れる。
Furthermore, since there is no need to narrow the light emitting/receiving range, there is no need to compromise the ease of aligning the optical axis, and there is no need to make electrical connections between multiple photoelectric switches when they are placed side by side. . Also,
The pulse period can be shortened only when changing from a light-blocking state to a light-receiving state, or from a light-receiving state to a light-blocking state, and the pulse period can be lengthened during normal times, extending the lifespan of the light emitting element and reducing power consumption. .

(ホ) 実施例の説明 以下、本発明の一実施例について図面を参照し
ながら説明する。第2図において、投光部1T
は、低抗14,16,17,18,19,コンデ
ンサ15、ダイオード20,22、コンパレータ
21からなるRC自励式パルス発振器を備え、こ
の低抗14とコンデンサ15の時定数回路に直列
にトランジスタ13を接続して低抗11,12と
ともに制御回路を構成している。パルス発振器の
パルスは低抗23,24、トランジスタ25より
なる電流増巾回路をへて、更に低抗26をへて発
光ダイオード(LED)27に送られる。受光部
1Rは、フオトトランジスタ29と、抵抗28,
31〜34、コンデンサ30、コンパレータ35
からなる波形整形回路とを備え、フオトトランジ
スタ29の出力信号のうち、一定レベル以上の波
高値をもつ信号のみを波形整形回路により矩形波
に変換するようにしている。こうして矩形波にさ
れた受光信号は、5個のフリツプフロツプ36〜
40よりなるシフトレジスタに導びかれる。これ
ら各フリツプフロツプは、前記パルス発振器のパ
ルスをクロツクパルスとしており、このクロツク
パルスのタイミングで入力が行なわれるようにな
つている。そのため特に初段のフリツプフロツプ
36は、受光信号をパルス発振器のパルスにより
ゲートするゲート回路としての機能を果たしてい
る。各フリツプフロツプの出力はORゲート41
及びANDゲート42に導びかれており、受光信
号が5個連続してこのシフトレジスタに取り込ま
れたとき、ANDゲート42の出力が“H”にな
る。またORゲート41は5個のフリツプフロツ
プのうちいずれか1個の出力で“H”となつてい
る場合に“H”となり、全てのフリツプフロツプ
の出力が“L”のとき、すなわちクロツクパルス
の5個分の時間連続して受光信号がない場合に
“L”となる。従つてシフトレジスタはデイジタ
ル型の積分回路として機能していることが分る
(なお、アナログ型の積分回路を用いることをで
きるが、この場合にはORゲート41,ANDゲー
ト42の代わりには積分出力のレベル検出回路を
2個設け、一方の検出レベルを一定時間内に1個
の受光信号があつた場合の積分出力に対応させ、
他方の検出レベルを5個の受光信号が連続して生
じたときに達する積分出力に対応させておけばよ
い)。ORゲート41,ANDゲート42の出力は
NANDゲート43,44、NORゲート46、
NOT回路45よりなるフリツプフロツプに入力
される。また、シフトレジスタの初段のフリツプ
フロツプ36の出力と最終段のフリツプフロツプ
40の出力とを排他的論理和回路73に導いて、
この出力によつてトランジスタ13を制御するよ
うにしている。
(E) Description of Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In Fig. 2, the light projecting section 1T
is equipped with an RC self-excited pulse oscillator consisting of low resistors 14, 16, 17, 18, 19, a capacitor 15, diodes 20, 22, and a comparator 21, and a transistor 13 is connected in series with the time constant circuit of the low resistor 14 and capacitor 15. are connected together with the low resistors 11 and 12 to form a control circuit. The pulses from the pulse oscillator pass through a current amplification circuit made up of resistors 23 and 24 and a transistor 25, and then are sent to a light emitting diode (LED) 27 via a resistor 26. The light receiving section 1R includes a phototransistor 29, a resistor 28,
31 to 34, capacitor 30, comparator 35
Among the output signals of the phototransistor 29, only signals having a peak value above a certain level are converted into rectangular waves by the waveform shaping circuit. The light reception signal thus made into a rectangular wave is sent to five flip-flops 36 to 36.
40 shift registers. Each of these flip-flops uses the pulse from the pulse oscillator as a clock pulse, and input is performed at the timing of this clock pulse. Therefore, the flip-flop 36 in the first stage in particular functions as a gate circuit that gates the received light signal with the pulse of the pulse oscillator. The output of each flip-flop is OR gate 41
and an AND gate 42, and when five consecutive light reception signals are taken into this shift register, the output of the AND gate 42 becomes "H". Further, the OR gate 41 becomes "H" when the output of any one of the five flip-flops is "H", and when the output of all the flip-flops is "L", that is, the output of the five flip-flops is "H". It becomes "L" when there is no light reception signal for a continuous period of time. Therefore, it can be seen that the shift register functions as a digital type integrating circuit (an analog type integrating circuit can be used, but in this case, an integrating circuit is used instead of the OR gate 41 and the AND gate 42). Two output level detection circuits are provided, and the detection level of one corresponds to the integrated output when one received light signal is received within a certain period of time.
The other detection level may be made to correspond to the integral output reached when five light reception signals occur in succession). The output of OR gate 41 and AND gate 42 is
NAND gates 43, 44, NOR gate 46,
The signal is input to a flip-flop consisting of a NOT circuit 45. Further, the output of the flip-flop 36 in the first stage of the shift register and the output of the flip-flop 40 in the final stage are led to the exclusive OR circuit 73,
The transistor 13 is controlled by this output.

次に第2図のA〜G点の各信号波形がそれぞれ
示されている第3図のタイムチヤートを参照しな
がら動作について説明する。
Next, the operation will be described with reference to the time chart in FIG. 3, which shows the signal waveforms at points A to G in FIG. 2, respectively.

当初受光信号が生じていない場合、フリツプフ
ロツプ36〜40の出力は全て“L”となつてい
るとすると、排他的論理和回路73の出力は
“H”であるからトランジスタ13はオフであり、
コンデンサ15には抵抗71を通じて充電がなさ
れる。そのため抵抗71とコンデンサ15の時定
数により決まる周期でパルスが発生する。第3図
AはLED27の点灯電流の波形であるが、これ
はパルス発振器のパルスの波形でもあり、またシ
フトレジスタのクロツクパルスの波形でもある。
このLED27からの投射光が図示しない被検出
物体によつて遮られており、このときに他の光電
スイツチのLEDから発射されたパルス光がフオ
トトランジスタ29に入射して、第3図Bに示す
ような受光信号が生じたとする。この受光信号B
のタイミングとクロツクパルスAのタイミングと
が重なると、フリツプフロツプ36の出力Eは第
3図Eに示すように“H”となる。したがつて、
排他的論理和回路73の出力Dが“L”となつて
トランジスタ13がオンになり、コンデンサ15
の充電が早まる。そのため他の光電スイツチから
の次のパルス光とパルス発振器のパルスとが重な
らないことになり、次のパルスが生じたときフリ
ツプフロツプ36の出力Eは“L”、フリツプフ
ロツプ37の出力は“H”、他のフリツプフロツ
プ38〜40の出力は“L”となる。そのため排
他的論理和回路73の出力Dは“H”となつて、
パルス発振器のパルス周期はもとに戻る。
If the outputs of the flip-flops 36 to 40 are all "L" when no light reception signal is generated initially, the output of the exclusive OR circuit 73 is "H", so the transistor 13 is off.
Capacitor 15 is charged through resistor 71 . Therefore, pulses are generated at a period determined by the time constants of the resistor 71 and the capacitor 15. FIG. 3A shows the waveform of the lighting current of the LED 27, which is also the waveform of the pulse of the pulse oscillator and the waveform of the clock pulse of the shift register.
The projected light from this LED 27 is blocked by an object to be detected (not shown), and at this time, pulsed light emitted from the LED of another photoelectric switch enters the phototransistor 29, as shown in FIG. 3B. Suppose that such a received light signal is generated. This received light signal B
When the timing of the clock pulse A overlaps with the timing of the clock pulse A, the output E of the flip-flop 36 becomes "H" as shown in FIG. 3E. Therefore,
The output D of the exclusive OR circuit 73 becomes "L", the transistor 13 is turned on, and the capacitor 15
charges faster. Therefore, the next pulse light from another photoelectric switch and the pulse of the pulse oscillator do not overlap, and when the next pulse occurs, the output E of the flip-flop 36 is "L", the output of the flip-flop 37 is "H", The outputs of the other flip-flops 38-40 become "L". Therefore, the output D of the exclusive OR circuit 73 becomes "H",
The pulse period of the pulse oscillator returns to the original value.

このようにパルス周期を短するようにしている
ため、他の光電スイツチからのパルス光が入射し
たとしても他の光電スイツチの投光タイミングが
5パルスにわたつて重なることはなく、ANDゲ
ート42の出力が“H”となることはない。被検
出物体が移動し、遮光状態から入光状態になつて
自らの投射光が受光されるようになると、最初全
て“L”であつたフリツプフロツプ36〜40が
初段から順次“H”となつていくので、全てのフ
リツプフロツプが“H”となるまでの5パルスの
間、排他的論理和回路73の出力Dが“L”とな
つてパルス周期が短くなる。同様に入光状態から
遮光状態へと移つたときにもフリツプフロツプ3
6,40の出力は5パルスの間異るので、その間
パルス周期が短くなる。つまりこのような場合、
シフトレジスタを駆動するクロツクパルスの周期
が短くなるため、光電スイツチの応答時間が短く
なる。この短くなつたときのパルス周期が応答時
間を決めるため、必要とされる応答時間に設定し
ておけば、出力が反転するような状態でない通常
の状態ではパルス周期が長くなつてLED27に
流す平均電流が少なくなり、LED27自体の劣
化を防ぎ、かつ光電スイツチの低消費電力化に役
立つ。
Since the pulse period is shortened in this way, even if pulsed light from another photoelectric switch is incident, the light emission timing of the other photoelectric switch will not overlap for 5 pulses, and the AND gate 42 will not overlap. The output never becomes "H". When the object to be detected moves and changes from a light-shielding state to a light-receiving state and begins to receive its own projected light, the flip-flops 36 to 40, which were initially all "L", sequentially become "H" from the first stage. Therefore, during the five pulses until all the flip-flops become "H", the output D of the exclusive OR circuit 73 becomes "L" and the pulse period becomes short. Similarly, when transitioning from the light-receiving state to the light-blocking state, the flip-flop 3
Since the outputs of 6 and 40 differ for 5 pulses, the pulse period becomes shorter during that time. In other words, in such a case,
Since the period of the clock pulse driving the shift register is shortened, the response time of the photoelectric switch is shortened. The pulse period when this shortens determines the response time, so if you set it to the required response time, the pulse period will be long under normal conditions where the output is not inverted, and the average value flowing to the LED 27 will be reduced. This reduces the current, prevents deterioration of the LED 27 itself, and helps reduce power consumption of the photoelectric switch.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,b,cは光電スイツチの投光部と受
光部の位置関係を示す概略的な平面図、第2図は
本発明の一実施例の回路図、第3図は第2図のA
〜Gの各点における信号波形を示すタイムチヤー
トである。 1T,2T…投光部、1R,2R…受光部、3
…被検出物体、27…投光用LED、29…フオ
トトランジスタ(受光素子)、36〜40…フリ
ツプフロツプ、73…排他的論理和回路。
Figures 1a, b, and c are schematic plan views showing the positional relationship between the light emitting part and the light receiving part of the photoelectric switch, Figure 2 is a circuit diagram of an embodiment of the present invention, and Figure 3 is the same as Figure 2. A of
It is a time chart showing the signal waveform at each point of ~G. 1T, 2T...Light emitter, 1R, 2R...Light receiver, 3
... object to be detected, 27... LED for light projection, 29... photo transistor (light receiving element), 36 to 40... flip-flop, 73... exclusive OR circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 パルス発振器と、このパルス発振器から出力
されるパルスに応じてパルス点灯する発光素子
と、前記発光素子からの光を受けて受光信号を生
じる受光素子と、この受光信号を前記パルス発振
器からのパルスによつてゲートするためのゲート
回路と、このゲート回路を含み、複数段からな
り、ゲート回路に入力される信号を計数する計数
回路と、前記ゲート回路の出力と前記計数回路の
最終段の出力の不一致を検出する論理回路と、こ
の論理回路の不一致出力に応答して、前記パルス
発振器のパルス周期を短くする制御回路とを備え
たことを特徴とする光電スイツチ。
1 a pulse oscillator, a light emitting element that lights up in pulses in response to pulses output from the pulse oscillator, a light receiving element that receives light from the light emitting element and generates a light reception signal, and a light reception element that generates a light reception signal by receiving the light from the pulse oscillator. a gate circuit for gating by, a counting circuit including this gate circuit and consisting of multiple stages and counting signals input to the gate circuit, an output of the gate circuit and an output of the final stage of the counting circuit. 1. A photoelectric switch comprising: a logic circuit that detects a mismatch between the two; and a control circuit that shortens the pulse period of the pulse oscillator in response to the mismatch output of the logic circuit.
JP57162833A 1982-09-18 1982-09-18 Photoelectric switch Granted JPS5873889A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57162833A JPS5873889A (en) 1982-09-18 1982-09-18 Photoelectric switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57162833A JPS5873889A (en) 1982-09-18 1982-09-18 Photoelectric switch

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP55089555A Division JPS6051043B2 (en) 1980-06-30 1980-06-30 Photoelectric switch

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP12162593A Division JP2709017B2 (en) 1993-05-24 1993-05-24 Photoelectric switch

Publications (2)

Publication Number Publication Date
JPS5873889A JPS5873889A (en) 1983-05-04
JPH0445794B2 true JPH0445794B2 (en) 1992-07-27

Family

ID=15762105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57162833A Granted JPS5873889A (en) 1982-09-18 1982-09-18 Photoelectric switch

Country Status (1)

Country Link
JP (1) JPS5873889A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6487U (en) * 1987-06-18 1989-01-05

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4068130A (en) * 1976-11-16 1978-01-10 Chloride Incorporated Smoke detector with means for changing light pulse frequency

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4068130A (en) * 1976-11-16 1978-01-10 Chloride Incorporated Smoke detector with means for changing light pulse frequency

Also Published As

Publication number Publication date
JPS5873889A (en) 1983-05-04

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