JPH0444718U

JPH0444718U -

Info

Publication number: JPH0444718U
Application number: JP8763490U
Authority: JP
Priority date: 1990-08-22
Filing date: 1990-08-22
Publication date: 1992-04-16

Description

[Brief explanation of the drawing]

第１図はこの考案によるバイアス回路の実施例
を示す接続図、第２図〜第５図はこの考案を説明
するための図、第６図は従来のバイアス回路を示
す接続図である。図中、Ｄ１は第１のゼナーダイオード、Ｅ１か
らＥ６は電界効果トランジスタの端子、Ｅ７から
Ｅ９は端子、Ｒ１からＲ７は抵抗、ＲＴ１からＲ
Ｔ３は正特性サーミスタ、ＴＲ１とＴＲ２は電界
効果トランジスタである。なお、図中同一符号は
同一又は相当部分を示す。 FIG. 1 is a connection diagram showing an embodiment of a bias circuit according to this invention, FIGS. 2 to 5 are diagrams for explaining this invention, and FIG. 6 is a connection diagram showing a conventional bias circuit. In the figure, D1 is the first Zener diode, E1 to E6 are field effect transistor terminals, E7 to E9 are terminals, R1 to R7 are resistors, and RT1 to R
T3 is a positive temperature coefficient thermistor, and TR1 and TR2 are field effect transistors. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

a first field effect transistor, a gate terminal of the field effect transistor, and a first resistor, one of which is connected to the gate terminal of the first field effect transistor, and the other of which is grounded;
a second resistor having one end connected to the gate terminal of the first field effect transistor; a third resistor having one end connected to the drain terminal of the first field effect transistor; and a third resistor having one end connected to the drain terminal of the first field effect transistor. a first basic bias circuit consisting of a resistor and a source terminal grounded to the ground of the first field effect transistor; gate terminal of a field effect transistor,
a second basic bias circuit consisting of a fourth resistor, a fifth resistor, a drain terminal of a second field effect transistor, a sixth resistor, a source terminal of the second field effect transistor; and the first basic bias circuit. a positive polarity thermistor, one of which is connected to the other of the second resistor of the circuit and the other of the fifth resistor of the second basic bias circuit, and one of which is connected to the other of the positive thermistor, and the other is connected to the ground. a grounded Zener diode, a seventh resistor having one end connected to the other Zener diode and the other end connected to a negative power supply terminal, and the other of the third resistor of the first basic bias circuit. and the second
A bias circuit comprising a positive power supply terminal connected to the other of the sixth resistor of the basic bias circuit, and a ground terminal.