JPH0444696A - Static ram - Google Patents

Abstract

PURPOSE:To directly investigate the holding characteristic of information by providing a function to supply an operational voltage selectively to a power supply line to which a static MOS memory cell is coupled. CONSTITUTION:Between respective complementary data lines D0, -D0, D1, -D1 and the power supply line to which a power supply terminal VCC for peripheral circuit is coupled, P-channel type load MOS FET Q5-Q8 are provided to be operated as resistors by supplying the ground potential of a circuit to the gate normally. Since these MOSFET Q5-Q8 are formed while reducing the sizes comparatively small, small conductance can be obtained. These MOSFET Q5-Q8 are respectively equipped with P channel type load MOSFET Q9-Q12 parallelly.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to static RAM (random access memory), and relates to a technique that is effective when applied to RAM using high resistance load type memory cells. be.

[Conventional technology]

Once a memory chip is formed in the shape of a substrate on a semiconductor wafer, an electrical test is performed by applying a probe to the bonding pad of the memory chip knob to check whether the memory chip operates as desired. conduct. A memory tester is used for such electrical tests. Regarding memory testers, there is, for example, "Microcomputer Handbook J, pages 738 to 741, published by Ohmsha on December 25, 1985.

[Problem to be solved by the invention]

Unlike a logic LSI, a RAM has a simple basic operation of only writing and reading data. However, since it is densely integrated in the RAM, malfunctions are likely to occur due to mutual interference between lines and cells. Various algorithms for detecting such defects have been devised, but as memory capacity increases, shortening test time has become an important issue.

SUMMARY OF THE INVENTION An object of the present invention is to provide a static RAM with a function that allows the operational stability of an M,OS memory cell to be easily and quickly checked.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the operating voltage can be selectively supplied to the power supply line to which the static MOS memory cell is coupled.

[For production]

According to the above-described means, after writing predetermined data into a memory cell, the operating voltage of the memory cell is cut off for a certain period of time, thereby making it possible to examine the information retention characteristics.

[Embodiment] FIG. 1 shows a block diagram of an embodiment of a static RAM according to the present invention. Each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon using a known semiconductor integrated circuit manufacturing technique. Although the circuit block in the figure is not particularly limited, it shows the state of a memory chip formed on a semiconductor wafer in the shape of a substrate. Therefore, the external terminal is used as a bonding pad.

Address signal AX/AY consisting of multiple bits is transmitted to address buffer ADB. The address signal taken into this address buffer ADB is sent to the decoder DCH.
can be conveyed to. Of the decoders DCR, a decoder circuit corresponding to the X-system address signal AX decodes the address signal AX to form a word line selection signal. The word line selection signal is not particularly limited, but word driver D
This will be communicated to the RV. By providing such a word driver DRV, a word line having a relatively large load capacitance due to the coupling of a large number of memory cells can be switched between selection and non-selection at high speed.

The memory array M-ARY is configured by a matrix arrangement of static type MOS memories as described below. That is, each memory cell is arranged at the intersection of a data line and a word line.

Of the decoders DCR, the decoder circuit corresponding to the Y-system address signal AY decodes the address signal AV to form a data line selection signal. The data line selection signal is transmitted to the Y selection circuit (column switch) YSW. The Y selection circuit YSW selects the data line of the memory array M-ARY from the common data line CD according to the data line selection signal.
Connect to.

The read signal from the common data line CD is supplied to the sense amplifier SA, where it is amplified at high speed. The amplified output signal of the sense amplifier SA is sent out from the output terminal Dout through the data output circuit DOB. In the figure, the sense amplifier SA and the data output circuit DOB are represented as one block 5AdxDOB.

Timing control circuit TG receives chip select signal C8 and write enable signal WE, and outputs internal control signal W.
E, sense amplifier operation timing signal sc, data output control signal doc, data input control signal dic, etc. are formed.

The data input circuit DIB is supplied from the input terminal Din.
In response to the received write data, a write signal is transmitted to the common data line CD.

In order to easily and quickly determine the information retention characteristics of memory cells in such a state-of-the-art RAM, the memory array M-AR is
Power supply terminals vCC and V for Y and other peripheral circuits, respectively.
A CCM will be established. That is, address buffer ADB
The power supply lines of peripheral circuits such as the decoder circuit R and the decoder circuit R are coupled to the power supply terminal VCC. On the other hand, memory array M-
The power supply line to which the static MOS memory cell of ARY is connected is a power supply terminal VC provided separately from the above peripheral circuit.
Combined with CM.

Although not particularly limited, when the RAM is assembled, the above power supply terminals (bonding bathode > VCC and V
It is connected to a common power supply terminal (lead) with the CCM by wire bonding or the like.

Therefore, power can be independently supplied from the power supply terminals as described above only when the RAM is completed on a semiconductor wafer. That is, in the probing process, an information retention test of the memory cell is performed by selectively supplying power using the terminals VCC and VCCM.

FIG. 2 shows a block diagram of an embodiment of a static RAM according to the present invention. The RAM in the same figure is
It is formed on a single semiconductor substrate, such as single crystal silicon, using well-known CMO3 integrated circuit technology.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal N-type silicon. P channel MO3
The FET has a source region, a drain region formed on the surface of the semiconductor substrate, and a gate made of polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. Consists of electrodes. The N-channel MO3FET is formed in a P-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of P-channel MO3FETs formed thereon. The P-type well region constitutes the substrate gate of the N-channel MOS FET formed thereon.

In the figure, a P-channel MO3FET is distinguished from an N-channel MO3FET by adding an arrow to its channel (back gate) portion.

The memory array MARY is composed of a plurality of memory cells MC arranged in a matrix, word lines WO to Wn, and complementary data lines DO, DO to DI, and Di. Each of the memory cells MC has the same configuration, and as one specific circuit is shown as a representative, the gate and drain are cross-connected to each other, and the source is connected to the circuit ground point (G
N-channel storage MO3FET coupled to
QI, Q2, and high resistance R1, R, 2 made of a polysilicon layer provided between the drains of the MO3FETs QI, Q2 and the power line connected to the power supply terminal VCCM as described above. Contains.

An N-channel transmission gate MO is connected between the common connection point of the MO3FETs QI and Q2 and the complementary data lines Do and DO.
SFETQ3. Q4 is provided. Transmission gate MO3FETQ3 of memory cells arranged in the same row. The gates of Q4, etc. are commonly connected to the corresponding word lines WO-Wn, etc. shown in the example, and the input/output terminals of the memory cells arranged in the same column are respectively shown in the example. They are connected to a corresponding pair of complementary data lines (bit lines or digit lines) DO, DO and DI, Dl, etc.

In the memory cell, MOSFETs QI and Q2 and resistors R1 and R2 constitute a kind of flip-flop circuit, but the operating point in the information retention state is quite different from that of a flip-flop circuit in the ordinary sense. That is, in the above memory cell) kk/IC, in order to reduce power consumption, its resistor R1 is set to MO8-FETQ.
The resistance value is set to be extremely high enough to maintain the gate voltage of MO3FET Q2 at a voltage slightly higher than its threshold voltage when MO3FET Q2 is turned off.

Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistors R1 and R2 are made to have a high resistance enough to compensate for the drain leakage current of the MOSFETs QI and Q2. The resistors R1 and R2 have a current supply capacity sufficient to prevent information charges stored in the gate capacitance (not shown) of the MOS F BTQ2 from being discharged.

According to this example, if the RAM is 0MO3-
Although manufactured by IC technology, the memory cell MC is composed of an N-channel MO3FET and a polysilicon resistance element as described above.

The memory cell and memory array of this embodiment can be made smaller in size than when a P-channel MO3FET is used in place of the polysilicon resistance element. That is, when using a polysilicon resistor, the driving MO3FET
It can be formed on the gate electrode of QI or G2, and its size can be reduced. Then, like when using a P-channel MO3FET, the drive MOS F
Since it is not necessary to separate it from ETQl and G2 by a relatively large distance, no wasted blank space is generated.

In the figure, although not particularly limited, each complementary data line D
O, Do, Dl, Di and power supply terminals V for the above peripheral circuits
A P-channel type load MO3FET Q5, which acts as a resistance element by constantly supplying the circuit ground potential to its gate, is connected to the power supply line to which CC is connected.
~Q8 is provided. These MO3FETQ5~Q8
is made relatively small in size so that it has a small conductance. P-channel type loads MO3FETs Q9 to Q1.2 are provided in parallel to these loads MO3FETs Q5 to Q8, respectively. These load MO3FETs Q9 to Q12 are formed relatively large in size, so that
It is made to have a relatively large conductance. MO when the above MOS FETQ9 to Q12 are in the on state
Combined conductance of 3FETQ5 to Q8, transmission gate MO3FET of memory cell MC, and MO3FE for storage
The ratio of T to the composite conductance of the memory cell MC is
In the read operation, complementary data lines DO1DO, Di, Dl, etc. are selected to have a desired potential difference according to the stored information. Each load above MO3FETQ9
~The gate of Q12 is connected to the power supply terminal v during write operation.
Internal write signal WE set to high level like CC
is supplied. As a result, during the write operation, the load MO3FETs Q9 to Q12 are turned off.

Therefore, the load means for the complementary data line in the write operation is the MO3FETQ5 with small conductance.
~Q8 only.

In the figure, the word line WO is selected by the decoder DCR and the drive circuit DRV as described above.
) The gate circuit G1 serves as an X-system decoder XDCR and a drive circuit DRV. This also applies to word lines Wn shown as other representatives.

The X-system address decoder XDCR is composed of mutually similar NOR gate circuits Gl, 02, etc.

The input terminals of these NOR gate circuits Gl, 02, etc.
A predetermined combination of internal complementary address signals formed by address buffers XA and DB receiving an X-system external address signal AX consisting of a plurality of bits is applied.

Between the complementary data line Do and the common complementary data line CD in the memory array, an N-channel MO3FET QI 3 and a P-channel MO3F'ET are connected in parallel.
A CMOS switch circuit consisting of QI 4 is provided.

Other data lines DO and DI.

Dl, etc. are also connected to the corresponding common complementary data lines CD, CD by CMOS switch circuits similar to those described above. These CMOS switch circuits constitute the Y selection circuit (column switch) YSW shown in FIG. 1 above.

N-channel type MO3FETQI that constitutes the column switch YSW 2. Selection signals YO and Y1 formed by a Y address decoder YDCR are supplied to the gates of Ql5 and Ql7°QL9, respectively. The above P-channel type MO3FETQI 4. Ql 6 and G18. Q2Of7) gate receives the selection signal YO,
Output signals of CMOS inverter circuits Nl and N2 receiving Yl are supplied.

The Y-system address decoder YDCR is composed of NOR gate circuits G3, G04, etc., each having a similar configuration. These NOR gate circuits G3. G4 and the like are applied with a predetermined combination of internal complementary address signals formed by a Y address sofa YADB that receives a Y-system external address signal AY consisting of a plurality of bits.

In this embodiment, although not particularly limited, an internal write signal WE is supplied to the gates of the common complementary data lines CD, CD in order to speed up the write operation, thereby realizing a high-speed write recovery operation. To do this, a P-channel type load (pull-up) MOSFETQ
21 and Q22 are provided.

The common complementary data lines CD, CD are connected to an input terminal of a sense amplifier SA that constitutes a read circuit and an output terminal of a data input circuit DIH that constitutes a write circuit.

An output terminal of the data output circuit DOB is connected to an output terminal Dout that outputs a read signal. Data input circuit D
An input terminal of IB is connected to a data input terminal Din to which write data is supplied.

Sense amplifier SA performs a highly sensitive sensing operation.

The sense amplifier SA performs an amplification operation for a certain period of time when the activation pulse SC is supplied. That is, the operations of sense amplifier SA and data output circuit DOB are controlled by activation signals sc and doc generated from timing control circuit TG. Sense amplifier SA and data output circuit DO
B, activated when in read mode, common complementary data lines CD and C when it is activated
The data signal supplied to D is differentially amplified, and the amplified signal is output from the output terminal Dout. Data output circuit DO
B puts its output terminal Dout into a high impedance state or a floating state when it is disabled by the control signal doc.

The operation of the data input circuit DIB is controlled by the control signal dic in the write mode, and when the data input circuit DIB is in the operating state, a complementary data signal corresponding to the input data supplied to the input terminal Din is sent to the common complementary data line. CD
, output to CD. The data input circuit DIB has a pair of output terminals in a high impedance state or a floating state when it is inactive by the control signal dic.

The timing control circuit TC receives control signals from the external terminals WE and C8, and outputs the internal control timing signals sc,
Form doc, dic, WE, etc.

the above! In the RAM of the configuration, the memory array MA R,
Logic "0" is written to all memory cells of Y. For example, to explain the memory cell shown as a representative example in the figure, a low level write signal is supplied from a non-inverted complementary data line DO, a high level write signal is supplied from an inverted complementary data line DO, and a memory cell MO3FETQ
I is turned on and storage MO3FETQ2 is turned off.

Writing similar to the above is performed for all memory cells, and all stored information is set to logic "0".

After this, the operating voltage VCCM for the memory array M-ARY
Cut off the power supply to the At this time, the charging current from the high resistance is stopped for each memory cell, so
Similar to the information retention operation of the dynamic memory cell, the information retention operation is performed using the storage charge accumulated in the gate capacitance of the storage MOSFET QI or the like. At this time, if the high resistance is defective and its resistance value is set relatively small, the information charge held in the gate of the MOS FETQ 1 etc. will be discharged within a relatively short time. Alternatively, if a leakage current flows between the source or drain of the transmission gate MO3FET Q3 or Q4 and the substrate, the information storage charge will be lost in the same manner as described above.

In normal memory cells, after a certain period of time has elapsed to hold the storage charge accumulated in the gate capacitance, the operating voltage is supplied again from the power supply terminal VCCM, and logic "0" is read out from all memory cells. confirm. Similarly, after writing logic "1" to all memory cells and stopping the supply of operating voltage VCCM to the memory cells for a certain period of time, all memory cells write logic "1".
” is read out.

If it is a high resistance or transmission game (like the one above) MOSFET
If there is a leakage current between the source, drain, and substrate of the
It can be detected by inverting it and reading it out like "0".

A test that tests the information retention characteristics of such memory cells and detects malfunctions (defects) due to mutual interference between each line such as a word line or data line or between cells only for RAM that is determined to be good. perform an action. In this case, since those with poor information retention characteristics are screened out as described above, it is possible to obtain highly reliable test results while shortening the overall test time. In this way, since the detection rate of defective RAMs in the broaching process can be increased, the selection yield can be increased.

FIG. 3 shows a block diagram of another embodiment of the static RAM according to the present invention.

In this embodiment, a switch MO3FETQM is used to selectively supply the operating voltage to the memory array M-ARY. That is, power supply terminal VCC and memory array M
-A P-channel MO3F,
An ET type switch MO3FETQM is provided. This M.O.
The gate of 5FETQM is coupled to control terminal VCCM'. The resistor R provided between the gate of MO3FETQM and the ground potential point of the circuit is used to pull down and turn on the switch MO3FETQM steadily when the control terminal VCCM is in a floating state. .

With this configuration, testing of the information retention characteristics of the memory cell can be performed not only during the probing step but also after the RAM is assembled.

That is, by providing the control terminal VCCM' as an external terminal (test terminal) and supplying a high level to it, it is possible to turn off the switch MO3FETQM and stop supplying the operating voltage to all memory cells.

The control signal transmitted to the gate of MO3FETQM can be supplied directly from an external terminal as in the embodiment shown in the same figure, or
Use a specific address terminal and set its voltage level higher than the normal high level (5V), for example! , OV may be used to generate a control signal VCCM' which is set to a high level when a high voltage such as VCCM' is supplied. When such a three-value input circuit is used, there is no need to increase the number of external terminals.

The effects obtained from the above examples are as follows. That is, it is possible to selectively supply an operating voltage to the power supply line to which <11 static type MOS memory cells are coupled,
By cutting off the operating voltage of the memory cell for a certain period of time after writing predetermined data into the memory cell, it is possible to directly examine the information retention characteristics.

(2) By performing the conventional operation test on the RAMs selected according to <11 above, it is possible to substantially shorten the time and increase the efficiency of selection.

(3) By selectively supplying the operating voltage to the power supply line to which the static MOS memory cell is connected via a switch element, the number of external terminals does not need to be increased and the memory can be used even after the RAM is completed. The advantage is that the information retention characteristics of cells can be directly investigated.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, in the embodiment of FIG. 1, the power supply terminal V for the memory array M-ARY
The configuration may be such that the CCM is connected to a dedicated external terminal.

In this case, in addition to the blobbing process, similar tests can be performed during shipping inspection after assembly is completed. In addition, by providing such a terminal, 1. During the pantry hack amplifier operation, the hack-up voltage can be supplied only to memory cells that perform information storage operations. Alternatively, the stability of the memory cell may be evaluated by adding a function to set all word lines to a non-selected level and testing data retention characteristics.

The load means in the static MOS memory cell is
In addition to using high-resistance polysilicon as described above, a completely static type using a P-channel MO5FET whose current supply capacity is set to be small as described above may be used. Further, the load means provided on the complementary data lines of the memory array are two MOS F E
In addition to using T, a single MOS FET may be used. As described above, the configuration of the memory array and the specific circuit configuration of its peripheral circuits can take various embodiments. For example, the peripheral circuit may be constructed from a combination of an 0M03 circuit and a bipolar transistor. The MOSFET referred to in this invention refers to an insulated gate type field effect transistor having various types of gate insulating films, including those in which the gate insulating film is composed of an oxide film.

The present invention can be widely used in RAMs using static MOS memory cells, and may be built into various digital integrated circuits such as one-chip microcomputers.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, after making it possible to selectively supply the operating voltage to the power supply line to which the static MOS memory cell is coupled, and writing predetermined data into the memory cell,
Information retention characteristics can be directly investigated by cutting off the operating voltage of a memory cell for a certain period of time.

[Brief explanation of drawings]

FIG. 1 is a professional diagram showing an embodiment of a static RAM according to the present invention, FIG. 2 is a circuit diagram of a main part showing an embodiment of a static RAM according to the invention, and FIG. FIG. 2 is a diagram showing another embodiment of the static RAM according to the present invention. ADB, XADB, YA, DB... Address number 7, DCR, XDCR, YDCR... Decoder, DRV
...Drive circuit, ysw...Y selection circuit, TG...Timing control circuit, SA...Sense amplifier, DIB...Data output circuit, DIB...Data input circuit, MC...Memory cell, Nl, N2... Inverter circuit, G1-G5・
・Noah gate circuit.

Claims (1)

Claims: 1. A static RAM characterized by having a function of selectively supplying an operating voltage to a power supply line to which a static MOS memory cell is coupled. 2. A static type RAM characterized in that a bonding pad is provided independent of a power supply line to which a static type MOS memory cell is coupled. 3. A static type RAM having a function of supplying an operating voltage to a power supply line to which a static type MOS memory cell is coupled via a switch element that is switch-controlled by a control signal supplied from a control terminal. .