JPH0444337A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To optimize the performance of an LSI in a high speed region and a low power consumption region by controlling a current of a DC component circuit flowing in the LSI corresponding to using environmental conditions of the LSI by a signal out of the LSI. CONSTITUTION:An LSI 11 has an input terminal 16 of input means for inputting a control signal for controlling a current of a DC component circuit out of the LSI 11, a switch S of control means for controlling the current flowing to the circuit, and current sources IA14, IAL15. If the LSI is operated at a high speed (environmental conditions A), the switch S is set to A by a signal out of the LSI, and a DC current of IA flows. Then, if it is operated at a low speed (environmental conditions B), the switch S is set to B by a signal out of the LSI, and a DC current of IAL (IAL<IA) flows. When the current is controlled in this manner, power consumption at the time of the conditions A is P2, which is the same as a conventional LSI, but the power consumption at the time of the condition B becomes P1l (P1l<P1), and the power consumption is considerably reduced as compared with the conventional LSI.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as LSI).
In particular, the present invention relates to LSI circuits and chip configurations that cover a wide performance range.

[Conventional technology] Today, the performance required of LSIs is becoming more and more diverse, and the problem has arisen that it is necessary to develop a wide variety of LSIs to meet this demand. It is hoped that this will be covered.

First, a conventional LSI will be explained with reference to FIG.

The internal circuit of an LSI consists of a circuit in which the current value does not change depending on the clock frequency, that is, a part in which direct current flows steadily (hereinafter referred to as a DC branch circuit), and a part in which the current value does not change depending on the clock frequency. Conventional LSIs can be divided into circuits where the voltage changes, that is, parts where AC current flows only when one circuit operates (hereinafter referred to as AC branch circuits). It is classified as either containing one or both types of circuits.

Hereinafter, as shown in FIG. 2(a), a case will be described in which an LSI includes at least one part in which a direct current flows steadily.

The power consumption of the LSI shown in Figure 2(a) is as shown in Figure 2(b).
As shown in , it changes in proportion to the clock frequency. Further, since the power consumed by the DC branch circuit is PO, the power of PO is consumed even when the clock frequency is zero, that is, when the LSI is in a stopped state.

Here, for example, consider a case where there are two environmental conditions for LSI use.

One is when you want to operate the LSI at high speed (environmental condition A
), and the LSI operates at a clock frequency f2. The other case is when the operating frequency is low but the power consumption of the LSI is desired to be kept low (environmental condition B), and the LSI operates at the clock frequency f1 (fl<f2).

The power consumption when the LSI operates at high speed (environmental condition A) is P2, and the power consumption when it operates at low speed (environmental condition B) is Pl, and the difference between P2 and Pl is the AC component of the power consumption. This is only the decrease in .

Therefore, if the proportion of the DC component of the power consumption of the LSI is relatively large, the power consumption cannot be effectively reduced even if the clock frequency is lowered to fl.

In other words, in the case of this conventional example, the LSI can be used under environmental condition A, but cannot be used under environmental condition B due to its large power consumption.
It is not possible to respond to different operating environment conditions.

As a conventional technique for covering multiple performance areas with one product type, there is a proposal for a technique that allows selection of normal power consumption and low power consumption.

Conventional methods for selecting low power LSI include, for example,
LSI shown in Japanese Patent Application Laid-Open No. 63-104443
As shown in the figure, a clock frequency divider circuit and a power supply voltage divider circuit are provided inside the LSI, and their outputs are selected for each of the plurality of functional blocks that make up the LSI using information set in a programmable register. For example, this can be done by making it possible to apply a voltage. As a result, when the operating state of the LSI chip changes, the clock frequency and power supply voltage supplied to each functional block can be selected as necessary, so power consumption can be dynamically controlled. An LSI with low power consumption is realized.

However, since the power supply voltage is changed, there is a problem in that the amplitude of the high-power signal changes.

[Problems to be Solved by the Invention] The above-mentioned conventional technology selects the clock frequency and power supply voltage inside the LSI based on the information in the register inside the chip, and achieves low power consumption of the LSI. and the method of selecting the power supply voltage, 1
There are limits to the performance range covered by each type of LSI.

For example, when the above LSI is used in two performance areas: a high speed, high power consumption area (hereinafter referred to as the high speed area) and a low speed, low power consumption area (hereinafter referred to as the low speed area),
The above LSI is optimally designed to be used in one performance area (the amplitude of the output signal is designed in one area), so if it is used in the other performance area, the performance will drop. . There are problems like this.

An object of the present invention is to provide an LSI that can accommodate various power consumption conditions and clock frequency conditions with one type and covers a wide performance range.

[Means for Solving the Problems] The current flowing inside the LSI is the sum of the current in a circuit whose current value depends on the clock frequency and the current in a circuit whose current value does not depend on the clock frequency. The above purpose is to control the current flowing inside the LSI that does not depend on the clock frequency from outside the LSI.
Realized.

Therefore, in a semiconductor integrated circuit device having one or more circuits whose current value does not change even if the clock frequency changes, the current of the circuit in the semiconductor integrated circuit device is controlled from outside the device. It has an input means into which a control signal is input, and a control means for controlling the current of the circuit, and the current value is made variable.

[Function] The current consumed by an LSI is divided into the power of a circuit whose current value changes depending on the clock frequency (hereinafter referred to as an AC circuit) and the power of a circuit that does not depend on the clock frequency (hereinafter referred to as a DC branch circuit). The electric power can be divided into two types:

The power of the AC branch circuit increases or decreases approximately in proportion to the clock frequency input from outside the LSI, but the power of the DC branch circuit remains constant regardless of the clock frequency.

Therefore, when the same LSI is used in two cases, a high-frequency clock and a low-frequency clock, simply changing the input clock will cause the power consumption of the LSI with the low-frequency clock to be lower than the power consumption of the LSI with the high-frequency clock. In this case, only the power of the AC circuit is reduced, and the power of the DC branch circuit is not reduced, so a large reduction in power cannot be achieved.

However, depending on the environmental conditions in which the LSI is used (depending on whether it is a high-frequency clock or a low-frequency clock), the performance of the LSI can be improved by controlling the current of the DC branch circuit that flows inside the LSI using signals external to the LSI. It becomes possible to optimize in the high speed area and low power consumption area.

For example, when used in a high-speed area, a control signal that causes a large DC current to flow through a DC branch circuit is applied externally to the LSI to achieve high speed, and when used in a low-power consumption area, The control signal that reduces the current in the DC branch circuit is
By applying power to the LSI, it is possible to reduce the power consumption of the DC circuit and achieve a significant reduction in power consumption.

(The following is a blank space) [Example] Hereinafter, an example of an LSI according to the present invention is shown in FIGS. 1 and 3 to 3.
This will be explained with reference to FIG.

FIG. 1 is a block diagram of an embodiment of a semiconductor integrated circuit device according to the present invention.

L which is a semiconductor integrated circuit device according to the present invention shown in FIG.
SIII has a DC branch circuit 12 and an AC circuit 13, which are operated by a power supply CC.

The LSIII has an input terminal 16, which is an input means to which a control signal for controlling the current of the DC branch circuit is input from outside the LSIII, and a current flowing through this circuit.

A switch S, which is a control means, and a current source lA
14, with IAL15.

Switch S connects these two current sources IAI4 and IAL1
Perform the switch in step 5.

It will be explained next that the embodiment of the present invention shown in FIG. 1 can accommodate two usage environmental conditions (environmental conditions A and B).

As shown in FIG. 1(a), in this embodiment as well, the internal circuit can be divided into a part where a direct current flows constantly and a part where an alternating current flows only when the circuit is in operation.

The present embodiment is characterized in that the direct current flowing through the internal circuits or input/output circuits of the LSI can be controlled by signals from outside the LSI.

First, when the LSI is operated at high speed (environmental condition A), switch S is turned to A to flow the DC current of IA by a signal from outside the LSI, and when the LSI is operated at low speed (
For environmental condition B), the switch S is turned to B in response to a signal from outside the LSI, and a direct current of IAL (IAL<IA) is caused to flow.

When the current is controlled in this way, the power consumption under environmental condition A is P2, which is the same as a conventional LSI, but the power consumption under environmental condition B is PIL (PIL (Pi),
Compared to conventional LSIs, it is possible to significantly reduce power consumption. This is possible because the DC current required when the circuit operates at low speed is generally smaller than the DC current required when the circuit operates at high speed.

Therefore, the power consumption in the case of environmental condition B is the DC component P
Since it can be used as OL, the total power consumption can be reduced to P
Compared to conventional LSI,
It can be seen that power consumption can be significantly reduced.

In this way, by controlling the direct current flowing through the LSI's internal circuits or input/output circuits using signals from outside the LSI, even in environmental conditions A where high speed is required, low power consumption is required. Since the same LSI can be used in B, the LSI of -
This makes it possible to meet the above two usage environment conditions.

Therefore, it has the effect of significantly reducing the time and cost of LSI development.

FIG. 3 shows an embodiment in which the LSI 31 is provided with a current control pin P, which is a means for inputting a control signal to control the current, in order to realize the above embodiment.

The LSI 31 of this embodiment has a current control pin P which is an input terminal.
As shown in FIG. 3(b), the characteristics of the LSI 31 take on two states depending on the input signal to the control pin P.

Next, the operation will be explained.

The control pin P allows the performance of the LSI to be controlled to the characteristics shown in (b). That is, the control pin P
When set to the first power supply voltage (V CC ), the LSI enters the high-speed mode and operates at one frequency fH, and the power consumption at this time becomes P)l. On the other hand, connect the control pin P to the ground voltage (GND
), the LSI goes into low-speed mode and the frequency fL
(fL<fH), and the power consumption at this time is PL
(PL<PH).

FIG. 4 is a circuit diagram showing an embodiment of the control signal input terminal and control means for realizing the embodiment described above, together with a DC branch circuit.

The configuration of the circuit is as follows.

In this embodiment, an N-type channel MOS transistor is used as the first conductivity type MOS transistor which is a variable impedance element.
A P-type channel MOS transistor is used as the second conductivity type MO5I transistor.

An input terminal 14 to which an external control signal that controls the current of a DC branch circuit in the LSI is input is connected to the gate terminal of the first N-type channel MOS transistor 101, and an inverter that generates an inverted signal of the control signal. 120, and first and second P-type channels M, which are variable impedance elements.
Gate terminals which are control terminals of O3 transistors 104 and 105 are connected, and source terminals of the first and second P-type channel MOS transistors 104 and 105 are connected to a first power supply VCC.

The drain terminal of the first P-type channel MOS transistor 104 is connected to the collector terminal, which is the current input terminal, of the first bipolar transistor 107, which is the first semiconductor element, and the second P-type channel MoS transistor ( A drain terminal of the PMO 105 (hereinafter referred to as PMO3) is connected to a collector terminal, which is a current input terminal, of a second bipolar transistor 108, which is a semiconductor element.

An emitter terminal that is a current output terminal of the first bipolar transistor 107 and an emitter terminal that is a current output terminal of the second bipolar transistor 108 are connected.

First N-type channel MOS transistor (hereinafter, NMO
5) 101 is connected to the emitter terminal, and the source terminal is connected to the second power supply GND.

The base, which is the input terminal of the second bipolar transistor 108, is connected to the third power supply VBB.

The base terminal of the first bipolar transistor 107 becomes the input terminal 43 of the LSIII, the collector of the first bipolar transistor 107 becomes the first output terminal 41 of the LSIII, and the collector of the second bipolar transistor 108 becomes the input terminal 43 of the LSIII. This becomes the second output terminal 42 of LSll.

In this embodiment, for example, when the control signal is set to the first power supply voltage level vCC, the NMOS101°PMO810
4,105 is turned on. At this time, the current flowing from the first power supply vCC to the second power supply is IA. Also, the amplitude V OUT of the output signal is as follows, assuming that the channel resistances of PMO3103 to 106 are each 2R, VOUT=I A
tree R, and the DC power consumption of the circuit is POLC
= VCC tree IA.

On the other hand, when the control signal is set to the second power supply voltage level GND, NMO8IOL and PMO8104°105 are turned off. At this time, the current flowing from the first power source to the second power source is IAL=IA/2.

Moreover, the amplitude V 0LIT of the output signal is VOUT=I
AL* 2R=(IA/2)3k 2R= IA* R
This is the same as when the control signal is vCC.

What is the DC power consumption of the circuit?

POC=VCCI IAL=VCC main (IA/2), and the control signal P is half of the value when it is vCC.

In this way, according to the circuit of this embodiment, it is possible to control the power consumption by halving it without changing the output amplitude using the control signal.

FIG. 5 shows another embodiment in which the current in the DC branch circuit of the internal circuit is controlled. This embodiment is different from the above embodiments in that the control signal is not directly applied to the gate of MO5, but the current in the DC branch circuit is controlled by the frequency of the clock signal.

The circuit configuration is as follows.

In this embodiment, an N-type channel MOS transistor is used as the first conductivity type MOS transistor, which is a variable impedance element, and a P-type channel MOS transistor is used as the second conductivity type MOS transistor. There is.

The control signal for controlling the current is a clock signal, and means for inputting this control signal are a clock input pin CK, which is an input terminal, and first and second frequency/voltage converters, which are signal converters.

The clock input pin CK is connected to first and second frequency/voltage converters (f-V converters) 110, 111, and the output terminal of the first frequency/voltage converter 110 is connected to a third variable impedance element. A certain first N-type channel MOS
connected to the gate terminal of the transistor 101 and connected to the second
The output terminal of the R-wavenumber/voltage converter 111 is connected to the gate terminals of first and second P-type channel MO5 transistors 104 and 105, which are first and second variable impedance elements.

The source terminals of the first and second P-type channel MO5 transistors 104, 105 are connected to a first power supply VCC.

The train terminal of the first P-type channel MOS transistor 104 is connected to the collector terminal of the first bipolar transistor 107, which is the first semiconductor element, and the drain terminal of the second P-type channel MOS transistor 105 is connected to the collector terminal of the first bipolar transistor 107, which is the first semiconductor element. It is connected to the collector terminal of a second bipolar transistor 108, which is a second semiconductor element.

The emitter terminal of the first bipolar transistor 107 and the emitter terminal of the second bipolar transistor 108 are connected.

The drain terminal of the first N-type channel MO3 transistor 101 is connected to the emitter terminal, and the source terminal is connected to the second power supply GND.

The base of the second bipolar transistor 108 is connected to the third power supply VBH.

The base terminal of the first bipolar transistor 107 becomes the input terminal 53, the collector of the first bipolar transistor 107 becomes the first output terminal 5↓, and the collector of the second bipolar transistor 108 becomes the second output terminal 53. This becomes the terminal 52.

Next, the operation will be explained.

In the first frequency/voltage converter 110, the output voltage has a positive characteristic with respect to the input frequency, and in the second frequency/voltage converter 111, the output voltage has a negative characteristic with respect to the input frequency. When the clock frequency is fH, the output voltage of the first f-V converter 110 is VH, and the output voltage of the second f-V converter 111 is VL.

At this time, the channel resistance of the NMO 8101 becomes R, and a current IA flows from the first power supply VCC to the second power supply GND.

On the other hand, when the clock frequency is fL, the first f-V converter 1
The output voltage of 10 is VL, and the second f-■ converter 111
The output voltage of is VH. At this time, the channel resistance of NMO5101 is greater than R, so the first power supply VBB
A current IA smaller than the current IA is applied from the second power supply GND to the second power supply GND.
L flows.

In this way, by controlling the DC current of the internal circuit by the clock frequency, when the frequency is low, the DC component of power consumption becomes small, and low power consumption is realized.

In addition, the channel resistance of the PMOs 8104 and 105 is set to the second f-■ converter 111 so that the output signal amplitude is constant.
is controlled by the output voltage of In this way, the current value is reduced while keeping the high force amplitude constant. In other words, it is possible to reduce power consumption.

According to the above embodiment, power control is substantially possible by current control, and the input terminal for the current control signal may be used as an input terminal for power control. In addition, the current control means,
It may also be used as a power *J'l1 means.

The embodiments described above achieve lower power consumption of the LSI during low frequency operation by controlling the DC current within the LSI.

On the other hand, the embodiment shown in FIG. 6 controls the power supply voltage inside the LSI using external pins of the LSI,
This method realizes lower power consumption of LSI during low frequency operation.

This principle will be explained below.

Among the power consumption of an LSI, the power consumption of the AC branch circuit is proportional to the square of the power supply voltage, and the power consumption of the DC branch circuit changes in proportion to the power supply voltage.

Therefore, selection of the high speed region/low power consumption region of the LSI can also be realized by switching the power supply voltage inside the LSI using an external signal.

For example, when used in a high-speed region, the power supply voltage inside the LSI is controlled to a high value to achieve high-speed performance.
When used in a low power consumption area, by controlling the power supply voltage with a signal from outside the LSI, the power consumption of the AC circuit is reduced by the square of the voltage, and the power consumption of the DC branch circuit is reduced. Since it can be reduced in proportion to the voltage, it is possible to achieve a significant reduction in power consumption.

The embodiment shown in FIG. 6 will be described below.

The LSI 61 of the embodiment shown in FIG. 6(a) has a clock input pin 62 and a voltage control pin 63.

Depending on the signal input through this voltage switching pin 63, the characteristics of the LSI change as shown in (b).

The reason why such control is possible is because the characteristics shown in (C) of the LSI internal circuit are utilized.

In other words, when the clock frequency is high and the internal circuit must operate at high speed (circuit delay time = tH), the power supply voltage is set to VH, and when the clock frequency is low and the internal circuit must operate at low speed ( Circuit delay time = tL)
To do this, lower the power supply voltage to VL.

The AC power consumption of LSI is proportional to the square of the power supply voltage,
Since the DC component is proportional to the first power of the power supply voltage, it can be seen that the power consumption of the entire LSI is largely dependent on the power supply voltage.

Therefore, as in this embodiment, the power supply voltage is changed to the voltage switching pin 6.
1, it becomes possible to significantly reduce the power consumption in the low power consumption mode compared to the power consumption in the high speed mode.

An embodiment for realizing the above power supply voltage control is shown in FIG.

The LSI 76 has an input terminal 75 which is a control signal input means.
and an input circuit 7 which has a switch S as a control means and a voltage converter 74, and further processes input and output signals of the LSI.
1 and output circuit 72.

It has an internal circuit 73 that forms the main part of the LSI.

Next, the operation will be explained. When VH is input to the voltage converter 74 from the input pin 75, the voltage converter 74 outputs a voltage VL lower than VH. External power supply VCC (= V
H) is the input terminal 77 of the switch S and the input/output circuit 71
．． 72 , and the output terminal 78 of switch S is connected to the input terminal of voltage converter 74 , and the output terminal 78 of switch S is connected to the input terminal of voltage converter 74 .
The output of 4 is connected to internal circuit 73 and input/output circuits 71 and 72.

If the switch S is turned to B by the voltage control signal, the power supply voltage inside the LSI becomes VH, and if the switch S is turned to A,
The power supply voltage of internal circuit 73 and input/output circuits 71 and 72 becomes VL.

Note that although the signal level inside the LSI may change depending on the power supply voltage, the level of the interface signal with the outside of the LSI is constant, so even if the internal power supply voltage is VL, it is necessary to supply voltage VH to the input/output circuit. Therefore, the configuration shown in FIG. 7 is adopted.

Eighth embodiment of a semiconductor integrated circuit system having a semiconductor integrated circuit device and power supply switching means according to the present invention
This will be explained with reference to the figure and FIG.

FIG. 8 is a block diagram of an embodiment of a semiconductor integrated circuit system.

This system consists of multiple LSIs, which are semiconductor integrated circuit devices.
A31. LSIA 31, a switch S that is a power source switching means, a DC power source (for example, 3.3 V) 84, and an AC-D that supplies another DC power source (for example, 5.5 V).
It has a C converter 85 and a plug 86.

Switch S is when AC power is supplied.

Connected to the H side, otherwise connected to the L side.

Next, the operation will be explained.

When plug 86 is connected to an AC power source, switch S
5V is supplied to LSIA, B, etc. On the other hand, when the AC plug is not connected, a power supply voltage of 3.3V is supplied from the DC power supply to LSIA, B, etc.
Supplied to IA, B, etc. LSIA if 5V power supply voltage is supplied.

B, etc. operate in a high-speed region, while LSIA, B, etc. operate in a low power consumption region when a 3.3V11 source voltage is supplied.

Another embodiment of the semiconductor integrated circuit system will be described with reference to FIG.

FIG. 9 is a block diagram of another embodiment of the semiconductor integrated circuit system.

This system includes a first DC power supply (for example, 5.5V),
A second DC power supply (for example, 3.3V), a switch S which is a power supply switching means, and an LSI which is a semiconductor integrated circuit device.
A91 and LSIA31.

Next, the operation will be explained.

When switch S is connected to the H side, LSIA91,
When a 5V power supply voltage is supplied to the 892, etc., and the switch S is connected to the L side.

A 3.3-inch power supply voltage is supplied to LSIA91, 892, etc.

5■ If power supply voltage is supplied, LSIA91°B92
etc. operate in the high-speed region, while when a 3.3■ power supply voltage is supplied, LsrA91. B92 and the like operate in a low power consumption region.

According to the semiconductor integrated circuit system shown in FIGS. 8 and 9, the operating state is selected depending on the available power supply, such as high-speed operation when the usable power supply voltage is high and low-speed operation when the power supply voltage is low. I can do it.

[Effects] Conventional LSIs are optimally designed to satisfy a specific performance, and therefore cannot bring out sufficient performance when used in other performance areas. Therefore, it was necessary to develop multiple LSIs corresponding to multiple performance areas.

According to the present invention, it is possible to use different types of LSIs in multiple performance ranges, so it is possible to use different types of LSIs in multiple performance areas.
While it was necessary to develop an LSI of -
All you have to do is develop it. In addition, it becomes possible to realize an LSI that corresponds to a plurality of power consumption conditions and clock frequency conditions and covers a wide performance range with one type of LSI.

[Brief explanation of drawings]

FIG. 1 is a block diagram and power consumption characteristic diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a block diagram and power consumption characteristic diagram showing a conventional semiconductor integrated circuit device, and FIG. 4 is a circuit diagram showing an embodiment of the DC branch circuit and current control means of the semiconductor integrated circuit device according to the present invention. FIG. is a circuit diagram showing another embodiment of a DC branch circuit and current control means of a semiconductor integrated circuit device, FIG. 6 is an embodiment of a semiconductor integrated circuit device having a voltage switching pin according to the present invention, and FIG. A block diagram of a semiconductor integrated circuit device that performs voltage control according to the present invention, FIG. 8 is a block diagram of one embodiment of the semiconductor integrated circuit system according to the present invention, and FIG. 9 is a block diagram of another semiconductor integrated circuit system according to the present invention. FIG. 2 is a block diagram of an embodiment of the invention. 11... Semiconductor integrated circuit device (LSI), 12...
AC branch circuit, 13... DC branch circuit, 16... Input terminal, 101.102... NMO8, 103-106.
・PMO5, 107, 108...Bipolar transistor.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having one or more circuits whose current value does not change even if the clock frequency changes, the current of the circuit in the semiconductor integrated circuit device is
comprising an input means into which a control signal for controlling the device is inputted from outside the device, and a control means for controlling the current of the circuit by directly or indirectly receiving the control signal input to the input means, A semiconductor integrated circuit device characterized in that the current value of the circuit described above is made variable. 2. In a semiconductor integrated circuit device having one or more circuits whose current value does not change even if the clock frequency changes, a control signal for controlling the current of the circuit in the semiconductor integrated circuit device from outside the device. 1 whose impedance changes by directly or indirectly receiving the input terminal into which is input and the control signal input to the input terminal.
or two or more variable impedance elements, wherein the variable impedance elements are connected in series or parallel with the circuit to control a current value of the circuit. 3. The semiconductor integrated circuit device according to claim 1, wherein the input means has an input terminal, the circuit has one or more semiconductor elements, and the semiconductor element has a current input terminal and a current output terminal. the control means has a plurality of variable impedance elements whose impedance changes according to a control signal, the variable impedance element has a control terminal into which a control signal is input, and the input terminal includes: A semiconductor integrated device, wherein at least one variable impedance element is connected directly or indirectly to a control terminal of the variable impedance terminal, and at least one of the variable impedance elements is connected to a current input terminal and a current output terminal of the semiconductor element, respectively. circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein the input means has an input terminal and an inverter for inverting a control signal, and the circuit includes one or more MOSs of the first conductivity type. A transistor (hereinafter referred to as a first type MOS) and one or more second conductivity type MOS transistors (hereinafter referred to as a first type MOS)
The control means has the first type MOS and the second type MOS, and the input terminal has the first type MOS and one or more bipolar transistors. It is connected to the gate terminal of the first type MOS, and an inverted signal obtained by inverting the control signal by the inverter is input to the gate terminal of the second type MOS, and the second type MOS is connected to the collector terminal of the bipolar transistor. A semiconductor integrated circuit device, wherein the first type MOS is connected to an emitter terminal of the bipolar transistor. 5. The semiconductor integrated circuit device according to claim 1, wherein the input means has an input terminal and first and second signal converters, and the circuit has one or more first conductivity types. MOS transistor (hereinafter referred to as first type MOS) and one or more second conductivity type MOS transistors (hereinafter referred to as
The control means includes the first type MOS and the second type MOS, and one or more bipolar transistors.
The control signal is input to the first and second signal converters, and the output terminal of the first signal converter is a first type MO
the output terminal of the second signal converter is connected to the gate terminal of the second type MOS; the second type MOS is connected to the collector terminal of the bipolar transistor; A semiconductor integrated circuit characterized in that a first type MOS is connected to the emitter terminal of the bipolar transistor, and the first and second signal converters have characteristics of output voltages with respect to input signals that are opposite to each other. Device. 6. In a semiconductor integrated circuit device, an input terminal into which a control signal for controlling the internal power supply voltage of the semiconductor integrated circuit device is input from outside the device, and an input terminal that directly or indirectly receives the control signal input to the input terminal. A semiconductor integrated circuit device comprising voltage control means for controlling an internal power supply voltage of the semiconductor integrated circuit device. 7. In a semiconductor integrated circuit device, an input means into which a control signal for controlling the internal power supply voltage of the semiconductor integrated circuit device is inputted from outside the device, and receiving, directly or indirectly, the control signal input to the input means. A semiconductor integrated circuit device comprising voltage control means for controlling an internal power supply voltage of the semiconductor integrated circuit device. 8. In a semiconductor integrated circuit device having one or more circuits whose power consumption does not change even when the clock frequency changes, the power consumption of the circuits in the semiconductor integrated circuit device is controlled from outside the device. The circuit has an input means into which a control signal is input, and a control means that controls the power consumption of the circuit by directly or indirectly receiving the control signal input to the input means, and the power consumption is made variable. A semiconductor integrated circuit device characterized by: 9. A semiconductor integrated circuit system comprising one or more semiconductor integrated circuit devices and switching means for switching a power supply voltage supplied to these devices. 10. It has one or more semiconductor integrated circuit devices, an AC power supply for supplying power to these, a battery, and a switching means for switching these power supplies, and when AC power is supplied, it can operate at high speed. A semiconductor integrated circuit system characterized in that it operates at low speed when power is supplied from a battery.