JPH0444139A - Prefetch control system - Google Patents

Abstract

PURPOSE:To improve the processing speed and the efficient utilization of a cache memory by inserting a prefetch PF instruction into a position preceding an instruction using data in a program by several instructions and prefetching the data into the cache memory. CONSTITUTION:An instruction decoding control circuit 1-3 decodes a prefetch instruction and informs a cache control circuit 1 of a PF flag. Then the circuit 1 retrieves a cache tag 3-2 for the data on an informed address. When a mistake is decided, the circuit 1 stops the return of an interlock signal in response to the information of the PF flag and writes the data read out of a main storage 4 into a cache memory 3-3 to prefetch it in a state where the execution of an instruction is carried on. Thus an interlock state due to a cache mistake can be evaded so that the processing speed and the efficient utilization of the cache memory can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a prefetch control method for prefetching data into a cache memory, a prefetch instruction is inserted and prefetched for data required for program processing, thereby improving processing efficiency and achieving high efficiency. The purpose is to provide a cache usage method, and when an instruction extracted from a program and decoded is a prefetch instruction, the cache control circuit is notified of the PF flag and the address to be read, and this cache control circuit receives the notification. When a cache tag is searched for the address data and an error is found, in response to the notification of the PF flag, the return of the interlock signal is suppressed and the execution of the instruction is continued.
The configuration is such that data read from the main memory is written to the cache memory and prefetched to prepare for use of the data after a plurality of instructions.

[Industrial application field]

The present invention relates to a prefetch control method for prefetching data into a cache memory. With the recent demand for faster computer systems, there is a demand for improved cache hit ratios. For this reason, it is desirable to transfer and prefetch data required by a program running in the cache in advance.

[Conventional technology]

Conventional instruction processing devices use hardware to read out data around the missed address at the time of a cache miss from the main memory, transfer it to the cache, and store it therein. In order to improve the hint rate through this prefetch, a large amount of data around the cache miss address is transferred to the cache and stored.

[Problem to be solved by the invention]

Therefore, the above-mentioned prefetch transfers and stores a large amount of data that the program does not need in the cache, which is less effective, erases the data that is needed from the cache, and causes excessive use of the cache. There is a problem in that data storage reduces the throughput of the host device 41.

SUMMARY OF THE INVENTION An object of the present invention is to insert a prefetch instruction to prefetch data necessary for program processing, thereby improving processing efficiency and providing an efficient method of using a cache.

[Means to solve the problem]

Means for solving the problem will be explained with reference to FIG.

In FIG. 1, the instruction decoding control circuit 1-3 notifies the cache control circuit 3-1 of a PF flag when the instruction extracted and decoded from the program is a prefetch instruction.

The cache control circuit 3-1 searches the cache tag 3-2 and determines whether data at the notified address exists in the cache memory 3-3 (whether there is a miss/history 1- or not).
, and writes data read from the main storage device 4 to the cache memory 3-3 in the event of a miss.

[Effect]

As shown in FIG. 1, the present invention provides an instruction decoding control circuit 1-
3 is decoded as a prefetch command, it notifies the cache control circuit 1 of the PF flag, and the cache control circuit 1 executes the PF flag in the cache control circuit 1 for the flag at the notified address.
2, when a mistake is found, the data read from the main memory 4 is cached while suppressing the return of the interlock signal and continuing execution of the instruction in response to the notification of this PF flag. It is written to the memory 3-3 and prefetched.

Therefore, by inserting a prefetch instruction several instructions before an instruction that uses data in a program and prefetching the data into the cache memory, interlocks caused by cache misses can be avoided and processing speed can be improved. This makes it possible to use the cache memory efficiently.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 to 5.

In FIG. 1, an instruction decoding unit (IPU) 1 is a unit that decodes instructions taken in from a program. This instruction register 1-2 stores the instruction to be executed.
-1 instruction decoding control circuit 1-
3, and an instruction address register 1-4 for storing an instruction address to be read.

The instruction decoding control circuit 1-3 notifies the cache control circuits 3-1 of a PF flag when the instruction extracted and decoded from the program is a prefetch instruction, and also notifies the cache control circuit 3-1 of an instruction interlock signal. In response to this, the execution of decoding of instructions is stopped.

The calculation unit (EPU) 2 performs various calculations in response to notifications of control signals generated based on the results of decoding instructions by the instruction decoding control unit 1-3, and controls the calculations. It is comprised of an arithmetic control circuit 2-1, an operand address register 2-2 for storing operand addresses, an arithmetic unit 2-3 for performing various operations, and the like.

The main memory control unit (SCU) 3 includes a cache control circuit 3-1 that performs cache control, and a cache control circuit 3-1 that performs cache control, and a cache memory 3-3 that searches and determines whether data exists (hit/miss or not). It is composed of a cache tag 3-2, a cache memory 3-3 for storing data, and the like.

The main storage unit (MSU) 4 is a memory that stores instructions and data.

Next, the operation of the configuration shown in FIG. 1 will be explained in detail in accordance with the order shown in the flowchart of FIG.

In FIG. 2, ■ determines whether it is a PF instruction or not. This means that the instruction decoding control circuit 1-3 in FIG.
-2 is decoded to determine whether it is a PF instruction (a prefetch instruction newly established in the present invention). Y
In the case of ES, with the interlock inhibited by ■ and 0, when there is a miss from ■ to @, the data at the ○P address is read from the main storage device 4 and prefetched into the cache memory 3-3.

(2) sets the PF flag. As a result, the PF flag is notified from the instruction decoding control circuit 1-3 to the cache control circuit 3-1.

(2) performs interlock suppression. This means that in response to notifying the cache control circuit 3-1 of the PF flag with @, the cache control circuit 3-1 sends an instruction interlock signal to the instruction decoding control circuit 1-3 even if there is a miss. The instruction decoding control circuit 1-3 prevents the return of the instruction, and the instruction decoding control circuit 1-3 performs prefetch processing (■YES, [phase], ■, ■
This makes it possible to continue decoding the next instruction without waiting for the end of the prefetch process.

(2) Generates an OP address. In this case, the arithmetic unit 2 generates an operand address based on the control signal notified from the instruction decoding control circuit 1-3 (see FIG. 3).

(2) determines whether there is a mistake or not. In this case, the cache control circuit 3-1, which has been notified of the operand address generated in step (2), searches the cache tag 3-2 and determines whether or not there is a miss. If YES (in case of mistake), [phase]
Or prefetch with [phase]. On the other hand, if NO (
If there is a hit), the data exists in the cache memory 3-3, so there is no need to prefetch and the process proceeds to the next instruction.

[Phase] is determined to be a mistake in ■, so a read request is issued to the main storage device 4.

Data is transferred to O from the main storage device 4.

0 writes data to the cache memory 3-3. This means that the data has been prefetched into the cache memory 33. Then, the process proceeds to the next instruction.

As described above, when ■YES is decoded as a PF instruction, the PF flag is notified to the cache control circuit 31, and the return of the instruction interlock signal is suppressed in the event of a miss.
By reading data from the main storage device 4, storing it in the cache memory 3-3, and prefetching it, the relevant P
Instructions after the F instruction is inserted use this prefetched data, allowing high-speed processing to be performed without stopping instruction execution due to a mistake (see FIG. 5(b)).

Next, an explanation will be given of the operation when the instruction is decoded as ``NO'' and is not a PF instruction.

(2) Generates an OP address. In this case, the arithmetic unit 2 generates an operand address based on a control signal notified from the instruction decoding control circuit 1-3.

O determines whether it is a mistake or not. In this case, the cache control circuit 3-1, which has been notified of the operand address generated in step (2), searches the cache tag 3-2 and determines whether or not there is a miss. In the case of YES (in the case of a mistake), a read request is issued to the main storage device 4 in [phase], data is transferred in [phase], and processing is executed in (2). At this time, in [phase], the cache control circuit 3-1 notifies the instruction decoding control circuit 1-3 of an interlock signal to stop the processing, and in phase 2, the interlock signal is released, and step 3 is executed. Varnish. On the other hand, in the case of No (in the case of a hint), data is transferred from the cache memory 3-3, the [phase] is executed, and the process proceeds to the next instruction.

FIG. 3 shows an example of the format of a prefetch instruction according to the present invention. Here, the PF instruction is a prefetch instruction, and is composed of Code, M, B, ■, and D as shown in the figure. Code is 77”.M is M
This bit is an ode bit that indicates a mode such as the presence or absence of an instruction cache. B, I, and D represent a pace register, an index register, and a displacement amount. The OP address is the value (address) obtained by adding the contents of B and IXD.

Reading of instruction data and reading of operand data will be explained using FIG.

The instruction decoder 1 notifies the storage controller 3 of an instruction read request along with the address of the instruction to be executed. When hit (when instruction address data exists in cache 3-4)
transfers the instruction data to the instruction decoder 1. On the other hand, in the case of a miss, the IPU ink-tsunk signal is sent to the instruction decoder 1 to stop the operation, and a read request is sent to the main memory 4 to transfer the data to the cache 3-4 and the instruction decoder l. Transfer to. Then, the IPU intercock signal is canceled and processing is continued.

Further, the result of decoding the instruction is notified to the calculation unit 2 as a control signal, and various calculations are performed. At this time, the calculation unit 2 notifies the storage control unit 3 of an operand read request together with the operand address to be subjected to the calculation. When a hint is given, the operand data is transferred to the calculation unit 2. On the other hand, in the event of a miss, the EPU interlock signal is sent to the calculation unit 2 to stop the operation, and a read request is sent to the main storage device 4 to transfer the data to the cache 3-4 and the calculation unit 2. Forward. Then, the EPU interlock signal is released and processing is continued.

Next, a comparison of instruction execution times will be explained using FIG.

FIG. 5(a) shows the state of the pipeline when there is no conventional PF instruction and a cache miss occurs.

In this case, an error occurs when executing instruction 8, and as shown in the figure, a waiting time of 5 cycles required to read data from the main memory device 4 occurs between cycles 11 and 15, for a total of 16 cycles. It becomes necessary.

Figure 5 (b) shows that there is a PF instruction of the present invention and the cache
Represents the state of the pipeline in case of a mistake. In this case, by inserting a PF instruction with the data used in instruction 8, prefetching it, and writing it to the cache memory 3-3, it will be hit when instruction 8 is executed, eliminating waiting time. The process ends in a total of 12 cycles.

Therefore, the conventional 16 cycles shown in FIG. 5(a) become 12 cycles according to the present invention shown in FIG. 5(b), making it possible to shorten the execution time by 4 cycles. In addition, by inserting a PF instruction for only the data to be used a few steps earlier and writing it to the cache memory 3-3, it is no longer necessary to write a large amount of data to the cache memory 3-3 as in the past to improve the hit rate. Therefore, the cache memory 3-3 can be used efficiently.

〔Effect of the invention〕

As explained above, according to the present invention, a prefetch instruction (
By inserting a PF instruction and prefetching the data into the cache memory, it is possible to avoid interlocks caused by cache misses, improve processing speed, and use the cache memory efficiently. can be used.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of one embodiment of the present invention, FIG. 2 is a flowchart 1 for explaining the operation of the present invention, FIG. 3 is an example of the format of a prefetch instruction according to the present invention, and FIG. 4 is the overall configuration of the present invention. FIG. 5 shows comparative diagrams of instruction execution times. In the figure, 1 is an instruction decoding section, 1-3 is an instruction decoding control circuit, and 2
3 represents an arithmetic unit, 3 represents a main memory control unit, 3-1 represents a cache control circuit, 3-2 represents a cache tag, 3-3 represents a cache memory, and 4 represents a main storage device.

Claims (1)

[Claims] In a prefetch control method for prefetching data into a cache memory, when an instruction extracted and decoded from a program is a prefetch instruction, the cache control circuit (3-1) is notified of the PF flag and the address to be read. When this cache control circuit (3-1) searches the cache tag (3-2) for the data at the notified address and finds that there is a mistake, it issues an interlock signal in response to the notification of the PF flag. The data read from the main memory (4) is written to the cache memory (3-3) and prefetched while the return of the command is suppressed and instruction execution continues, in preparation for use of the data after multiple instructions. A prefetch control method characterized by being configured as follows.