JPH0443713A - Tri-state buffer - Google Patents

Abstract

PURPOSE:To prevent defective breakdown voltage between the bade and emitter of an output bipolar transistor (TR) even when a level of a bus is fully changed from VSS to VCC by connecting a switching element between the base and emitter of the output bipolar TR. CONSTITUTION:When a switch MOSFETS1 connected between the base and the emitter of an output bipolar TR Q1 at pullup side is turned on, a reverse bias between the base and emitter at an output high impedance state is avoided and a pullup MOSFETS2 is turned on at the output high level state. Thus, an output level is sufficiently arisen up to a VCC level and the level drop of the output by the base-emitter voltage VBE of the output bipolar TR Q1 is prevented. Thus, the level of the bus is fully changed from VSS to VCC and defective breakdown voltage between the base and emitter of the output bipolar TR is prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to semiconductor integrated circuit technology and B1-CMOS
The present invention relates to the application of logic circuits, and relates to techniques that are effective for use in, for example, internal bus drive circuits of LSIs.

[Prior Art] In LSIs that have an internal bus or are intended to be connected to an external bus, it is necessary to avoid signal conflicts when multiple bus master circuits or LSIs are connected to the same bus. Therefore, a tri-state buffer that can take an output high-impedance state is used for the bus driver.

Conventionally, this type of tristate buffer generally uses a CMOS logic circuit as shown in FIG. 4, for example. This tri-state buffer TBF outputs the output data D while the output enable signal ○E is at low level.
By turning on one of the output stage MOSFETs Ql and Q2 in response to ATA, the signal line on the bus BUS is connected to Vc.
Charge to C level or discharge to Vss level. When the output enable signal ○E is set to a high level, both MOSFETs Ql and Q2 in the output stage are turned off, and the output stage is placed in a high impedance state.

Incidentally, in recent years, with the increase in the scale of LSIs, the length of signal lines constituting a bus has become longer, and the number of circuits connected to a wooden bus has also been increasing. As a result, the parasitic capacitance of the bus increases and the signal transmission speed slows down. A possible countermeasure to this increase in parasitic capacitance is to increase the size of the output MO3 of the bus driver to increase the driving force, but increasing the MOS size increases the chip area and makes it difficult to achieve high integration. Can not.

On the other hand, in a semiconductor memory, generally, an address signal supplied from the outside is decoded to form a signal for selecting one word line and one data line. A relatively long signal line is provided inside such an address decoder or in a portion connecting the decoder with a word line drive circuit or a column switch. Such long signal lines create a large capacitive load on the logic gates that make up the decoder. Therefore, in the past, memory decoders were converted into so-called Bi-C
A technology has been developed that increases the driving force while suppressing the increase in power consumption by configuring the device with MOS logic gates (Japanese Patent Application Laid-open No. 133721/1983).

By applying the Bj-CMO8 circuit technology in semiconductor memory as described above to a tristate buffer as a bus driver, it is possible to drive a bus with a large parasitic capacitance without significantly increasing the occupied area and increase the signal transmission speed. I can do it.

[Problems to be Solved by the Invention] However, when the present inventors investigated configuring a tristate buffer that drives an internal bus of an LSI using a Bi-CMO8 logic circuit, the following problems were found. It has become clear that this occurs.

In other words, the current interface between LSI is TT
Since the amplitude is less than 5cm, such as the L level or ECL level, there is no support even if the Bi-CMO8 circuit is used as a buffer buffer. On the other hand, in the tri-state buffer that drives the internal bus, the CMO8 circuit on the side receiving the signal (for example, the buffer BFF in FIG.
), there is a demand for the bus to swing from \-'ss to Vcc with full amplitude. However, when the bus is swung with an amplitude of 5.5 mm, a voltage higher than the withstand voltage is applied between the base and emitter of the bipolar transistor on the pull-up side of the output stage of the other bus driver that is in a high impedance state, and the base There is a risk that the emitter junction may be destroyed.

In particular, in order to improve the performance of bipolar transistors,
When the emitter region and the base region are made highly doped or shallow, the breakdown voltage between the base and emitter further decreases, making breakdown voltage failure more likely.

An object of the present invention is to provide an internal bus driver consisting of a B1-CMOS tri-state buffer that does not cause breakdown voltage failure between base and emitter even when the bus is fully swung from Vss to Vcc.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, it has a push-pull type output stage in which two bipolar transistors or a bipolar transistor and a MOS FET are connected in series, and one of the two output transistors is turned on and the other is turned off according to output data, and a control signal is output. A Bi-CMO8 logic circuit consisting of a CMOS logic stage that forms a signal to simultaneously turn off two output transistors and put them in an output high impedance state based on the internal bus is used as an internal bus drive circuit, and A switch MOS F is connected between the base and emitter of the up-side bipolar transistor.
ET is connected, and this switch is turned on when the output is in a high-impedance state, and a pull-up MOSFET is connected between the output node and the power supply voltage terminal, and this pull-up MOSFET is turned on when the output is in a high-level state. It is.

[Operation] According to the above-described means, the switch MOS FET connected between the base and emitter of the output bipolar transistor on the pull-up side is turned on, thereby creating a reverse bias between the base and emitter in the output high impedance state. At the same time, when the output is at high level, the pull-up MOSFET is turned on, so that the output level is sufficiently raised to the Vcc level, and the output level is lowered by the base-emitter voltage VBE of the output bipolar transistor. can be prevented.

[Embodiment] FIG. 1 shows an embodiment of a B1-CMOS tri-state buffer according to the present invention.

In FIG. 1, 1 is a bipolar transistor Q1 and n
A push-pull output stage consisting of a channel MOSFET Q2 connected in series;
and N10SFET Q2 to form a signal that complementarily controls on/off or turns them off at the same time.
%10S logic circuit section.

In the second embodiment, a switch MOSFET is connected between the base and emitter terminals of the bipolar transistor Ql in the output stage 1.
ET Sl is connected and this switch MOSFET
Sl is turned on when the output is high impedance and turned off at other times by a signal obtained by inverting the output enable signal OE, which is a control signal for bringing the tristate buffer into a high impedance state, by an inverter IVI. There is.

Furthermore, when the switch MOSFET Sl is turned on and the output is at high impedance, the N-channel MOSFET M2 in the previous stage CMOS inverter IVJ, which forms the base voltage for turning off the output transistor Q1, is turned on (the P-channel MOSFET Ml is turned off). .

Therefore, we took the trouble to connect the transistors Q1 and MO' of the Ryo stage.
5FET Q2 is turned off and the charge at the floating output node n is transferred to the MOS in the inverter IVd.
There is a possibility that it may pass through FET M2.

Therefore, in this embodiment, the output node n of the inverter IV4
1 and the power supply voltage terminal V'ss, MOSFET M2
N-channel MOSFET M3 is connected in series with
This MOSFET M3 is the above switch MOSFET
It is turned off when the output is high impedance and turned on at other times by the same signal as the gate control signal of Sl.

Furthermore, in this embodiment, a pull-up MOS FETS2 consisting of a P-channel MOSFET is connected between the power supply voltage terminal Vcc and the output node n of the output stage l,
When the output is at a high level, the above pull-up MOS is activated by the output signal of the NAND gate G1, which performs the logical product of the output enable signal ○E and the data signal DATA and forms a signal that becomes the source of the on/off control signal for the output transistor Q1.
FET S2 is turned on and turned off at other times.

Note that in the embodiment shown in FIG.
In order to adjust the on-timing of FET S2, NA
The output of the ND gate G] is connected to the inverter IV6. MOSFET 324m is supplied through IV7, but inverter IV6. IV7 can also be omitted.

Next, the operation of the tristate buffer will be explained.

When the output enable signal OE is set to low level, NAN
D gates Gl, G2 are opened, and the output signal of one of NAND gates Gl, G2 becomes low level depending on the level of data signal DATA supplied from the internal logic circuit.

Also, while the output enable signal OE is at low level,
Inverter IV4 that inverts the output of NAND game hG]
MOSFET M3 inside is turned on (Sl is turned off). Therefore, the data signal DATA is
When II, the output stage transistor Q1 is on and MO
SFET G2 is turned off and the output changes to high level. At this time, since the pull-up M○5FET S2 is turned on by the output of the NAND gate G1, the output node r1. is raised sufficiently to the VCC level.

On the other hand, when the data signal DATA is "0", the output stage transistor Q1 is turned off and the MOS FETQ2 is turned on. Therefore, the output node n.

The charge is extracted and the output changes to low level.

Next, when the output enable signal OE changes to a high level, the outputs of the NAND gates Gl and G2 are set to a high level regardless of the data signal DATA. are all turned off, and the output node n becomes floating. Moreover, at this time, the MOSFET Sl between the base and emitter terminals of the transistor Ql is turned on, and the base potential and emitter potential become the same, so the output node n is brought to a high level by the buffer of another circuit via the bus. Even in this case, the potential difference between the base and emitter terminals of transistor Q1 becomes zero, and junction breakdown due to reverse bias is prevented.

FIG. 2 shows a second embodiment of the B i-CMOS tri-state buffer according to the present invention.

This embodiment uses an N-channel MOSFET instead of a P-channel MOSFET as switch MOSFET Sl in the tri-state buffer shown in FIG.
and this switch MOSFET S1″
The only difference is that an inverter IV8 is provided for inverting the output of the inverter Iv1 to form a signal with the opposite phase to the control signal of the switch Sl in order to turn on the output in a high-impedance state. It has the same configuration as the circuit.

Note that the inverter TV4 in FIG. 2 is made up of three N1N10SFETs to M3 connected in series, as in the embodiment shown in FIG.
) is controlled on and off by the inverted signal of the output enable signal ○E, and is turned off when the output is high impedance. To prevent.

The switch MOSFET Sl in FIG. 1 and the switch MOSFET Sl' in FIG. 2 may be connected in parallel between the base and emitter terminals of the output transistor Ql and turned on and off at the same time. In this way, the transmission gate type switch MOS
If the FET is connected, even if the output node n is brought to the Vcc level by another low time on the same bus, the Vs
Even if the transistor Q1 is set to the s level, the base potential of the transistor Q1 is prevented from falling or rising by the threshold voltage of the MOS FET from the level of the output node n, and the potential difference between the base and emitter is surely zeroed. This makes it possible to prevent breakdown voltage defects even in bipolar transistors with lower breakdown voltages.

FIG. 3 shows a third embodiment of a B1-CMOS tri-state buffer according to the present invention.

This embodiment is an example in which a bipolar transistor is used instead of a MOS FET as the pull-down side transistor Q2 of the output stage l.

In this example as well, MO3 and FET for full amplitude
A switch MOSFET S2 is provided, and a switch MOSFET Sl is connected between the base and emitter of the output transistor Ql, and is turned on when the output is high impedance.

Also, C
The MOS logic circuit section 2 has a simplified circuit format. For example, three N-channel MOSFETs M5~ connected in series between the output node n and the power supply voltage terminal Vss.
M7 constitutes a NAND gate. Inverter I
V4' is the MOSFET Ml shown in FIG.
~Node n of inverter IV4 consisting of M3 and MOS
An N-channel MOSFET (in the embodiment shown in FIG. 1, the output high-impedance state inverter IV4 (7) MOSFET MI is not necessary because it is always turned on) is used between the FET M1 and the FET M1. Since the data signal DATA is not uniquely determined in the output high impedance state, when the bus is driven low by another driver, the P channel ~105105 FET (and switch MOSFET) in the inverter IV4'
This is to prevent a through current from flowing through Sl.

Note that in the embodiments shown in Figures 1 and 2, a MOSFET is used as the pull-down transistor, but this is because the collector of a bipolar transistor generally has a large diffusion layer area, making it difficult to connect multiple bus drivers to one bus. This is because when connected, the load capacitance increases due to the parasitic capacitance of the collector.

Therefore, when a large number (10 or more) of bus drivers are connected to one bus, it is preferable to use the buffers of the embodiments shown in FIGS. 1 and 2.

On the other hand, when the number of bus drivers connected to one bus is small, the bus speed can be increased by using the buffer shown in FIG.

FIG. 5 shows a preferred L.
As an example of SI, an embodiment of a cache memory is shown.

The cache memory ]O in FIG. 5 is composed of a chip, and includes a directory memory 11, a data memory 12, and an LRU (Least Recent
y TJsed) type block replacement control circuit 13,
A tag comparator 14, a control logic 16 for controlling these circuits, and the like are formed. This cache memory 1 is connected between the memory bus and the MPU bus. Further, although not particularly limited, a block buffer 18 consisting of a dual-port register capable of storing data, for example, one block consisting of 16 bytes, is provided between the data memory 12 and the internal data bus 17b. It is provided.

In the directory memory 11, there is a data memory 12.
The upper ten or so bits of the address on the main memory of data stored in the same column position are stored as a tag. Of the address AD given to the recache memory 10 by the external MPU, the column address part CLM is
When fed to a common decoder in directory memory J and data memory 12, address tags and data are read simultaneously from the same column of each memory. Of these, 16 bytes of data are read out from the data memory 12 at a time, and the read data is temporarily stored in the block buffer 18. Data memory 1
Data transfer between block buffer 18 and block buffer 18 is not particularly limited, but is performed in units of 16 bytes.

On the other hand, the address tag read from the directory memory 11 is supplied to the tag comparator 14.

The tag comparator 14 is also supplied with the data of the tag part TAG of the address AD given by the MPU, and compares it with the tag read out from the directory memory, and determines whether there is a match or a mismatch. A signal CH indicating a mishit is output.

When the cache hits, one word (4 bytes) of the 16 bytes of data read from the corresponding column position in the data memory 12 and held in the block buffer 18 is specified by the lower 2 bits of the address. ) is selected by a selector (not shown) and supplied to the MPU via the data bus 17b. On the other hand, when a mishit occurs, the MPU bus and memory bus 21 are connected via the internal address bus 17a and the internal data bus 17b, so that the MPU directly accesses the main memory.

The data bus 17 is used to switch buses as described above.
A bus switching circuit 19 consisting of a tri-state buffer TBF is provided on the bus switching circuit 19, and each buffer TBF is controlled by an output enable signal OE and other control signals from the control logic 16.

As explained above, the above embodiment has two bipolar transistors or a bipolar transistor and a MOSFET.
A push-pull type output stage in which ETs are connected in series, one of the two output transistors is turned on and the other is turned off according to the output data, and the two output transistors are simultaneously turned off based on a control signal. C that forms a signal to put the output into a high impedance state
A Bi-CMOS logic circuit consisting of a MOS logic stage is used as an internal bus drive circuit, and a switch MOSFET is connected between the base and emitter of the bipolar transistor on the pull-up side of the output stage, and the switch is in a high-impedance state. is turned on, and a pull-up MOSFET is connected between the output node and the power supply voltage terminal, and when the output is at high level, this pull-up MOSFET is
By turning on the switch MOSFET connected between the base and emitter of the output bipolar transistor on the pull-up side, reverse bias between the base and emitter in the output high impedance state is avoided. In addition to preventing the occurrence of breakdown voltage defects, the pull-up MOS F E is
By turning on T, the level of the output is sufficiently raised to the Vcc level, and there is an effect that the level of the output can be prevented from dropping by the base-emitter voltage VBE of the output bipolar transistor.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, there is a switch MOSFET Sl connected between the base and emitter of the output transistor on the pull-up side and a pull-up MOSFET that raises the output level to the VCC level.
Although both S2 are provided, the pull-up MOSFET
The switch MOSFE can also be used in circuits without S2.
By providing T Sl, it is possible to prevent a breakdown voltage failure between the base and emitter of the transistor.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to a bus driver in a cache memory, which is the field of application that formed the background of the invention.
The present invention is not limited thereto, but can be used in general LSIs having a bus inside a microprocessor or digital signal processor.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in an LSI having an internal bus, it is possible to drive the bus at high speed, swing the bus with full amplitude from Vss to Vcc, and prevent breakdown voltage failure between the base and emitter of the output bipolar transistor. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of a B1-CMOS tri-state buffer according to the present invention, and FIG. 2 is a circuit diagram showing a second embodiment of a B1-CMOS tri-state buffer according to the present invention. , FIG. 3 shows the Bi-CM according to the present invention.
A circuit diagram showing a third embodiment of the OS tri-state buffer, FIG. 4 is a circuit diagram showing an example of a conventional CMOS tri-state buffer, and FIG. 5 is a circuit diagram showing an example of a conventional CMOS tri-state buffer. FIG. 2 is a block diagram showing an example of a configuration of a cache memory as a suitable LSI. 1...Output stage, 2...CMOS logic stage, Ql. Q2...Output transistor, Sl...Sui-Sochi element, S2...Pull-up MOSFET%M3
...Cutoff MOSFET. Figure Figure Bus ■6 V7

Claims (1)

[Claims] 1. A push-pull type output stage in which two transistors are connected in series between a first and a second power supply voltage terminal;
Complementary on/off control of two transistors,
At least one of the transistors in the output stage on the pull-up side is a bipolar transistor, and a switching element is connected between the base and emitter terminals of this transistor. A tri-state buffer characterized in that the switching element is turned on only when the output is high impedance. 2. The trie according to claim 1, further comprising a pull-up MOSFET connected between the output node of the output stage and the first power supply voltage terminal, which is turned on when the output is at a high level. state buffer. 3. In the CMOS circuit that forms the on/off control signal for the output transistor on the pull-up side of the CMOS logic stage, there is a circuit that blocks the path for charge to flow into the output node via the switching element when the output is high impedance. 3. The tri-state buffer according to claim 1, further comprising a cut-off MOSFET for controlling the tri-state buffer.