JPH0443439A - Peripheral controller - Google Patents

Abstract

PURPOSE:To prevent a program from being erroneously destroyed by providing a comparison means which compares an address image with the value of a program counter and which generates an interruption signal to a micro processor when they coincide and a storage means collecting and storing operation information on a device when interruption occurs. CONSTITUTION:An address storage means 2 storing the address image which a host device 3 designates, the comparison means 3 which compares the address image with the value of the program counter 1 and which generates the interruption signal to the micro processor when they coincide and the storage means 8 collecting and storing operation information on the device when interruption occurs are provided. In such a case, it is not necessary to rewrite the program since interruption is executed by the target address so as to execute a processing for obtaining operation information at the time of executing the program. Thus, the program is prevented from being erroneously destroyed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a peripheral control device, and in particular, it is possible to arbitrarily collect device operation information such as register information at the time when a specified address is passed during program operation. This invention relates to peripheral control devices with maintenance and diagnostic functions.

[Conventional technology]

Conventionally, this type of peripheral control device has set a process for recording device operation information fixedly at a specific address in the program. In addition, in the case of a program on a readable/writable memory element, by rewriting part of the program externally using a service processor, etc., it is possible to record the operating information of the device on the memory element at the target address. I was doing it.

[Problem to be solved by the invention]

The conventional peripheral control device described above rewrites a part of the program to collect operational information and records it on a storage element as a means of collecting operational information at the time when the target address is passed. calling the program.

When rewriting is performed on a read/write memory element,
Every time the peripheral control device performs initial settings, rewriting is disabled and rewriting must be performed again.
There are drawbacks.

Furthermore, if the program of the peripheral control device exists on a magnetic storage medium and is boot-loaded each time initial settings are made, there is also a method of rewriting the program on the magnetic storage medium. However, in this case, if you want to stop collecting information at the target address or change the address to collect information, you may need to rewrite the program,
Repeated modifications increase the possibility of corrupting the program, which requires extreme care and is generally difficult to handle.

Furthermore, if a program exists on a non-volatile memory element that cannot be written to, information on the program operation can be obtained at any address by rewriting the program, or information collection can be stopped midway to prevent a decrease in execution speed. The disadvantage is that it is impossible.

[Means to solve the problem]

The peripheral control device of the present invention is connected to a host device through an interface, and has a microprocessor, a program counter that indicates an execution address when a microprogram is executed, and a memory that stores the microprogram, and stores the microprogram at an address indicated by the program counter. In a peripheral control device that performs control by sequentially reading out data from memory, an address storage means that stores an address image designated by a host device compares the address image with the value of the program counter, comparing means for generating an interrupt signal to the microprocessor at certain times;
and storage means for collecting and storing operating information of the device when an interrupt occurs.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

A program counter 1 stores an execution address of a program, and is connected to an address storage register 2 and a comparator 3. Comparator 3 is connected to C via interrupt signal line 4.
It is connected to the control circuit 5 of the PU. interrupt vector 6
stores an address at which execution starts when an interrupt occurs, and is connected to the program counter 1 via an internal bus 7. Further, a memory circuit 8 that stores operational information of the device including registers, a microprogram storage area 9, and registers 10 that are updated as needed by program execution are connected to an internal space.Furthermore, This peripheral control device is connected from the boat 11 to a host device 13 via an interface 12 with the host device.

Next, the operation of this embodiment based on the above configuration will be explained.

First, the boat 11 receives an address for performing interrupt processing from the host device 13 via the interface 12, and
It is stored in the address storage register 2 as address data for address match comparison. A comparator 3 constantly compares the value of the program counter 1 and the value of the address storage register 2, and when they match, an interrupt request is issued to the control circuit 5 of the CPU via an interrupt signal line 4. CP by interrupt request
The control circuit 5 of the U sets the contents of the interrupt vector 6 in the program counter 1 via the internal bus 7, thereby executing the interrupt processing specified by the interrupt vector 6 at the execution address of the program stored in the program storage area 9. Change to the start address of the program.

The return address to the interrupted program is temporarily saved in the storage circuit 8. By operating the control circuit 5 of the CPU in accordance with the interrupt processing program, the contents of the registers 10 and information regarding the operation of the device are stored in the storage circuit 8. At the end of the interrupt processing program, the return address to the interrupted program saved in the storage circuit 8 is set in the program counter 1, thereby continuing the original processing.

〔Effect of the invention〕

As explained above, the present invention performs processing by interrupting at the target address in order to obtain operational information during program execution, so there is no need to rewrite the program.
This has the effect of preventing accidental program destruction. Furthermore, even if the program is operating on a non-writable non-volatile memory element, there is an advantage that operating information can be obtained when the program passes through a target address. Furthermore, since the address setting operation is performed from the host device, information collection can be freely performed from the host device by remote control.

Register, 3...Comparator, 4...Interrupt signal line, 5.
...CPU control circuit, 6...Interrupt vector, 7.
...Internal bus, 8...Memory circuit, 9...Microprogram storage area, 10...Registers, 11...
Boat, 12... Interface with host device, 13
...Upper device.

Claims (1)

[Claims] A microprocessor connected to a host device through an interface, comprising a microprocessor, a program counter that indicates an execution address when a microprogram is executed, and a memory that stores the microprogram, wherein the microprogram is stored at an address indicated by the program counter. In a peripheral control device that performs control by sequentially reading data from a memory, an address storage means that stores an address image designated by a host device compares the address image with the value of the program counter, and when they match, the A peripheral control device comprising: comparison means for generating an interrupt signal to a microprocessor; and storage means for collecting and storing operating information of the device when an interrupt occurs.