JPH0442974A - Solar cell with bypass diode - Google Patents

Abstract

PURPOSE:To inhibit to reduce an effective light receiving area and to form a solar cell with a bypass diode having a high efficiency by forming the diode at the lower part having a wide width of a root of a pectinated surface electrode. CONSTITUTION:A P-N junction between a P-type diffused layer 64 and an N-type diffused region 63 is connected in an antiparallel with a bypass diode BD, and a parasitic diode DSC of a PN junction between a P-type silicon substrate 61 and the region 63 is short-circuited by a junction short-circuiting part 80. In this case, since the diode BD is shielded by a part having a wide root width of a surface electrode 67, photovoltaic power is not generated, a satisfactory reverse direction is held, and it does not affect an influence to the electromotive force of a photoelectric converting PN junction. The diode BD is reversely biased by a solar cell SC, and a normal photovoltaic power can be produced from the cell SC.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to means for preventing damage to a solar cell when a reverse bias voltage is applied to the solar cell.

(Prior art) In general, a power generation device using sunlight is constructed by connecting individual solar cells 10.11° and 12.13 in parallel to form a submodule of 30tS, as shown in Fig. 6. In series with solar cell 10-1°11-1.12-1.
A sub-module 31 consisting of solar cells 13-1, etc., a sub-module 32 consisting of solar cells 10-2, 11-2, 12-2, 13-2, etc., all connected 1- to 5 solar cell arrays (hereinafter referred to as Al/I). ), and the load is connected to this. When light is incident on this array, the shadows of structures around the array are projected onto some of the solar cells (hereinafter referred to as cells) that make up the array, and when the cells are blocked from light, they are continuously illuminated. If the next cell A is reverse biased and this reverse bias is large, the reverse biased cell will fail jI! 5, the power generation performance of the array decreases.

this,? In order to prevent bias, the direction i#c, ! is opposite to the direction of the electromotive force of the sub module or cell. Means are used to connect the diodes and bypass the reverse bias of the cell. l! Figure 7 (&) indicates cells 10, 11゜12.1
This is an example in which a bypass diode Df1 is connected in parallel in the reverse direction to a submodule similar to 341.
lr diagram (b) shows bypass diodes Di, D2 . D3. This is an example in which D4 are connected in parallel in opposite directions. In both of these, the cells and diodes were supplied as individual components, and the diodes were connected to individual cells or submodules.

Another technique is to form a diode on the opposite side of the cell's light-receiving surface so as to share the cell's substrate, and to function as a bypass diode.

Figure 8 is a schematic cross-sectional view of one example. A diffusion layer 21t of NII is formed on one surface of a P-type silicon substrate 20, and an electrode 24 is provided on a part of the diffusion layer 21t. Light is received from the diffusion layer 21 side, and electricity is generated at the PN junction. A mesa is formed on the other surface, an N-type diffusion layer 22 is entirely formed on the surface, and an electrode 23 is provided on the surface. Although not shown, an electrode for connecting to another adjacent cell is provided on a part of the surface of the P-type silicon substrate 200. This equivalent circuit is shown in FIG. The positive side of cell SC is connected to the negative side of bypass diode BD, and the! of cell SC is connected to the negative side of bypass diode BD. The glass side of the inverse bypass diode BD is open. This twisted three-terminal cell is connected as in the 10th factor (&), (b). FIG. 10(a) is a perspective view when three cells are connected in series.The negative side of the first solar cell 1 and the positive side of the second solar cell 2 are connected to the lead wire 25. The negative side of the second solar cell 2 and the glass side of the third solar cell 3 are similarly connected to the lead wire 25. The lead wires 27 and 28 of the jfim are connected to the load. The positive side of the surface of solar cell 1 in N1 and the N-type diffusion layer 22 on the surface of second solar cell 2 are connected by a lead wire 26, and the positive side of the surface of solar cell 2 in series 2 and Nll! diffusion layer 2 on the surface of the third solar cell 3
2 are similarly connected by a lead wire 26, and this equivalent circuit is shown as xofg(b)K.

N! formed on the surface of the second solar cell 20! A bypass diode consisting of an SII diffusion layer 22 and a P-type silicon substrate 20 serves as a bypass for the first solar cell 1 and a third diode.
Bypass diode B formed on the surface of the solar cell 30 of
serves as a bypass for the second solar cell 2. Therefore, the third and final solar cell 3 connected in series must be connected in parallel with an individual diode C in the opposite direction.

Tsumashi, l! The method of connecting individual diodes, as shown in Figure 7-)(b), requires wiring to connect the cells and diodes, and also requires man-hours for wiring, which increases costs. In addition, individual diodes and wiring wires may protrude from the cell surface. Such protrusions are inconvenient when pressure is required to fold them, such as in space solar arrays.

For solar cells with bypass diodes that are connected to three terminals, such as those shown in Figures 8 and 10 (a) and (b), the connection is complicated, and the last cell in the series connection requires the following: Individual diodes must be used. Figure 7 (
As in cases a) and (b), protrusions also cause inconveniences.

Furthermore, in order to eliminate the above-mentioned drawbacks, a two-terminal connected solar cell with a bypass diode has been devised in which the bypass diode is integrated with the solar cell.

FIG. 4 is a schematic cross-sectional view of one example. A P+ layer 41 is formed on the back surface of a P-type silicon substrate 40, and a back electrode 46 is further formed thereon. Eight layers 42 serving as a light-receiving surface are formed on one surface of a P-type silicon substrate 41, and an antireflection film 45 is applied to the surface. P-type silicon substrate 41
An N-type well 48 is formed on the other surface of the t!, and two layers 49 are formed on the other surface of the well 48. 5i
02 film 44. Holes are formed at appropriate locations in the 5i02 film 44 to form required electrodes. One end of a comb-shaped surface electrode 44 provided on the surface of the eight layers 42 is connected to the second layer 49 . N-type well 48 and Pli silicon substrate 4
0 and is short-circuited by a junction short-circuiting electrode 47.

This equivalent circuit is shown in FIG. electron 67 and terminal 68
A solar cell SC is connected between the two.

This is formed by a PN junction between the pH silicon substrate 40 and the 8 layer 42 of FIG. In parallel with this, a bypass diode BD in the reverse direction and a short-circuited growth diode DSC in the forward direction are connected n-.

The bypass diode BD is formed by a PN junction between the first layer 49 and the N-type well 48 in FIG.
A PN junction between 8 and an N-type silicon substrate 40 and a junction shorting electrode 47 are formed.

Therefore, when a reverse bias is applied to the PN junction for phototransformation, the PN junction for bypass becomes forward-oriented.

(Invention solved〃6(-)Two majesty jumps〕The construction of Figure 4
If you change the structure, you will be able to overcome a lot of the previous efforts, but there are still problems such as the following.

If the bypass diode is located at the end of the solar cell, when the end of the solar cell is damaged, it will not function as a bypass diode (7ffi!).

Also, the current flows through the bypass diode.
The heat generated by this process cannot be dissipated efficiently.

A portion a of the surface of the PU silicon substrate 40 between the bypass diode N-type well 48 and the photoelectric conversion Ni 42 is inverted to the N-type, and the electrical characteristics are deteriorated.

The N layer 42 and the P-type silicon substrate 40, which serve as the light-receiving surface,
There may be a short circuit to the surface electrode 43 and the electrical characteristics may deteriorate. The part to be shorted is indicated by an arrow). In order to prevent stiffness, it is possible to completely form a CVDH film, a thermal oxide film, etc. in this vicinity and perform insulation treatment, but in that case, the cost will be high.

If the area of the junction shorting electrode 47 is small, the series resistance will be large and the forward characteristics of the bypass diode BDO will be poor.A
Ru. As a result, when current flows through the dimer, the amount of heat generated increases, resulting in power loss.If the scale is operated, the heat may damage the thick battery.

R) In the present invention, the following measures are taken to solve the above-mentioned gland li''
f: Resolved.

A bypass diode was provided 1c below the wide part of the root of the comb-shaped surface 1K pole.

A P+ type diffusion layer is formed as a channel stopper on the N layer on the light receiving surface side and the N type well of the bypass diode.

-i irradiation, the N-layer gold is formed as much as possible at the location where it is irradiated.

At the boundary between the end of the N layer on the light-receiving surface side and the surface of the P-type silicon substrate, under the surface electrode, a deep N-type diffusion layer with the same thickness as the N-type well layer is placed. to form.

Increase the area sound by increasing the number of bonding short-circuit electrodes or by other means.

(Function) Bypass diode 1r: The following effect can be obtained by forming the bypass diode 1r below the wide part at the base of the comb-shaped surface electrode.

1. The wide part at the base of the surface electrode is for current collection and interconnector connection, and is a place that is not normally exposed to light, so the effective light-receiving area does not decrease, making it possible to create a solar panel with a high-efficiency bypass diode. Kameike is obtained.

2 When reverse bias is applied to the solar cell, 1 is applied to the nokuivas diode! Current flows and generates heat, but is this heat ligature an interconnector? Heat can be dissipated by connecting it near the bypass diode.

3. If the diode is below the interconnector,
The PN junction of the bypass diode is sufficiently transparent to light, and deterioration of the diode due to radiation can be suppressed.

The channel stopper is expanded to the r-layer i-well of the bypass diode. , when forming the Ip shadow, it can be formed at the same time without increasing the cost (by inverting the surface of the P-type silicon substrate, short circuits between the N layer on the light receiving surface and the Nfi well of the bypass diode can be completely prevented, and the solar cell The conversion efficiency can be totally improved.

The downward pressure of the surface electrode which is not irradiated with light is P
Since no N junction is formed, the minority carrier collection efficiency per nest area of the PN junction is improved, and the open circuit voltage and electrical output are increased.

At the same time, an N-type well of a bypass diode is formed under the comb-shaped electrode at the boundary between the edge of the N layer (light-receiving surface) and the surface of the P-type silicon substrate. Since a deep N layer can be formed, photoelectric conversion efficiency is improved without increasing cost.

By increasing the number of junction short-circuiting electrodes and increasing the area, the resistance value is reduced, the power loss is reduced, the amount of heat generated is also reduced, and the reliability is improved.

(!I!Example) FIG. 1(&) is a schematic plan view of an embodiment of the present invention.

The surface of the Pffi silicon substrate 61 is covered with a transparent anti-reflection film 66 (not shown) as shown in Fig. 1 of IN1 in the part where photoelectric conversion is performed, and a comb-shaped base with a wide base is formed on the lower surface of the film. An electrode 67 is provided, and other necessary parts are covered with an oxide film 66 as shown in FIG. 1(b), although not shown.

The right center @@7-1 of the electrode 67 is made wider than other parts, and an interconnector is connected to this part. Electrode 6
On the surface of the Pffi silicon substrate 61 below the antireflection film 66, oxide film 65, etc., an N'' type diffusion layer 62 (indicated by a two-dot chain line) and an Nll diffusion region 63 (indicated by a dotted line) are formed. A P type diffusion layer 64 (indicated by a dotted line) is formed in a part of the Nll diffusion region 63.The N+ type diffusion layer 62 and pH diffusion layer 64 are formed in a part of the Nll diffusion region 63.
is connected to. In addition, there is an oxide film 6 in the necessary areas.
5, an N-type diffusion region 63 and a pH silicon substrate 61
An appropriate number of junction short-circuit parts 80 are provided to short-circuit the 0 surface. Therefore, the PN junction for photoelectric conversion consisting of the P-type silicon substrate 1 and the N+ type scattered layer 621 and the PN junction for the bypass diode consisting of the PIE diffusion layer 64 (!:Nll diffusion region 63) are in opposite directions. As shown in the schematic cross-sectional view below, the PI
A back electrode 6 is provided on the back surface of the silicon substrate 1.

Therefore, its equivalent circuit is the same as that shown in FIG. 5, which describes the conventional example. In the figure, 91 is a NIL diffusion layer, and the surface electrode 67 between the N+ diffusion layer 62 and the PfJ silicon substrate 61
to prevent short circuits caused by

111 (b) and (o) = (d) are respectively OA-A' in (a) of the same figure.

It is a BB', CC' cross-sectional view. As shown in these drawings, 621 ft of an N+ type scattering layer is formed on one surface of the P type silicon substrate 1 to serve as a light receiving surface. A KN type diffusion region 63 is formed in the other part of the surface, and a P type diffusion layer 64t is formed in a part of the surface. The surface of the N+ type scattering layer 62 is covered with an antireflection film 66. N” type diffusion layer 62
A part of the 0 surface and the P-type diffusion layer 64 are connected by a surface electrode 67. A P+ type diffusion layer 90 is provided on the back surface of the P type silicon substrate 61 to improve efficiency by the BSF effect. Further, a back electrode 68 is provided on the entire surface of the back surface, and the oxide film 65 is removed from the light receiving surface and the front electrode 671. l The surface of the silicon substrate 61 is protected. Circumference IIK of Nff1 diffusion region 63 on the surface
Also, a P+ type diffusion layer 90 is formed, which prevents short circuit between the N+ type scattering layer 62 and the Nll diffusion region 63 due to the channel caused by inversion. These P”f
The fi diffusion layer 90 can be formed simultaneously with the formation of the Pal mineralized layer 64.

The NIl diffusion layer 91 is formed at the periphery of the N+ diffusion layer 2 and below the surface electrode 67 at the same time as the N-type diffusion region 63 is formed. to prevent short-circuiting. The junction surface between the NW diffusion region 63 and the P-type diffusion layer 64 is transparent through the wide central portion 67-1 of the surface electrode 67. An interconnector will later be connected to this central s6 fu 1.

Referring to the equivalent circuit of FIG. 5, the operation of the solar cell having the structure shown in FIGS. 1(a) to (d) is as follows.

Under normal operating conditions, the solar cell SC consisting of the FN junction between the PfJ silicon substrate 61 and the N+ type scattering layer 62 is as follows:
Forward bias and P type silicon substrate 61? The N+ type scattering layer 62 generates a negative electromotive force. Therefore, P connected to N layer MIl diffusion layer 2
ffi diffusion layer 64 is negative, back electrode 68 is CPI
! Nff1 diffusion region 63 connected to silicon substrate 61
is positive. The PN junction between the PIl diffusion layer 64 and the Nff1 diffusion region 63 is a bypass diode BD.
are connected in parallel in opposite directions. Note that the parasitic diode DSC due to the PN junction between the P-type silicon substrate 61 and the N-type diffusion region 63 exerts a di-shorting force 5 at the junction short-circuit portion 80 . At this time, the bypass diode BD is shielded from light by the wide base portion of the surface electrode 67, so the bypass diode BD does not generate photovoltaic force and maintains a good reverse direction. The electromotive force KX of the junction has no influence. -Tt That is, the bypass diode BD in FIG. 5 is the solar cell 5C4C, 41
: A reverse bias is applied, and a normal photovoltaic force can be extracted from the solar cell SC. When assembling and using such a solar cell SC of a companion star as a 6-figure play, some of the sun 1! If the pond completely stops generating power for some reason, it is important to note that power generation has not stopped yet! A reverse bias is applied to the battery, load battery, etc., and a reverse bias is applied to the solar cell that has stopped generating power. As a result, a bias in the partial direction is applied to the bypass diode BD, so that the sun 1! Pond S
A voltage higher than the forward voltage of the bypass diode BDO is not applied to C[.

The above-mentioned bypass diode-equipped sun turtle pond is manufactured as follows. Figures 2 (a) to (9) show the
- As an example, a large number of solar cells are formed on a single regular silicon substrate, and individual C9 cells are taken out for dicing. The drawings below are for the individual cells.

First, as shown in Figure 2), oxide films 65, 65 are formed on both the front and back surfaces of a P-type silicon substrate 61.

Next, as shown in FIG. 2(b), four-hole holes 7171 are formed by photo-etching in the region where the bypass diode is to be formed and the region where the N-type diffusion layer for short circuit prevention is to be formed. The hole 71 at the left end is the area where the bypass diode of the adjacent cell is to be formed.

QK$2 figure (e) K shows h Le J: IC5i? 1.7
1... to form an N-type diffusion layer 91 and an N-type diffusion region 63.
1.71... is covered again with oxidized All@N7CJ:.

Next, Figure 1!2 (d,)! /I: The work that shows you,
Holes 72, 72... are entirely formed in the oxidized GSS on the surface of the N-type diffusion region 63 by photo-etching. Also, oxidation @65i on the back surface is removed. The hole 72 on the surface of the N-type diffusion region 630 is for the r-type diffusion layer 64 for the bypass diode, and the hole 72 at the periphery of the N-type diffusion region 63 in the casing is
This is because the P+ type diffusion layer serves as a channel stopper.

Next, r-type impurities are diffused through the holes 72, 72, . Then, a P-type diffusion layer 64 and a P-type diffusion MGO, 90 are formed on the first surface, and the holes 72.72i1
: Oxidized again $I6 B N: J: Covered with ri.

Furthermore, a P+ type diffusion layer 90 is formed on the back surface.

Konij: This is because of the BSF structure.

Next, as shown in FIG. 2(f), a hole 73-i is formed by photoetching in the oxide film 65 on the surface of the area scheduled for photoelectric replacement.

Next, as shown in FIG. 2 (2)) K, from hole 73 to N
The type impurity is diffused to completely form 1,000N+ type diffusion debris 62.

Next, as shown in Figure 2), the oxide film o5 on the surface of the r-dissipation layer 640 is photo-etched! : Su, hole 7
form 5. At this time, the oxide film 65 on the back surface is also removed.

Next, as shown in FIG. 2(i), the N+ type scattering layer 6
A comb-shaped front electrode 67 is connected to a part of the surface of the F-type silicon substrate 6, and a back electrode 68 covers the back surface of the F-type silicon substrate 6. At this time, a junction short-circuit portion 804 for short-circuiting the N type diffusion region 63 and the P+ type diffusion layer 90 of the bypass diode is simultaneously formed. Note that the surface of the N-type diffusion region 63 is exactly the same as that formed by the wide end portion of the surface electrode 87.

Next, as shown in FIG. 2(j), the surface electrode 67
Particularly, masking the connection part of the interconnector, N
An antireflection film 68 is formed on the surface of the diffusion layer 62 made of +. T
The skinning process involves forming an anti-reflection film 66 on the surface of the electrode and connecting the interconnector. Do it in a method that makes it perfect.

Next, as shown in FIG. 2(G), when cutting along the point a line 7G in front of the front right of the surface electrode 67 and in front of the N'''' disk diffusion layer 62, it is shown in FIG. As a result, a solar cell with a bypass diode can be obtained.

An interconnector is connected to this solar cell with a bypass diode in the following manner. for example! [Figure 3 (a)
As shown in (b), one interconnector 51 is connected to the surface of the wide electrode pad of the comb-shaped electrode 540 on the surface of the solar cell 50, and a bypass diode 53 is connected to the back surface of the electrode pad. It is formed. The other interconnector 52 reaches the back surface of one interconnector 51 along the back electrode of the solar cell 50 .

Conventionally, the bypass diode is not placed on the back side of the interconnector, but in another part, and the interconnector is also connected to the input/output end of the solar cell.

Therefore, if a crack 55 occurs and the solar cell breaks down as shown in the figure, there is a risk that the function of the bypass diode will disappear. Even if a crack 55 occurs when the interconnector is connected as shown in Figure 3 (JL) (b), the function of the bypass diode remains.
It is possible to completely prevent a decrease in the output of a group of solar cells connected in series to a cell in which this occurs.

(Effects of the Invention) As described in detail above, according to the present invention, when a reverse bias is applied to the solar cell, the diode constituting the bypass is integrally built into the silicon substrate, and the diode is connected to two terminals. The ability to combine with other cells simplifies module assembly.

1. Such a solar cell has high conversion efficiency, low power loss even when reverse bias is applied, and is highly reliable. It is particularly useful for solar cells used in outer space.

[Brief explanation of drawings]

Fig. 1(a) is a plan view of a simple embodiment of the present invention; Fig. 1(a) and (d) are respectively A-^1 of Fig. 1-).
, B++ BL. c-c' Simplified screen diagram Figures 2) to (G) are schematic cross-sectional views of each of the manufacturing processes of one embodiment of the present invention, and Figure 3 (a) is a plan view of an example of interconnector connection. 39) is its side view, Fig. 84 is a schematic sectional view of a conventional example, Fig. 5 is an equivalent circuit diagram of a solar cell with a bypass diode, Fig. 6 is a block diagram of a general solar power generation device, and Fig. 7 Figures (a), (b) and u are block diagrams of conventional examples of adding nine bypass diodes, Figure 8 is a schematic cross-sectional view of an example of a conventional solar cell with three-terminal bypass diodes, and Figure 9 is its equivalent. Circuit diagram, 10th
Figure (&) is a perspective view showing the connection of the solar cells in Figure 8;
FIG. 0(b) is its equivalent circuit diagram. 61... P-type silicon substrate, 62... N+ type scattering layer 63... N-type diffusion region, 64... Pffi diffusion layer, 65... Menguri film, 66... Antireflection Membrane, 67...
・Surface electrode, 68... Back electrode, 80... Junction short-circuit part, 9o... P-type diffusion layer, 91... N-type diffusion layer Figure 1 (Q) ~ Figure 2 Figure 2 6 & self-ttt figure figure figure figure figure

Claims (1)

[Claims] 1. A PN junction for photoelectric conversion formed on the surface of the semiconductor substrate and a PN junction for bypass formed in parallel in the opposite direction.
It has an N junction and a comb-shaped electrode formed on the surfaces thereof, and the bypass PN junction is formed below the wide part of the base of the comb-shaped electrode. A solar cell with a bypass diode.