JPH0442491A - Cmos integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain the CMOS integrated circuit which can operate by voltage composed of plural kinds of batteries by limiting only the voltage with plural kinds of batteries whose maximum value is limited to about 3.6V as operational voltage. CONSTITUTION:Memory access can be performed based on the supply of the voltage generated by the battery composed of the plural kinds of batteries whose maximum value is limited to 3.6V, a RAM composed of plural numbers 1 or N is included, and a logical level in an input/output interface is set to satisfy a technology standard for a CMOS circuit with low voltage. Namely, a circuit element constituting the RAM and a control circuit is constituted based on the battery voltage whose maximum voltage is 3.6V. Thus, the RAM with CMOS construction which can perform the memory access with these plural kinds of batteries can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an 0MO3 (complementary MO3) integrated circuit device, which operates using, for example, relatively low voltages generated by multiple types of batteries each having one voltage. The present invention relates to a technique that is effective for use in a CMOS integrated circuit device including a RAM (Random Access Memory) using dynamic memory cells that can be used in a dynamic manner.

[Conventional technology]

CMOS configuration RA using dynamic memory cells
An example of M is "Hitachi IC Memory Data Book" published in 1988, page 632. This RAM is
The power supply voltage is set to 5V (standard value).

In addition, a RAM that guarantees operation at a low voltage such as 4■ in only some operating modes is described in ``Toshiba Integrated Circuit Technical Data 1PB-TD-6''.

[Problem to be solved by the invention]

The development of small electronic devices such as microcomputers that are operated by battery voltage is progressing.

On the other hand, the conventional RAM guarantees its operation at a standard voltage such as 5.5 cm as described above, and memory access is not possible under the battery voltage. In this way, conventional RAMs are only intended to be operable using battery voltage during battery backup.

The inventors of the present application have considered developing a RAM that can be used under the limited conditions of being operated only at a small voltage such as battery voltage. Currently, the types of batteries mainly used in small electronic devices are lithium batteries, nickel-cadmium batteries, and lead batteries. The voltages generated by these batteries are 2.8V to 3.6V for lithium batteries, 1.2V for nickel-cadmium batteries, and 2V for lead batteries. Among these, NiCd batteries are often commercially available in a state in which a plurality of them are directly connected, and the output voltages are, for example, 2.4V and 3.6V.

The voltage range formed by such a battery is between 2 and 3
．． The absolute value falls within a relatively small voltage fluctuation range, such as within the range of 6V. We focused on the fact that it is possible to realize a fully operable CMOS circuit even with current CMOS integrated circuit technology, provided that it is operable only in this voltage range. In other words, CMOs that are conventionally operated with standard voltages such as 5.
In device design of S circuit, ±10% of power supply voltage
It is necessary to guarantee operation even under moderate voltage fluctuations, and the withstand voltage is set by taking into consideration the voltage of the internal booster circuit, which fluctuates depending on the operating voltage. You can't make it thinner, and you can't shorten the channel length. This makes it possible to avoid high voltages such as those mentioned above.
This makes it extremely difficult to design a CMOS circuit that can operate down to moderately low voltages.

On the other hand, under the condition of operating with a small voltage such as a battery voltage with a maximum value of about 3.6V as mentioned above, there is no need to increase the withstand voltage of the MOS FET etc. Making the insulating film as thin as possible,
Even with the current manufacturing technology of CMOS integrated circuits, such as short channeling, it is possible to realize a CMOS circuit that operates satisfactorily within the above voltage range.

An object of the present invention is to provide a CMOS integrated circuit device that can operate with a plurality of types of battery voltages.

Another object of the present invention is to provide a CMOS integrated circuit device including a RAM whose memory can be accessed using a plurality of types of battery voltages.

Another object of the present invention is to provide a CMOS integrated circuit device that is operable with a plurality of battery voltages and has guaranteed operating speed and current consumption for each of the different voltages. .

Another object of the present invention is to provide a CM equipped with a delay circuit that is optimal for a circuit that can be operated by a plurality of types of battery voltages.
An object of the present invention is to provide an OS integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, it includes a RAM whose memory can be accessed by supplying voltages generated by multiple types of batteries with a maximum value of about 3.6V, and the logic level at the input/output interface is set to a low voltage. CM for
Set to satisfy the technical standards for OS circuits. Further, AC and DC characteristics such as operating speed and current consumption are determined for each of a plurality of different operating voltages depending on the type of battery. A time constant circuit consisting of a polysilicon resistor and a MOS capacitor is used as a delay circuit included in the CMOS circuit.

[For production]

According to the above-mentioned means, by limiting the operating voltage to multiple types of battery voltages whose maximum value is up to about 3°6 V, memory access is possible with multiple types of batteries. You can get M. Since AC and DC characteristics regarding operating speed and current consumption are determined for each voltage that corresponds to multiple types of batteries, users can select the most efficient one that matches the capabilities of the CMOS circuit according to the battery being used. I can use it. Stable operation is possible by using a polysilicon resistor that does not have voltage dependence as a delay circuit for operating at low voltages as described above.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a memory card using a RAM to which the present invention is applied. Of the circuit blocks in the figure, each circuit block except for the contact terminals and battery is a CMOS chip consisting of an l chip.
Consists of integrated circuit devices. A plurality of these semiconductor chips are housed together with the battery in a card-like package.

The RAM is composed of a plurality of numbers from 1 to 2, and the control terminals, data terminals, and address terminals thereof are commonly connected to the internal control bus, data bus, and address bus. By using N RAMs in this way, the storage capacity of the memory card is N times the storage capacity of one RAM. Although not particularly limited, RAM is a pseudo-RAM that uses a dynamic memory cell consisting of an address selection MOS FET and an information storage capacitor as described later, and whose input/output interface is compatible with a static RAM. Static RAM (hereinafter simply referred to as PSR)
Sometimes called AM. ). By using a dynamic memory cell as a memory cell as described above, a relatively large storage capacity can be achieved even in a limited mounting space such as in a memory card.

The control circuit is a RAM consisting of one or more of the above.
In other words, the control circuit is connected to the bus of the microcomputer system via contact terminals, receives control signals from the microprocessor, etc., and decodes the system address of the upper bits. It generates a chip enable signal plane for selecting one RAM from N RAMs, and generates a write enable signal WE and an output enable signal OE for read/write control.

A plurality of data buses and address buses to which data terminals and address terminals of the RAM are commonly connected are connected to contact terminals.

The power supply control circuit receives the battery voltage of the internally mounted battery (lithium) and the external battery that controls the operation of the microcomputer system via contact terminals, and switches the battery voltage according to the operating mode. internal R
Supplies AM and control circuits. For example, when the RAM is in a data retention state, the power supply control circuit supplies voltage to a battery mounted inside the memory card. On the other hand, when the memory card of this embodiment is installed in a microcomputer system or the like and a read/write operation is performed, the voltage is switched to an external battery voltage that operates the microcomputer system.

In this case, the microcomputer system is a portable microcomputer system such as a laptop type, notebook type, or handtop type,
A relatively large lithium battery is used.

For example, if a memory card is constructed using four RAMs each with a data retention current of 5 μA, the nominal capacity mounted on it only when in the data retention state is 2.
If a 50mAh CR2430 type lithium battery is used, the battery can be used for a long period of about 520 days without needing to be replaced. Furthermore, even if the current consumption during memory access of the above RAM is 30 mA, and memory access is performed for only 1 hour on day -, the nominal capacity is 1
If you use a 300mAh CR15400 type lithium battery, you will not need to replace the battery for about 43 days.

Currently, the types of batteries mainly used in small electronic devices are lithium batteries, nickel-cadmium batteries, and lead batteries, as described above. The voltage generated by these batteries ranges from 2.8V to 3.6V for lithium batteries and 1.2V for nickel-cadmium batteries.
, lead battery is 2v. Among these, nickel-cadmium batteries are often sold in a state in which a plurality of them are directly connected, and the output voltages are, for example, 2.4V and 3.6V.

Therefore, the circuit elements that make up the RAM and control circuits must be configured based on a battery voltage with a maximum voltage of 3.6V, and the lower limit voltage required for the operation of the CMOS circuit is when the lead battery is discharged to some extent. Considering that the current can be obtained up to about 1.6V, the gate insulating film is formed as thin as possible, the channel length is shortened, etc. using CMOS circuit technology.
This guarantees operation at battery voltages up to V.

As a result, it is possible to obtain a memory card that can operate with any of three types of small batteries: a 3.6V lithium battery, two 3.6V NiCd batteries connected in series, and a 2V lead battery.

In this case, in order to obtain interface compatibility with an external microcomputer system, etc., the control circuit and power supply control circuit should be a circuit compatible with the 74HC series and/or 7AAC series of CMOS logic ICs, or a standard IC thereof. configured. The input/output interface of the RAM is also designed to be compatible with the 7dHC series and/or 74AC series.

JEDESOK Standard No. 8 (1984) (JE
L V CM OS (Low Volta) described in DE C5 TANDARD N118)
ge CMOS) and LVBO (Lo-Voltage
(Battery 0perated CMOS), and the above RAM interface specifications are set to satisfy these as well.

In order to comply with the above interface specifications, the RAM interface specifications of this embodiment are determined as shown in Table 1 below.

Table-1 VCC is the power supply voltage, V IN (aim)
is the minimum value of the input high level, VIL(a□) is the maximum value of the input low level, ■□(□8) is the maximum value of the input high level, and VIL(mint is the minimum value of the input low level).

In the standard interface specifications as mentioned above, the lower limit operating voltage VCC (min) is up to 2■ for both the 74HC series and LVBO, and L V CMOS
In this embodiment, the lower limit operating voltage VCC (min) is set to 1.6 V in consideration of the voltage during discharge of the lead battery. However, with the above standard interface, the power supply voltage VCC is 0.75 or 0.
Set the voltage multiplied by 7 to V I)l(sial and o to the power supply voltage vcc.

The voltage multiplied by 15 or 0.2 is ■1□1. Therefore, the interface specifications at the lower limit operating voltage of this embodiment are set to meet the above-mentioned severe conditions.

In order to satisfy the interface specifications shown in Table 1 above, input circuits such as the RAM address buffer and data input cover sofa, and P channel M that constitutes the output cover sofa, etc.
The conductance of O3FET and N-channel MO3FET and their ratio are set.

In addition, as mentioned above, if the guaranteed operation voltage is set to 1.6 V, which is lower than the lowest lead-acid battery voltage 2■, the current capacity of the lead-acid battery can be used to the limit. In addition, the following advantages arise.

For example, a lead battery is used as the built-in battery, and it is used as a RAM.
In other words, when the memory card is connected to a microcomputer system operated by a lithium battery, the memory card is connected to a microcomputer system operated by a lithium battery.
It is necessary to provide a backflow prevention diode to prevent backflow from occurring in the built-in lead battery. When such a reverse current prevention diode is connected, a voltage loss occurs by the forward voltage thereof. For this reason, if the lower limit voltage is set to 2<2> of the lead voltage, the lead battery as described above cannot be used for battery backup. On the other hand, if the lower limit voltage is guaranteed to a voltage lower than the lead voltage, such as 1.6 V, as in this embodiment, the lead battery can be used for battery backup as described above. In this case, a diode with a small forward voltage, such as a Schottky diode, may be used.

FIG. 2 shows a block diagram of an embodiment of a selection circuit, a timing generation circuit, and a voltage generation circuit of a pseudo-static type RAM used in the above-mentioned memory card or the like. Further, FIGS. 3 and 4 respectively show block diagrams of an embodiment of the pseudo-static RAM memory array, its direct peripheral circuits, and data input/output circuits. The circuit elements constituting each block in FIGS. 2 to 4 are not particularly limited, but are made of P-type crystal silicon using known CMOS integrated circuit manufacturing technology.
formed on a single semiconductor substrate. Further, in FIGS. 2 to 3 and the following circuit diagrams, signal lines related to input or output signals, etc. are shown starting from bonding bands formed on the surface of the semiconductor substrate.

The pseudo-static RAM of this embodiment has a dynamic RAM as its basic configuration as described above, and its memory cells are composed of so-called l-element type dynamic memory cells, thereby achieving high circuit integration and low cost. The aim is to reduce power consumption.

Further, the X address signals XO to XIO and the Y address signals Yll to Y18 are respectively provided at separate address input terminals A.
It is input via O-AIO and AIl to A18, and is further provided with a chimbu enable signal CE, a write enable signal W1, and an output enable signal OB as control signals, making the input compatible with normal static RAM. It is assumed to have an output interface. Furthermore, the pseudo-static RAM has an auto-refresh mode in which a refresh operation is performed sporadically while specified by a refresh counter RFC that has a built-in refresh address, and a refresh timer circuit TMR and a refresh timer counter circuit SRC that are built-in with the refresh counter RFC. It has a self-refresh mode in which a refresh operation for all word lines is executed autonomously and intermittently at a predetermined cycle.

In this embodiment, the output enable signal OE is
Although not particularly limited, it is also used as a refresh control signal RFSH, and the operation mode of the pseudo-static RAM is selectively set by the output enable signal OE and write enable signal WE.

In FIG. 2, a chip enable signal CE and a write enable signal W are supplied as start-up control signals from the outside.
E and the output enable signal OE, that is, the refresh control signal RFSH, are connected to the corresponding input buffers CEB, WE.
The signal is supplied to the timing generation circuit TG via B and OEB. This timing generation circuit TG receives a 3-bit complementary internal address signal B from the X address buffer XAB.
XO, BXI, and BXIO (here, for example, a non-inverted internal address signal BXO and an inverted internal address signal BXO are collectively expressed as a complementary internal address signal BXO; hereinafter, the same applies to complementary signals) are supplied. The timing generation circuit TG generates various signals necessary for the operation of each circuit block of the pseudo-static RAM based on the chip enable signal CE, write enable signal WE, output enable signal OE, and complementary internal address signals XO9XI and BXIO. Form a timing signal.

11-bit X address signals XO to XIO supplied from the outside via corresponding address input terminals AO to A10
Although not particularly limited, is supplied to one input terminal of the X address buffer XAB, and the 8-bit Y address signals Yll-Y1B are supplied to the Y address buffer YAB. The other input terminal of the X address buffer XAB is supplied with 11-bit refresh address signals ARO-ARIO from the refresh counter RFC.

The X address buffer XAB is supplied with inverted timing signals φref and φxl from the timing generation circuit TG, and the Y address buffer YAB is supplied with an inverted timing signal φyz.

Here, as will be described later, the inverted timing signal φref is used when the pseudo-static RAM is in the selected state in auto-refresh or self-refresh mode.
Timing signals φxi and φyl are selectively set to low level, and when the pseudo-static RAM is in the selected state, the levels of the X address signals xo-xio, refresh address signals ARO to ARIO, or Y address signals Y11 to YlB are determined. is selectively set to low level.

The X address buffer XAB is a pseudo (hereinafter static type R)
When AM is selected in normal write or read mode and the inverted timing signal φref is set to high level, the X address signal XO supplied via the external terminal
.about.XIO is captured and held in accordance with the inverted timing signal φxi. When the pseudo-static RAM is selected in the refresh mode and the inverted timing signal φref is set to low level, the refresh address signals ARO to ARIO supplied from the refresh address counter RFC are converted to the inverted timing signal φχ1.
and retain it. The X address buffer XAB further receives these X address signals X0-XI.
Complementary internal address signals BXO to BXIO are formed based on O or refresh address signals ARO to ARIO.

Of these, the complementary internal address signal BXO of the lower two bits
and BXI, as described above, are the timing generation circuit TO
and a 3-bit complementary internal address signal BX2.
BX3 and BXIO are supplied to word line selection drive signal generation circuit PWD.

The remaining 6 bits of complementary internal address signals BX4-BX9 are supplied to the X predecoder PXD. Complementary internal address signals BX2-BX9 are further supplied to the X-system redundant circuit XR.

Each memory array of the pseudo-static RAM is provided with four redundant word lines and eight sets of redundant complementary data lines. X system redundant circuit XR (XRU.

Among these, the defective address assigned to each redundant word line is compared bit by bit with the complementary internal address signals BX2 to BX9 supplied to the X address via the buffer XAB during memory access.

As a result, if these addresses match all bits,
The corresponding inverted redundant word line selection signals XRO to XR3 are selectively set to low level. Inverted redundant word line drive signal X
RO to XR3 are word line selection drive signal generation circuits PWD
Redundant word line selection drive signal generation circuit PRW attached to
Supplied to D.

The word line selection drive signal generation circuit PWD receives the complementary internal address signals BX2. Based on the word line drive signal φX supplied from BX3 and X10 and the word line drive signal generation circuit φXG, word line selection drive signals
Selectively form I IU and X0OD to Xi ID. In addition, the redundant word line selection drive signal generation circuit P
RWD outputs a corresponding redundant word line selection drive signal XROIJ-XR3U or XROD-X based on the word line drive signal φX and the inverted redundant word line signal BXIO.
Selectively forms R3D. Here, the word line drive signal φX is set at a predetermined boost level exceeding the power supply voltage of the circuit, and the word line selection drive signals xoou to XIIU (XOOD to XIID) and redundant word line selection drive signals XRO1J to XR3U (XROD −
XR3D) is also considered to be a boost level. By generating such a boost level, it is possible to perform full writing of the information storage charge, which is inevitably reduced due to operation at a low voltage as described above.

The X predecoder PXD receives the complementary internal address signal BX4.
~BX9 are sequentially combined and decoded 2 bits at a time to generate the corresponding predecoded signals AX450~AX4.
53. AX670~AX673 and AX890~A
X893 is formed alternatively. These predecode signals are commonly supplied to each X decoder.

Similarly, when the pseudo-static RAM is in the selected state in normal write or read mode, the Y address buffer YAB takes in Y address signals Yll to Y18 supplied via external terminals in accordance with the inverted timing signal φy1, hold this. Also, based on these Y address signals, a complementary internal address signal AY 11
-AYI8 is formed. These complementary internal address signals A
Y11 to Y18 are Y predecoder PYD and Y
It is supplied to the system redundancy circuit YRAC.

The Y-system redundancy circuit YRAC compares and checks the defective address assigned to each redundant data line and the complementary internal address signals AYII to AYI8 supplied via the Y address buffer YAB upon memory access. As a result, when these addresses match all bits, the corresponding redundant data line selection signals YRO to YR7 are selectively set to high level. Redundant data line selection signal YRO~
YR7 is supplied to each Y decoder via a Y predecoder PYD.

Y predecoder PYD receives complementary internal address signal AYI
By sequentially combining and decoding I to AY18 2 bits at a time, the corresponding predecoded signals AY120 to A
Y123. AY340-AY343. AY560~AY
563 and AY780 to AY783 are formed alternatively.

These predecode signals are commonly supplied to each Y decoder via corresponding signal lines. In this embodiment, the predecode signals AY560 to AY563 and AY? The signal lines for transmitting 80 to AY783 to each Y decoder are the redundant data line selection signal -yyRo-YR.
It is also used as a signal line for transmitting 7. Therefore, the Y predecoder PYD outputs the predecode signals AY560 to AY563 and AY78 according to the complementary internal control signal -φ-yr supplied from the Y system redundant circuit YRAC.
0~AY783 or redundant data line selection signal YRO~
It also has the function of selectively transmitting YR7 to the signal line.

As shown in FIG. 2, there is a substrate bank bias voltage generation circuit VBBG which forms a negative potential substrate puncture bias voltage VBB based on the circuit power supply voltage, and a substrate bank bias voltage generation circuit VBBG which forms a negative potential substrate puncture bias voltage VBB based on the circuit power supply voltage. and a voltage generating circuit HVC that generates an internal voltage HVC. Further, a word line drive signal generation circuit φxG is provided which forms the word line drive signal φX based on the inverted timing signal CE3 supplied from the timing generation circuit TG.

In FIG. 3, this pseudo-static RAM has eight memory arrays MARYOL, MARYOR, and
3L and MA'RY3R. These memory arrays have corresponding sense amplifiers 5AOL and 5AOR to 5A3L and 5A3R and column switches C3O.
With L and C3OR or C33L and C33R,
They are arranged symmetrically with the corresponding Y address decoders YDO-YD3 in between. In addition, the sense amplifiers, column switches, and Y decoders that correspond to these memory arrays are connected to the corresponding X address decoder XDOL.
and XDOR to XD3L and XD3R are placed vertically and divided, and a symbol (U) or (D) is attached corresponding to the placement position. In the following explanation, to avoid complexity, the above (
The symbol U) or (D) is omitted. Furthermore, among the memory arrays, those arranged above the X decoder are collectively referred to as an upper array, and those arranged below are collectively referred to as a lower array.

Memory array MARYOL to MARY3L and MA
RYOR-MARY3R is selectively brought into an active state by selectively bringing a designated word line into a selected state. In this embodiment, when the pseudo-static RAM is in normal write or read mode or auto-refresh mode, the eight memory arrays are MARYOL and MARY2L (or MARYOL).
R and MARY2R) or MARYIL and MAR
Two combinations of Y3L (or MARYIR and MARY3R) are activated at the same time. At this time,
In each memory array, the upper side array or the lower side array is selectively activated according to the complementary internal address signal BXIO of the most significant bit, and four sets of data lines are each set from the two memory arrays that are activated. They are simultaneously selected and connected to corresponding unit circuits of the corresponding main amplifiers MALL and MALR or MARL and MARR or write circuits DILL and DILR or DIRL and DTRR. As a result, this pseudo-static type R
The AM is a RAM having a so-called x8 bit configuration that inputs and outputs 8 pints of storage data simultaneously.

When the pseudo-static RAM is placed in the self-refresh mode, the eight memory arrays are brought into operation at the same time, although this is not particularly limited. At this time, in each memory array, the upper side array or the lower side array is selectively activated according to the complementary internal address signal XIO of the most significant bit, and a total of 8 Refresh operations for the main word lines are performed simultaneously. These refresh operations are autonomously and periodically executed at a cycle four times the normal refresh cycle, and the refresh address counter RFC is sequentially updated each time. As a result, the number of refreshes per unit time in the self-refresh mode is substantially reduced by a quarter, and the average current consumption of the memory array is correspondingly reduced.

As shown in FIG. 4, the pseudo-static RAM has 8
Eight data input/output terminals 100 to 107 are provided corresponding to bit input or output data. Ma,
Further, a data input buffer DIB and a data output buffer DOB each including eight unit circuits are provided corresponding to these data input/output terminals. Data input/output terminal 1
00 to ■07 are coupled to the input terminals of the corresponding unit circuits of the data input buffer DIB, and are also coupled to the output terminals of the corresponding unit circuits of the data output buffer DOB. The data input buffer DIB is supplied with a timing signal φdic from the timing generation circuit TG, and the data output buffer DOB is supplied with a timing signal φdoc. Here, the timing signal φdic is used to determine the level of input data supplied via the data input/output terminals 100 to 107 when the pseudo-static RAM is selected in the normal write mode, although it is not particularly limited. It is selectively set to a high level at the point in time.

Furthermore, when the pseudo-static RAM is in the selected state in the normal read mode, the timing signal φdoc is selectively set to a high level at the time when the levels of the read signals of the eight selected memory cells are determined. be done.

The output terminals of the lower four unit circuits of the data input buffer DTH are respectively coupled to the input terminals of the corresponding unit circuits of the write circuits DILL and DIRL, and the output terminals of the upper four unit circuits of the data input buffer DIB are The write circuits DILR and DIRR are respectively coupled to input terminals of corresponding unit circuits. Similarly, the input terminals of the lower four unit circuits of the data output buffer DOB are respectively coupled to the output terminals of the corresponding unit circuits of the main amplifiers MALL and MARL, and the input terminals of the upper four unit circuits of the data output buffer DOB are coupled to the output terminals of the corresponding unit circuits of the main amplifiers MALL and MARL. The terminal is the main amplifier MAL
R and MARR are respectively coupled to output terminals of corresponding unit circuits. The main amplifiers MALL and MALR receive a timing signal φmao from the timing generation circuit TG.
is supplied to the main amplifiers MARL and MARR,
A timing signal φmal is supplied.

The data input buffer DIB is a pseudo-static type RA
When M is selected in the write system operation cycle, the data input/output terminals 100~! The input data supplied via 07 is taken in according to the timing signal φdic, and is simultaneously set to a selected state via the corresponding unit circuits of the write circuits DILL to DIRR.
The data output buffer DOB, which writes data into the memory cells of
The 8-bit read signal amplified by LL to MARH is taken in according to the timing signal φdoc and sent to the outside via the corresponding data input/output terminals roo to 107. When the timing signal φdoc is set to a low level, the output of the data output buffer DOB is set to a high impedance state.

As mentioned above, the pseudo-static type RAM of this embodiment employs a non-address multiplex system, and has a total of 19
address input terminals AO-A18. It also has a total of 16 memory arrays, each of which is paired and substantially divided into upper and lower halves, and each memory array is selectively selected and divided into groups of 4 arrays, as will be described later. Each group includes a total of 256 word lines and a total of 1024 sets of complementary data lines that are selectively selected in groups of four at the same time. As a result, each memory array has an address space of substantially 262,144, or 256 kilobits, so that the pseudo-static RAM has a storage capacity of 4 megabits.

When the pseudo-static RAM is brought into a selected state in a normal operation mode, two of the 16 memory arrays are selected at the same time, so-called pairs. and,
A total of eight memory cells, four from each of the two memory arrays that are activated simultaneously, are selected and connected to the corresponding common I10 line. These memory cells further pass through a corresponding write circuit or main amplifier to a data input buffer sofa DIB or a data output buffer sofa DOB.
Can be connected to the corresponding unit circuit.

Address signals AO and A1 select a memory array bear, and address signal 10 selects an upper or lower array. As a result, 1/2 of the 16 memory arrays are selected and put into operation state two at a time. As described above, when the pseudo-static RAM is placed in the self-refresh mode, the address signals AO and A1 have no meaning, and the eight upper or lower arrays are simultaneously activated.

Next, the 6-bit address signals A4 to A9 are supplied to the X predecoder PXD, where they are combined into two bits each and decoded. As a result, the corresponding predecode AX450~AX453 to AX890~A
X893 is alternatively set to high level. These predecode signals are supplied to the X decoder and are used to selectively select word line groups in each memory array. The 2-bit address signals A2 and A3 are supplied to the word line selection drive signal generation circuit PWD, and are combined with the word line drive signal φX output from the word line drive signal generation circuit φXG to generate the word line selection drive signal X.
Provided to alternatively form OO, XOI, XIO and Xll. As described above, word line drive signal φX and word line selection drive signals X0O-Xll are set to a predetermined boost level that boosts the power supply voltage of the circuit. As a result, according to the above 8-bit address signals A2 to A9, 256 memory arrays are configured, which constitute two memory arrays designated by the above address signals AO and A1 and AIO.
One of the word lines of the book is alternatively brought into a selected state.

Similarly, 8-bit address signals A11-A18 input via address input terminals A11-A18 are used as Y address signals and are used for data line selection. That is, address signals Al1-A18 are sent to Y predecoder PY.
All and A as shown in Table 3.
12. A13 and A14. A15 and Al1 and A
I? and A18, 2 bits each are decoded. As a result, the corresponding predecoded signals AYI 20 to AYI 23. AY340-AY34
3. AY560~AY563 and AY780~AY
783 is alternatively set to high level. These predecode signals are further combined by the decoder tree of the Y decoder, and as a result, a total of 8 sets of complementary data lines, 4 sets each, are selected from each of the two memory arrays to be activated, and the corresponding common I10 connected to the line.

As a result, from a so-called 4 megabit memory cell to 8
memory cells are selected and the data input/output terminals 100 to 100 are selected.
! The input/output operation of 8-bit storage data is performed via the 07.

FIG. 5 shows a geometrical layout of an embodiment of the above-mentioned static type RAM on the semiconductor substrate surface. The basic layout of one embodiment of the pseudo-static RAM of this embodiment will be explained based on FIG. In the figure, the semiconductor substrate is shown horizontally for reasons of space, so in the following description, the left side of the figure will be referred to as the upper side of the semiconductor substrate surface.

As mentioned above, the pseudo-static type RAM has 8 pieces (actually 16 pieces) each divided into an upper side and a lower side.
Memory arrays MARYOL to MARY3L and MAR
X7 dress coder XDOL-XD equipped with YOR-MARY3R and provided corresponding to these memory arrays
3L and XDOR to XD3R, and four Y address decoders YDO to YD3 provided corresponding to the two memory arrays and each divided into an upper side and a lower side.

An X address decoder XDO is located in the center of the semiconductor substrate surface.
L-XD3L and XDOR-XD3R are arranged, and corresponding word line drive circuits WD O
LIJ-WD 3 LU (WD OLD-WD3LD
) and WDORU-WD3RU (WD ORD-
WD 3 RD) are arranged respectively. Then, the corresponding memory arrays MARYOL to MARY3L and MARYOR-MA sandwich these X-system selection circuits.
RY3R is arranged in a so-called vertical manner, sandwiching the corresponding Y decoder YDO-YD3 and extending its word line in the vertical direction. Although not shown, in the vicinity of the Y address decoders YDO to YD3, corresponding sense amplifiers 5AOL-3A3L and 5AOR to 5A3R and column switches C3OL-C33L and C3OR-C
33R are arranged respectively.

Memory array MARYOL-MARY3L and MARY
A pre-Y address decoder PYD, a Y-address redundancy control circuit YRAC, etc. are arranged above OR-MARY3R. Further, below these memory arrays, main amplifiers MALL to MARR, write circuits DILL to DIRR, etc. are arranged.

Bonding pads are arranged on each side of the semiconductor substrate surface so as to avoid positions close to each corner of the semiconductor substrate surface and positions close to the center of the left and right sides. Also, in the vicinity of these pads, corresponding unit circuits of an X address buffer XAB, a Y address buffer YAB, a data buffer sofa DIB, and a data output buffer sofa DOB are arranged.

FIG. 6 shows a timing chart of one embodiment of the read cycle of the pseudo-static RAM.

In the pseudo-static RAM of this embodiment, a read cycle is performed on the condition that the write enable signal WE is at a high level at the falling edge of the chip enable signal CE. The output enable signal OE is temporarily set to a low level at a predetermined timing that does not delay the output operation of read data. Address input terminal A
An 11-bit X address signal and an 8-bit Y address signal are supplied to O-A10 and AI1-A1B, respectively, in synchronization with the falling edge of the chip enable signal CE. In the figure, one of these address signals is exemplarily shown as a representative. The data input/output terminals 100-107 are normally in a high-impedance state, and when a predetermined access time has elapsed, 8-bit read data output from eight memory cells that are simultaneously selected is sent out. .

FIG. 7 shows a timing diagram of one embodiment of the write cycle of the pseudo-static RAM.

Pseudo-static RAM uses chip enable signal C.
At the falling edge of E, write enable signal W1 is set to low level prior to chip enable signal 61, or is temporarily set to low level at a predetermined timing after chip enable signal CE. be done. Address input terminal AO
-AtO and AIl to AI8 are input with X and Y address signals, and data input/output terminals 100-107 are
8 due to predetermined timing that does not delay the write operation.
Focus write data is supplied.

FIG. 8 shows a timing diagram of one embodiment of the paste-domodify write cycle of the pseudo-static RAM.

This operation cycle is a combination of the above-mentioned read cycle and write cycle, and since the output open signal d1 and the write enable signal WE are at a high level at the falling edge of the chip enable signal CE, the read cycle is first performed. Start.

After the read data of the specified address is sent from the data input/output terminals I00 to 107, at the time when the write enable signal WE is temporarily set to low level,
8-bit write data supplied from data input/output terminals 100-107 is written to the above address.

FIG. 9 shows a timing diagram of an embodiment of the auto-refresh cycle of the pseudo-static RAM.

Pseudo-static RAM uses chip enable signal C.
An auto-refresh cycle is executed on the condition that the output enable signal OE (refresh control signal RFSH) is temporarily set to the low level for a relatively short time (jpip) with E fixed at the high level. At this time, a refresh address for specifying a word line to be refreshed is supplied from a refresh counter RFC built in the pseudo-static RAM.

In the pseudo-static RAM, a total of two word lines specified by a refresh counter RFC are simultaneously set to a selected state, and a refresh operation is performed on a total of 2048 corresponding memory cells at the same time. The refresh counter RFC is automatically updated after its output signal, ie, the refresh address, is taken into the X address buffer.

FIG. 10 shows a timing diagram of one embodiment of the self-refresh cycle of the pseudo-static RAM.

Pseudo-static RAM uses chip enable signal 5.
The self-refresh mode is set on the condition that the output enable signal OE (refresh control signal RFSH) is kept at a low level for a relatively long time (tFAs) with 100 fixed at a high level.

In the pseudo-static type RAM, one self-refresh cycle in a self-refresh mode is first executed at the same time as the reflation/no-shtimer counter circuit SRC is activated. Thereafter, the refresh timer counter circuit SRC outputs a refresh activation signal of a predetermined frequency, thereby repeating the self-refresh cycle at a corresponding period. At this time,
The refresh address is the refresh counter RFC
are specified sequentially by

In this self-refresh cycle, in the pseudo-static RAM, eight memory arrays are brought into operation at the same time, and a total of eight word lines are brought into the selected state.

As a result, the 8192 memory cells coupled to these word lines are refreshed all at once, reducing the average operating current of the memory array.

Among the access times shown in the timing diagrams of FIGS. 6 to 10 above, typical access times are as follows. tllc is the random read/write cycle time, tCEA is the chip enable access time, and t*wc is the read-modify
is the write cycle time, tova is the output enable access time, tA)l is the address hold time, tAs is the address set up time, t is the chip enable precharge time, and tyc is the auto This is the refresh cycle time.

The pseudo-static RAM of this embodiment is guaranteed to operate within a voltage range of approximately 3.6V to 1.6V, as described above. In this way, the voltage fluctuation range is 2V, which is small in terms of absolute value, but when viewed from the minimum operating voltage of 1.6V, the maximum operating voltage of 3.6V is about twice that, which is a relatively large voltage. . Under such a relatively large voltage range, the fluctuation range of the operating speed and current consumption becomes relatively large.

Since it is possible to operate with multiple types of battery voltages with different generated voltages as described above, the AC characteristics such as access time and DC characteristics such as current consumption at multiple operating voltages are determined as follows. It shall be defined as shown in Table-2 and Table-3.

Table 2 shows the minimum voltage (1,6V) min, center voltage (
An example of AC characteristics consisting of a plurality of representative AC characteristics at a maximum voltage (2,6 V) typ and a maximum voltage (3,6 V) max is shown.

In this Table-2, the unit is ns (nanosecond).

Table 3 lists the minimum voltage (1,6V) min, center voltage (
An example of DC characteristics consisting of a plurality of representative DC characteristics at a maximum voltage (3,6 V) typ and a maximum voltage (3,6 V) max is shown.

Table-2 Table-3 Here, I CCI is the current consumption during memory access; is the current consumption in self-refresh mode.

The above minimum voltage of 1.6V assumes that lead batteries are mainly used, the center voltage of 2°6V assumes that Ni-Cd and lithium batteries are used, and the maximum voltage of 3°6V assumes that lithium batteries are used. This is what I expected. By determining the AC and DC characteristics for each different battery voltage in this way, it becomes easier for the user to use the device. That is, if worst-case AC characteristics and DC characteristics are determined as in the past, users using nickel-cadmium batteries or lithium batteries will be forced to use the PSRAM at a performance lower than that of the PSRAM. As mentioned above, in CMOS integrated circuits that are intended to be used in a manner where the relative voltage fluctuation width is large, the speed and current consumption fluctuation range depending on the operating voltage is large, so the AC and DC characteristics must be adjusted according to the respective power supply voltages. By showing this, the user can construct an extremely rational system that takes advantage of the performance of the CMOS integrated circuit. In particular, when the battery voltage is used as the operating voltage as in this example, since the battery capacity is limited, displaying the above DC characteristics for each voltage allows the user to take battery life into consideration. Since the system can be designed, the system will not stop due to unexpected battery discharge, etc.

When operating a CMOS circuit in a relatively large voltage range with a relatively small voltage as described above, the MOSFE
The conductance characteristics of T vary relatively greatly depending on the operating voltage. Therefore, as in conventional CMOS circuits, CMO
If an S inverter circuit is used as a delay circuit, the delay time will be highly dependent on voltage, and stable timing operation cannot be expected.

FIG. 11 shows a circuit diagram of an embodiment of a delay circuit suitable for a CMOS integrated circuit according to the present invention.

In this embodiment, in order to eliminate the voltage dependence of the delay time, a resistor R1 made of a polysilicon layer and an MO5 capacitor C
A delay circuit is constructed using a time constant circuit consisting of 1. The figure shows an example of a delay circuit that forms an output signal that rises with a delay of time TD when the input signal A rises from a low level to a high level.

Input signal A is input to the time constant circuit made up of the resistor R1 and capacitor C1 via the CMOS inverter circuit N1. The delay signal B formed by the time constant circuits R1 and C1 is amplified by a CMOS inverter circuit N2 and transmitted to a time constant circuit composed of a similar resistor R2 and capacitor C2. The delay signal C formed by the time constant circuits R2 and C2 is supplied to one input of the Nant gate circuit G1. The input signal A is supplied to the other input of this Nant gate circuit Gl. The output signal of the Nant gate circuit Gl is output as a delayed signal through an output CMOS inverter circuit N3.

Although not particularly limited, the capacitor cl connects the source and drain of the N-channel MO3FET in common and connects it to the ground potential point of the circuit, and the capacitor C2 connects the source and drain of the P-channel MO5FET in common to the power supply voltage Vcc. It is connected to.

FIG. 12 shows a waveform diagram for explaining an example of the operation of the delay circuit.

When input signal A changes from low level to high level,
Correspondingly, the output signal of the inverter circuit Nl changes from high level to low level, and the signal B changes from high level to low level in accordance with the time constant of the resistor R1 and capacitor CI. In response to this change in signal B, the output signal of inverter circuit N2 changes from low level to high level,
The signal C changes from low level to high level according to the time constant of the resistor R2 and capacitor C2.

The Nant gate circuit G1 opens its gate in response to the input signal A being at a high level (logic "1"), and essentially operates as an inverter circuit. Therefore, when the level of the signal C changes from low level to high level and reaches the rosin threshold voltage, the output signal changes from high level to low level. In this way, the delayed signal output through the inverter circuit N3 is controlled by the time constant circuits R1, CI and R2.
, 'i! corresponding to the time constant of C2! ! Rising from low level to high level with court time TD.

In addition, inverter circuits N1 to N3 and gate circuit G
1 also has a signal propagation delay time, but since it is smaller than the above time constant, the above delay time TD is determined by the time constant of the above time constant circuits R1, CI and R2゜C2. It's not too much to say.

When input signal A changes from high level to low level,
Accordingly, the output signal of the Nant gate circuit G1 changes to high level. That is, even if the level of signal C is still high, the output signal is changed to high level regardless of this. As a result, the output signal through the inverter circuit N3 immediately changes to low level. Therefore, the delay circuit of this embodiment has the input signal A as described above.
An output signal is generated which is delayed by the delay time TD only with respect to the rising edge of the signal.

FIG. 13 shows a cross-sectional view of the element structure of one embodiment of the resistor R1 and capacitor C1.

The surface of the element formation region of the P-type semiconductor substrate 1 is covered with ordinary N.
N° type source and drain regions SD are formed by the same manufacturing process as for forming the channel MOSFET.

A thick field insulating film 2 is formed on the semiconductor substrate in areas other than the element formation region. The above pair of sources,
A thin gate insulating film 4 is formed in the element formation region including the substrate surface sandwiched by the drain region SD.

Then, a first polysilicon layer is formed on the field insulating film 2 and the gate insulating film 4. Semiconductor impurities are introduced from the surface of this 1Nth polysilicon layer into the portions that constitute the gate electrode and resistor R1 of the MOSFET, and the first conductive polysilicon layer is used as the gate electrode G, resistor R1, and wiring layer. A silicon layer is formed.

An ohmic contact is provided in which the gate oxide film and polysilicon layer on the source and drain regions are selectively removed, and an aluminum layer 5 provides a ground potential thereto.
is provided. Note that the resistor R1 and the gate electrode G acting as one electrode of the capacitor CI are integrally formed, and the delay signal C thus formed is transferred to an N-channel MOS constituting an inverter circuit N2 (not shown).
As the wiring connecting the FET and the gate electrode of the P-channel MO3FET, an aluminum wiring formed in the same process as the aluminum wiring that applies the ground potential to the capacitor C1 is used.

FIG. 14 shows delay time characteristics of a delay circuit according to the present invention and a delay circuit using a conventional inverter circuit. In the figure, the solid line indicates the delay characteristic of the delay circuit according to the present invention, and the broken line indicates the delay characteristic of the delay circuit using the conventional inverter circuit.

The delay circuit of this embodiment utilizes a polysilicon resistance element that is not dependent on power supply and an MO3 capacitor.

As a result, the voltage dependence is large in the low voltage region of 1■ or less due to the power dependence of the inverter circuit inserted mainly for waveform shaping, etc., but the PSRA of this embodiment
A substantially constant delay time y' can be obtained at high voltages starting from around the minimum voltage of 1.6 V that M is intended to guarantee.

On the other hand, when an inverter circuit is used as in the past, the delay time increases rapidly from a voltage of 4.5 V or less, which is not guaranteed in the conventional RAM, and a stable delay time cannot be obtained.

Therefore, the PSRAM according to the present invention guarantees an operating voltage with a relatively wide range at a low voltage.
It is no exaggeration to say that in a MOS circuit, a delay circuit using a polysilicon resistor and an MO3 capacitor as shown in the above embodiment is indispensable in order to perform stable timing operation.

The effects obtained from the above examples are as follows. In other words, (11) By limiting the conditions to the voltage generated by multiple types of batteries whose maximum value is up to about 3.6V, it is relatively easy to access memory under the supply of the above voltage. PARAM-enabled CMOS structure
Alternatively, DRAM can be obtained, and by setting the logic levels at its input/output interface to meet technical standards for low-voltage CMOS circuits, the memory can be accessed using standard logic ICs. You can get the effect of

(By using a dynamic memory cell in which the memory cell is composed of an MO3FET for address selection and a capacitor for information storage as a RAM with a 21CM OS structure, a large storage capacity can be obtained in a battery-powered memory card, etc.). can get.

(3) As a battery-powered CMOS-structured RAM, a pseudo-static RAM with an input/output interface that is compatible with static RAM simplifies refresh operations and allows memory access to be performed in the same way as static RAM. Therefore, it is possible to obtain the effect that it can be made suitable for a battery-powered memory card.

(4) LVCMOS, LVBO and 74HC or A defined by Jedesok Standard Number 8 as the technical standards for the above-mentioned low voltage CMOS circuits.
By using it for C series CMOS logic ICs, it is possible to obtain compatibility with existing ICs.

(5) Operation is possible using voltages generated by multiple types of batteries with a maximum value of approximately 3.6V, and the logic level at the input/output interface satisfies technical standards for low-voltage CMOS circuits. At the same time, by determining the DC and AC characteristics for each of the different operating voltages depending on the type of battery, we provide a user-friendly CMOS integrated circuit that fully demonstrates the performance of the CMOS integrated circuit. The effect of being able to do this is obtained.

(6) Since the above DC and AC characteristics include the memory access time in the built-in RAM and the current consumption in the memory access state and data retention state, the user can calculate the R
The effect is that the system can be designed to fully utilize the performance of AM.

(7) It is operable by the voltage generated by multiple types of batteries whose maximum value is up to about 3.6V, and the internal delay circuit includes a polysilicon resistor and MOS.
By using a time constant circuit consisting of a capacitor,
The advantage is that various timing settings for logic sequence control can be stably performed even at low voltages such as those of lead batteries.

(8) The above-mentioned polysilicon resistor uses the first polysilicon layer that constitutes the gate electrode of the MOSFET to simplify the connection with the MOS capacitor connected to it and to set the resistance value. The effect is that pattern accuracy and stable note resistance values can be obtained.

(9) The lower limit voltage of the plurality of battery voltages mentioned above is the voltage generated by the lead battery, and is set to a predetermined voltage at which the current necessary for the operation of the CMOS circuit is obtained. In addition to being able to extend the operating time with the battery, the above-mentioned lead battery can also be used even when a backflow prevention diode is connected when the battery is used.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, the pseudo-static RAM shown in FIGS. 1-5 may only have its input/output interface compatible with static RAM. That is, at least the address signal and the control signal are static type RA.
It is sufficient if the configuration is similar to that of M.

In addition to pseudo-static RAM, other types of RAM that can be operated with multiple types of battery voltages as in the above embodiments include
It may be a dynamic type RAM, or it may be a RAM having static type memory cells in addition to one using dynamic type memory cells such as the above-mentioned pseudo-static type RAM or dynamic type RAM. However, when applied to such a static type RAM, the storage capacity becomes smaller for the same chip area. It goes without saying that the CMOS integrated circuit can be operated not only by battery voltage, but also by various power supplies that generate similar voltages.

In addition to RAM as mentioned above, various digital control circuits such as microprocessors, and CMOS circuits such as gate arrays can determine the AC characteristics and DC characteristics for each battery voltage to be driven. good. And the first
The delay circuit shown in Figure 1 uses a NOR gate circuit instead of a Nant gate circuit to delay the fall of the input signal, or omit the gate circuit and delay both the rise and fall of the input signal. Various embodiments such as the above can be adopted.

Delay circuits such as those shown in FIGS. 11 and 13 are widely used in CMOS integrated circuits that are operated by battery voltages of multiple types at relatively low voltages, as well as RAMs with CMOS configurations as described above. Available.

The present invention can be widely used in various CMOS integrated circuit devices in addition to the above-described CMOS-configured PSRAM and DRAM.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, by limiting the operating voltage to multiple types of battery voltages whose maximum value is up to approximately 3.6V,
It is possible to obtain a CMOS structured RAM that allows memory access using a plurality of types of batteries. Since AC and DC characteristics such as operating speed and current consumption are determined for each voltage that corresponds to multiple types of batteries, users can select the best one that matches the capabilities of the CMOS circuit according to the battery being used. Can be used efficiently. Stable operation is possible by using a polysilicon resistor that does not have voltage dependence as a delay circuit for operating at low voltages as described above.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a memory card to which the present invention is applied, and FIG. 2 shows a selection circuit, a timing generation circuit, and a voltage generation circuit of a pseudo-static RAM used in the above-mentioned memory card, etc. FIG. 3 is a block diagram showing an embodiment of the memory array of the pseudo static type RAM, and FIG. 4 shows the direct peripheral circuits and data input/output of the pseudo static type RAM. FIG. 5 is a block diagram showing an embodiment of the circuit; FIG. 5 is a geometrical layout diagram showing an embodiment of the pseudo-static RAM on the semiconductor substrate surface; FIG. 6 is a lead diagram of the pseudo-static RAM. FIG. 7 is a timing diagram showing an example of a write cycle of the pseudo-static RAM, and FIG. 8 is a timing diagram showing an example of a do-modify write cycle of the pseudo-static RAM. 9 is a timing diagram showing an example of an auto-refresh cycle of the pseudo-static RAM, FIG. 10 is a timing diagram showing an example of a self-refresh cycle of the pseudo-static RAM, and FIG. A circuit diagram showing an embodiment of the delay circuit according to the invention, FIG. 12 is a waveform diagram for explaining an example of its operation, and FIG. 13 shows an embodiment of the resistor and capacitor used in the delay circuit. FIG. 14, which is a sectional view of the element structure, is a characteristic diagram showing the voltage dependence of the delay circuit according to the present invention and a delay circuit using a conventional inverter circuit. RAM...Random access memory, PSRAM...
・Pseudo-static RAM, TG...timing generation circuit, XAB...X address buffer, YAB...Y address buffer, WC...word line rear circuit, TMR
・・Refresh timer circuit, SCR・・Refresh timer counter circuit, 5CNTR・・Refresh timer counter unit circuit, PC・・Precharge system′
411 circuit, PXD...X predecoder, RFC...refresh counter, CNTR...refresh counter unit circuit, XRO-XR3...X system redundant circuit, φXG
. . . Word line drive voltage generation circuit, PWD . . Word line selection drive signal generation circuit, PRWD . . Redundant word line selection drive voltage generation circuit, SN. PN...Sense amplifier drive circuit, PYD...Y predecoder, YRACO~YRAC7...Y system redundant circuit, MA
LL-MARR...Main amplifier, DIB...Data input cover sofa, DTLL-DIRR...Writing circuit, W
S...Write selection circuit, DOB...Data output cover sofa, O3L...Output selection circuit, HVC, VBB, VL...
・Voltage generation circuit, XDLOL-XD3R-・'X5”:
J-da, YDO-YD3...Y decoder, MARYOL
~MARY3R...Memory array, 5AOL-3A3R
...Sense amplifier, C3OL-C33R...Column switch 01-C2...Capacitor, R1-R2...Resistance, N1
-N3...CMOS inverter circuit, G1...Nant gate circuit, 1...semiconductor substrate, 2...field insulating film, 3...first polysilicon layer (resistance, gate electrode),
4. Gate oxide film, 5. Aluminum wiring. Figure 1

Claims (1)

[Claims] 1. An input/output interface including a RAM whose memory can be accessed under the supply of voltage generated by a plurality of types of batteries whose maximum value is up to about 3.6V. 1. A CMOS integrated circuit device, wherein the logic level of the CMOS integrated circuit device is set to satisfy technical standards for low-voltage CMOS circuits. 2. In the above RAM, the memory cells are MOS for address selection.
2. The CMOS integrated circuit device according to claim 1, wherein the CMOS integrated circuit device is constructed using a dynamic memory cell consisting of a FET and an information storage capacitor. 3. The CMOS integrated circuit device according to claim 2, wherein the RAM constitutes a pseudo-static RAM having an input/output interface compatible with a static RAM. 4. A patent characterized in that the above-mentioned technical standards for low voltage CMOS circuits are for LVCMOS and LVBO determined by JEDEC Standard Number 8, and 74HC or AC series CMOS logic ICs. CM according to claim 1, 2 or 3
OS integrated circuit device. 5. It is said that it can operate with the voltage generated by multiple types of batteries whose maximum value is up to about 3.6V,
The logic level at the input/output interface satisfies technical standards for low-voltage CMOS circuits, and the DC characteristics and AC characteristics are determined for each of a plurality of different operating voltages depending on the type of battery. CMOS
Integrated circuit device. 6. The CMOS integrated circuit device according to claim 5, wherein the DC characteristics and AC characteristics include the memory access time in the built-in RAM and the current consumption in the memory access state and data retention state. . 7. It is said that it can operate with the voltage generated by multiple types of batteries whose maximum value is up to about 3.6V,
A polysilicon resistor and MO are used as internal delay circuits.
A CMOS integrated circuit device characterized by using a time constant circuit consisting of an S capacitor. 8. The CM according to claim 7, wherein the polysilicon resistor uses a first polysilicon layer constituting a gate electrode of a MOSFET.
OS integrated circuit device. 9. The delay circuit forms an operation timing signal for a RAM whose read/write operations are enabled by supplying voltages generated by a plurality of types of batteries whose maximum value is up to about 3.6V. and its RAM
Claim 7, characterized in that the logic level at the input/output interface is set to satisfy technical standards for low voltage CMOS circuits.
9. The CMOS integrated circuit device according to item 8. 10. The delay circuit forms an operation timing signal for a RAM whose read/write operations are enabled by supplying voltages generated by a plurality of types of batteries whose maximum value is up to about 3.6V. The CMOS according to claim 7, 8, or 9, wherein the CMOS is used in a battery, and has DC characteristics and AC characteristics determined for each different operating voltage depending on the type of battery. Integrated circuit device. 11. A patent characterized in that the lower limit voltage among the plurality of types of battery voltages is a voltage generated by a lead battery and is a predetermined voltage at which the current necessary for the operation of the CMOS circuit is obtained. A CMOS integrated circuit device according to claim 1, 5, or 7.