JPH0441379Y2 - - Google Patents
Info
- Publication number
- JPH0441379Y2 JPH0441379Y2 JP1985135183U JP13518385U JPH0441379Y2 JP H0441379 Y2 JPH0441379 Y2 JP H0441379Y2 JP 1985135183 U JP1985135183 U JP 1985135183U JP 13518385 U JP13518385 U JP 13518385U JP H0441379 Y2 JPH0441379 Y2 JP H0441379Y2
- Authority
- JP
- Japan
- Prior art keywords
- reset
- semiconductor device
- power supply
- circuit
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 31
- 230000002093 peripheral effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 102100029968 Calreticulin Human genes 0.000 description 1
- 101100326671 Homo sapiens CALR gene Proteins 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
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- Electronic Switches (AREA)
Description
【考案の詳細な説明】
＜産業上の利用分野＞
本考案は、リセツト端子を有するIC等の第１
の半導体装置と、リセツト端子をもたないIC等
の第２半導体装置とを備えた電子機器に用いられ
るリセツト回路に関するのもである。[Detailed description of the invention] <Industrial application field> The present invention is applicable to the first IC, etc. that has a reset terminal.
The present invention relates to a reset circuit used in an electronic device including a semiconductor device and a second semiconductor device such as an IC that does not have a reset terminal.
＜考案の概要＞
本考案は上記リセツト回路において、上記第１
の半導体装置用のリセツトパルス印加時に、上記
第２の半導体装置への電源供給を一時的に遮断す
るスイツチイング回路を、前記第２の半導体装置
の電源電圧供給路に挿入することにより、前記第
１及び第２の半導体装置を同時にリセツトできる
ようにしたものである。<Summary of the invention> The present invention provides the first reset circuit in the above reset circuit.
By inserting into the power supply voltage supply path of the second semiconductor device a switching circuit that temporarily cuts off the power supply to the second semiconductor device when a reset pulse is applied for the second semiconductor device, The first and second semiconductor devices can be reset at the same time.
＜従来の技術＞
従来から、コンピユータ等の電子機器には、
CPUをはじめ各種ペリフエラル、ゲートアレイ、
論理IC等の半導体装置が使用されているが、そ
の中にはリセツト端子をもたない半導体装置があ
つた。例えば、既存のペリフエラルについては、
Ｚ−80DMAがあり、またゲートアイレ等を論理
設計する際にどうしても入出力端子が不足する場
合等は、リセツト端子を設けないこともある。<Conventional technology> Traditionally, electronic devices such as computers have
Various peripherals including CPU, gate array,
Semiconductor devices such as logic ICs are used, but some of them do not have a reset terminal. For example, for existing peripherals,
If there is a Z-80DMA and there is a shortage of input/output terminals when designing the logic of a gate array, etc., a reset terminal may not be provided.
尚、本文中で使用している「ペリフエラル」と
は、CPU以外の周辺LSIのことを意味している。
例えば、Ｚ−80フアミリのＺ−80DMA，Ｚ−
80PIO，Ｚ−80SIO等や各種CRTC，FDC等であ
る。 Note that the term "peripheral" used in this text refers to peripheral LSIs other than the CPU.
For example, Z-80DMA of Z-80 family, Z-
These include 80PIO, Z-80SIO, etc., various CRTCs, FDCs, etc.
＜考案が解決しようとする問題点＞
上記のようにリセツト端子をもたない半導体装
置を使用する場合、最も留意すべき点は、何らか
のソフト的，ハード的要因によつて、その半導体
装置が正常に作動しなくなり、他の回路の動作に
影響を与えることである。例えば、Ｚ−80DMA
はその動作時にはバスを専有するため、CPUを
バスから切り離してしまうが、この時Ｚ−
80DMAへのプログラミングが誤まつていたりす
ると、Ｚ−80DMAはバスをCPUへ返さなくなつ
てしまう。この状態を外部から見ると、コンピユ
ータが暴走したようになる。<Problems to be solved by the invention> When using a semiconductor device that does not have a reset terminal as described above, the most important point to keep in mind is that the semiconductor device may malfunction due to some software or hardware factor. This may cause the circuit to stop working and affect the operation of other circuits. For example, Z-80DMA
Because it monopolizes the bus during its operation, it disconnects the CPU from the bus, but at this time Z-
If the programming to the 80DMA is incorrect, the Z-80DMA will not return the bus to the CPU. Looking at this state from the outside, it looks like the computer has gone out of control.
このような場合、通常はユーザーがリセツトス
イツチを操作することによりCPUや各ペリフエ
ラル等がリセツトされるため、暴走状態から抜け
出せるが、Ｚ−80DMAのようにリセツト端子の
ないペリフエラル等では、リセツトできないた
め、暴走状態から抜け出せない。特にＺ−
80DMAの場合は、第２図から分かるように、電
源供給路を切断するしか方法がないが、このよう
に電源供給路を切断して電源供給を遮断してしま
うと、メモリ内容が破壊されるため、好ましくな
かつた。 In such a case, the user can usually reset the CPU and each peripheral by operating the reset switch, so the runaway state can be overcome, but peripherals such as the Z-80DMA that do not have a reset terminal cannot be reset. , I can't get out of a runaway state. Especially Z-
In the case of 80DMA, as you can see from Figure 2, the only way is to disconnect the power supply path, but if you disconnect the power supply path and cut off the power supply in this way, the memory contents will be destroyed. Therefore, it was not desirable.
＜問題点を解決するための手段＞
上記従来の問題点を解決するために、本考案で
は、リセツト端子を有する半導体装置リセツト用
のリセツトパルスの印加に応じて、リセツト端子
をもたない半導体装置への電源供給を一時的に遮
断するスイツチング回路を、前記リセツト端子を
もたない半導体装置の電源供給路に挿入したもの
である。<Means for Solving the Problems> In order to solve the above conventional problems, in the present invention, in response to the application of a reset pulse for resetting a semiconductor device having a reset terminal, a semiconductor device having no reset terminal is reset. A switching circuit for temporarily cutting off the power supply to the semiconductor device is inserted into the power supply path of the semiconductor device that does not have the reset terminal.
＜作用＞
従つて、他の半導体装置等に影響を与えること
なく、これらの半導体装置と同時に、リセツト端
子をもたない半導体装置をリセツトすることがで
きる。<Operation> Therefore, a semiconductor device without a reset terminal can be reset at the same time as these semiconductor devices without affecting other semiconductor devices.
＜実施例＞
以下、本考案の実施例を図面を用いて説明す
る。<Example> Hereinafter, an example of the present invention will be described using the drawings.
第１図は本考案のリセツト回路のブロツク図で
あり、１は電源スイツチ、２はリセツトパルス発
生器、３はCPU，４はリセツト端子を有する半
導体装置（以下、Z80−SIOを例に上げて説明す
る）、５はリセツト端子をもたない半導体装置
（以下、Z80−DMAを例に上げて説明する）、６
はリセツトスイツチ、７はスイツチング回路であ
る。 Figure 1 is a block diagram of the reset circuit of the present invention, in which 1 is a power switch, 2 is a reset pulse generator, 3 is a CPU, and 4 is a semiconductor device having a reset terminal (hereinafter, Z80-SIO is taken as an example). 5 is a semiconductor device that does not have a reset terminal (hereinafter, Z80-DMA will be explained as an example), 6 is a semiconductor device that does not have a reset terminal.
7 is a reset switch, and 7 is a switching circuit.
リセツトパルス発生器２は、リセツトスイツチ
６をオン・オフ操作することで、CPU３及びZ80
−SIO４のリセツト端子とスイツチング回路７と
に、リセツトパルスを供給するものであり、ま
た、前記スイツチング回路７は、Z80−DMAの
電源供給路に挿入され、前記リセツトパルスが供
給されたときに、Z80−DMA５への電源供給を
一時的に遮断するものである。 The reset pulse generator 2 controls the CPU 3 and Z80 by turning on and off the reset switch 6.
- A reset pulse is supplied to the reset terminal of the SIO4 and the switching circuit 7, and the switching circuit 7 is inserted into the power supply path of the Z80-DMA, and when the reset pulse is supplied, This temporarily cuts off the power supply to Z80-DMA5.
このように構成されたリセツト回路の場合、リ
セツトスイツチ６をオン・オフ操作すれば、リセ
ツトパルス発生器２からリセツトパルスがCPU
３及びZ80−SIO４のリセツト端子とスイツチン
グ回路７とに供給されるので、CPU３及びZ80−
SIO４がリセツトされるとともに、スイツチング
回路７がZ80−DMA５への電源供給を一時的に
遮断するので、Z80−DMA５もリセツトされる。 In the case of the reset circuit configured in this way, when the reset switch 6 is turned on and off, the reset pulse is sent from the reset pulse generator 2 to the CPU.
3 and Z80-SIO4 reset terminal and switching circuit 7, so CPU3 and Z80-
When SIO4 is reset, switching circuit 7 temporarily cuts off the power supply to Z80-DMA5, so Z80-DMA5 is also reset.
＜考案の効果＞
以上のように本考案のリセツト回路は、リセツ
トスイツチと、前記リセツトスイツチのオン・オ
フ操作により、リセツト端子を有する半導体装置
リセツト用のリセツトパルスが発生されるリセツ
トパルス発生器と、リセツト端子をもたない半導
体装置への電源電圧供給路に挿入され、前記リセ
ツトパルスの印加に応じて、前記リセツト端子を
もたない半導体装置への電源供給を一時的に遮断
するスイツチング回路とを、具備しているため、
前記リセツトスイツチのオン・オフ操作により、
リセツト端子を有する半導体装置等に影響を与え
ることなく、リセツト端子を有する半導体装置と
リセツト端子をもたない半導体装置を同時にリセ
ツトすることができる。<Effects of the Invention> As described above, the reset circuit of the present invention includes a reset switch and a reset pulse generator that generates a reset pulse for resetting a semiconductor device having a reset terminal by turning on and off the reset switch. , a switching circuit that is inserted into a power supply voltage supply path to a semiconductor device that does not have a reset terminal, and temporarily cuts off power supply to the semiconductor device that does not have a reset terminal in response to application of the reset pulse; Because it is equipped with
By turning on and off the reset switch,
It is possible to simultaneously reset a semiconductor device having a reset terminal and a semiconductor device not having a reset terminal without affecting the semiconductor device having the reset terminal.
第１図は本考案のリセツト回路のブロツク図、
第２図は従来のリセツト回路のブロツク図であ
る。
１……電源スイツチ、２……リセツトパルス発
生器、３……CPU、４……Z80−ISO、５……
Z80−DMA、６……リセツトスイツチ、７……
スイツチング回路。
Figure 1 is a block diagram of the reset circuit of the present invention.
FIG. 2 is a block diagram of a conventional reset circuit. 1...Power switch, 2...Reset pulse generator, 3...CPU, 4...Z80-ISO, 5...
Z80-DMA, 6...Reset switch, 7...
switching circuit.
Claims (1)
置と、リセツト端子をもたないIC等の第２の半
導体装置とを備えた電子機器に用いられるリセツ
ト回路において、 リセツトスイツチと、 前記リセツトスイツチのオン・オフ操作によ
り、前記第１の半導体装置リセツト用のリセツト
パルスが発生されるリセツトパルス発生器と、 前記第２の半導体装置への電源電圧供給路に挿
入され、前記リセツトスイツチのオン・オフ操作
により発生するリセツトパルスの印加に応じて、
前記第２の半導体装置への電源供給を一時的に遮
断するスイツチイング回路とを、 具備してなり、前記リセツトスイツチのオン・
オフ操作により、前記第１及び第２の半導体装置
を同時にリセツトすることを特徴としたリセツト
回路。[Claims for Utility Model Registration] A reset circuit used in an electronic device including a first semiconductor device such as an IC having a reset terminal and a second semiconductor device such as an IC without a reset terminal. a reset pulse generator that generates a reset pulse for resetting the first semiconductor device when the reset switch is turned on and off; the reset pulse generator is inserted into a power supply voltage supply path to the second semiconductor device; In response to the application of a reset pulse generated by the on/off operation of the reset switch,
a switching circuit that temporarily cuts off power supply to the second semiconductor device, and a switching circuit that turns on/off the reset switch.
A reset circuit that simultaneously resets the first and second semiconductor devices by an off operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985135183U JPH0441379Y2 (en) | 1985-09-03 | 1985-09-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985135183U JPH0441379Y2 (en) | 1985-09-03 | 1985-09-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6244329U JPS6244329U (en) | 1987-03-17 |
| JPH0441379Y2 true JPH0441379Y2 (en) | 1992-09-29 |
Family
ID=31037124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985135183U Expired JPH0441379Y2 (en) | 1985-09-03 | 1985-09-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0441379Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5725024A (en) * | 1980-07-21 | 1982-02-09 | Hitachi Ltd | Resetting circuit of microcomputer |
| JPS60231224A (en) * | 1984-04-28 | 1985-11-16 | Olympus Optical Co Ltd | Reset circuit |
-
1985
- 1985-09-03 JP JP1985135183U patent/JPH0441379Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5725024A (en) * | 1980-07-21 | 1982-02-09 | Hitachi Ltd | Resetting circuit of microcomputer |
| JPS60231224A (en) * | 1984-04-28 | 1985-11-16 | Olympus Optical Co Ltd | Reset circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6244329U (en) | 1987-03-17 |
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