JPH0440108A - Offset cancel circuit - Google Patents

Abstract

PURPOSE:To cancel offset caused by supplying a bias current by providing an equivalent dummy circuit, and supplying the current from an output transistor on the side to be paired with an output transistor on the side of a differential amplifier circuit for supplying the bias current, to this equivalent dummy circuit. CONSTITUTION:An input side differential amplifier circuit 6 is composed of differential amplifiers 11 and 12, which are connected in two steps, and a level shift circuit 7 is connected to the output of the differential amplifier 12 by a current mirror. A dummy load circuit 8 constitutes a circuit equivalent to a transistor 131 of a buffer amplifier 5 receiving a bias current Ib. The dummy load circuit 8 makes the same current value flow out from a transistor 121 opposite to the transistor 122 on the side of outputting the bias current as the bias current which flows out from a transistor 122. In such a case, since an output side 14a of the buffer amplifier 5 is fed back to an input side, the output currents of the transistors 121 and 122 on the output side of the differential amplifier 12 are made equal even in an operational state. Therefore, the offset is canceled even for the buffer amplifier 5 in the next step of the differential amplifier circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to an offset cancel circuit, and more specifically, it has a current output amplifier of a differential amplifier circuit on the input side, and the output of the current output amplifier is connected to a buffer amplifier. The present invention relates to an offset canceling circuit capable of canceling an offset caused by a current output amplifier generating a bias current to be supplied to a buffer amplifier in an amplifier circuit that receives a signal and generates an output signal.

[Prior Art] FIG. 2 is an example of a conventional amplifier circuit in which a puffer amplifier receives the current output of a differential amplifier circuit provided on the input side.

In the figure, a differential amplifier circuit 2o is an amplifier circuit provided at the input stage, and includes transistors 21.2 for differential amplification.
2, and a constant current source 23 with a current value IA. Diode-connected current mirror load transistors 24, 25 are inserted on the collector side of the transistors 21, 22, and their outputs are taken out by transistors 27, 28 that are current mirror partners of these transistors 24, 25. This output is connected to a current mirror load circuit 29 inserted on the collector side of each of these transistors.
The signal is level-shifted by (transistors 29ax29b) and output to the next stage buffer amplifier 30 from the connection point between the collector of the transistor 28 and the current mirror transistor 29b.

The buffer amplifier 30 here includes a Darlington-connected transistor 32 having a constant current circuit 31 on the emitter side.
．． It is an emitter follower composed of 33.

In such a circuit, from the input stage to the buffer amplifier 30
A bias current Ib is supplied to the input stage, and an offset occurs in the input stage differential amplifier circuit 20 due to the influence of the bias current Ib. Therefore, in order to reduce this offset as much as possible, it is necessary to reduce the bias current Ib as much as possible.

For this reason, here, the buffer amplifier 30 is a Darlington-connected amplifier so that the bias current Ib can be further reduced.

[Problem to be Solved] However, even if the bias current Ib is reduced in this way, an offset voltage is generated depending on the value of the current value IA of the constant current source 23, so when the value of the current value IA is small, Rather, the offset voltage Vof becomes larger. In other words, this is because the bias current 1b is output under the following conditions.

Here, if the bias current Ib is reduced, the offset voltage V
Although of becomes small, in order to make Ib small, the current of the constant current circuit 31 must be made small, and there is a drawback that the dynamic range is limited by the load impedance connected as the next stage.

The present invention solves the problems of the prior art, and provides an offset cancellation circuit that can generate a bias current by balancing a current output amplifier system of a differential amplifier circuit configuration in the input stage. The purpose is to

[Means for Solving the Problems] The configuration of the offset canceling circuit of the present invention to achieve the above object has a bias relationship equivalent to the bias relationship of the input transistor to which the bias current of the next stage amplifier is supplied, and An equivalent dummy circuit is provided in which the relationship between input current and output current is equivalent to that of the input transistor, and current is transferred from the output transistor that is paired with the output transistor that supplies the bias current of the differential amplifier circuit to the equivalent dummy circuit. By supplying , the offset due to the supply of bias current is canceled.

[Operation] In this way, an equivalent dummy load circuit is provided, and the same amount of current as the current on the bias current output side is generated from the output transistor that is paired with the bias current output side of the differential amplifier circuit of the current output amplifier on the input side. By taking out as the output current,
Since the output currents of the respective phase output transistors can be balanced, the input stage differential amplifier circuit operates in a balanced state, and no offset occurs.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a low pass filter (LPF) to which the offset canceling circuit of the present invention is applied.

In FIG. 1, 1 is an LPF, 2 is its active integrating circuit, 3 is a variable six-stage amplifier that constitutes the current output amplifier of its input stage, 4 is its integrating capacitor, and 5 is its integrating capacitor. This is the next stage buffer amplifier.

The variable G-amp 3 is inserted between a differential amplifier circuit 6 in the input stage, a level shift circuit 7 that receives the output of the differential amplifier circuit 6, and the output a side of the level shift circuit 7 and ground (GND). and a capacitor C for integration.

The input side differential amplifier circuit 6 includes a two-stage connected differential amplifier 11.
12, and the level shift circuit 7 is composed of a differential amplifier 12.
A current mirror is connected to the output of The integration time constant of such an integration circuit 2 is determined by the capacitance of the capacitor C and the output impedance of the differential amplifier circuit 6.

The differential amplifier 11 includes N-type bipolar transistors 111 and 112 for differential amplification, and a constant current source 11 with a current value I3.
3. Diode-connected N-type bipolar load transistors 113 and 114 are respectively inserted on the collector side of the transistor 11L112. The outputs of these respective collectors are input to the differential amplifier 12, and the base of the transistor 111 is connected to the input terminal (IN).
11a to receive input signals.

The differential amplifier 12 includes N-type bipolar transistors 121 and 122 for differential amplification that receive the respective outputs of the differential amplifier 11 at their respective bases, and a constant current source 123 having a current value I4. Transistor 121.122
P-type bipolar transistors 124 and 125, which are diode-connected current mirror loads, are inserted on the collector side of the transistor.

The L//'C shift circuit 7 includes a transistor 124.1.
It has P-type bipolar transistors 71 and 72 which are the counterpart of the current mirror No. 25, and outputs from a current mirror load circuit consisting of N-type bipolar transistors 73 and 74 inserted on the collector side of each of these transistors. The level of the collector of the transistor 72 and the current mirror transistor 74 are shifted.
An output is generated at the connection point 7a.

The buffer amplifier 5 receives a bias current I from this output cuff a.
The emitter follower 14 includes a differential amplifier 13 that receives the signal B and an emitter follower 14 that receives the output of the differential amplifier 13. The emitter follower 14 has a constant current circuit 142 on the emitter side.
The output of the emitter follower 14 (output terminal (OUT) 1
4a) are all fed back to the opposite phase side of the differential amplifier 13 to form a buffer amplifier. This output is
It is also fully fed back to the base of the transistor 112 of the differential amplifier 11 in the input stage.

The differential amplifier 13 includes N-type bipolar transistors 131 and 132 for differential amplification, and a current source 133 thereof. P-type bipolar transistors 134 and 135 are inserted as a current mirror load circuit on the collector side of the transistors 131 and 132, and the bias current I from the input stage is applied to the base of the transistor 131.
receive b. Then, it is output from the collector of the transistor 135, and the output is added to the base of the transistor 141.

A dummy load circuit 8 constitutes a circuit equivalent to the transistor 131 of the buffer amplifier 5 receiving the bias current 1b. This has a transistor 161 with almost the same characteristics as the transistor 131, and a diode-connected transistor 164 having the same form and almost the same characteristics as the diode-connected transistor 134 inserted into the collector of the transistor 131 is inserted as a load at its collector. Similarly to the transistor 134, it is connected to the +VCC power supply line 15. Also, transistor 1
A transistor 163 is provided downstream as a transistor corresponding to the current source 133 provided downstream of the current source 133, and its emitter is connected to the ground line (GN
D) connected to 16.

Therefore, the collector potential of the transistor 161 in a steady state is the same as the collector potential of the transistor 131. Furthermore, the same bias voltage as the base bias voltage of transistor 131 is applied to the base of transistor 161. This voltage is provided by bias circuit 9.

The bias circuit 9 is provided to generate a bias voltage equal to the bias voltage of the transistor 131, has its base connected to a bias voltage vb equal to the bias voltage vb of the input terminal 11a, and has its emitter connected to the constant current source 91. A transistor 92 is connected to the power supply line 15 via a transistor 92 whose collector is grounded, and a bias voltage Vb+I generated on the emitter side of this transistor 92.
The transistor 93 receives a voltage of Vf (forward voltage drop of the transistor) at its base and outputs IVf to its emitter.
Generates a low bias voltage vb.

The emitter of transistor 93 is connected to the base of transistor 161, resulting in
A bias voltage vb is applied to the base of 1. As a result, the base of transistor 161 is clamped to bias voltage vb.

Here, the collector side of the transistor 93 is connected to the collector of a transistor 121 for differential amplification, and receives the output of this transistor. Further, the base of the transistor 163 corresponding to the constant current circuit 133 is connected to the transistor 1
33 and the collector and base of the transistor 133a, a constant current source 142a is connected to the connection point between the collector and the base of the transistor 133a, and a current of I2 is passed through the constant current source 142a. Also, the transistor 163°133
．． Resistors R1 and R2°Ri are connected to 133a, respectively. These transistors 163.133,13
The area ratio of the resistors 3a is 1:2:1, and the ratio of the values of the resistors R1tR2tRi is 1:2:1. Therefore, 1/2 of the current of the transistor 133
flows into transistor 163. This is equal to the current flowing between the collector and emitter on the output side of the transistor 131 of the differential amplifier 13 in a steady state.

As a result, the transistor 161 becomes a circuit whose bias relationship is equivalent to that of the transistor 131.

Here, as described above, the output 14a is connected to the base of the transistor 112, which is an input with an opposite phase to this output, and the output side is fully fed back to the input stage. Therefore, from the collector of transistor 121 to transistor 93
Assuming that the current flowing in is Ia, this current Ia is approximately equal to the aforementioned bias current 1b.

That is, in a steady state with no signal, the output side is fed back to the input side, so the transistors 131 and 132 are in a balanced state, and the collector currents flowing through them are considered to be equal. Therefore, transistor 131
The base potential of is the bias voltage vb.

If the current of the transistor 133 is If, this bias current Ib becomes Ib=Ix/2βNPN. However, βNPM is assumed to be hfe of an NPN transistor.

On the other hand, as transistors integrated at the same time, the characteristics of the transistor tet and the transistor 131 are almost the same.

The transistor 183 receives the current Il of the transistor 133.
Since current I2 (=It /2) which is 1/2 of
A current of (=It/2) also flows through the transistor 161. Moreover, the base potential of the transistor 161 is the same voltage vb as that of the transistor 133. The potential relationship on the collector side is also the same, and the current gain β is also almost the same.

Therefore, current 1a=11/2β−11/2β2:Ir/
2β=Ib.

Therefore, transistor 121.1 of differential amplifier 12
22, a current Ib corresponding to a bias current flows out from each collector. Therefore, even if the differential amplifier circuit 6 in the input stage supplies the bias current Ib to the buffer amplifier 5 in the next stage, a current 1a equivalent to that is transmitted from the collector of the transistor 121 of the differential amplifier 12 to the equivalent dummy load circuit 8. outflow against. Therefore, no offset occurs in the differential amplifier 12. Mochichin, differential amplifier 11
There is no offset in either.

In this way, the dummy load circuit 8 causes the same current value as the bias current flowing out from the transistor 122 to flow out from the transistor 121 on the opposite side to the transistor 122 on the bias current output side.

Further, in the above case, since the output side 14a of the buffer amplifier 5 is fed back to the input side, the output currents of the output side transistors 121 and 122 of the differential amplifier 12 are the same even in the operating state. Therefore, the above relationship holds true not only in the steady state but also in the operating state. That is, the dummy load circuit 8 operates in the same way as the transistor 131, has the same characteristics, and receives the input current in the same phase as the bias current. As a result, the output current of the same value flows through the dummy transistor 131, so even if the transmission is in a certain operating state, the same operation is performed, and the differential amplifier circuit in the input stage is also connected to the buffer amplifier in the next stage. This results in a balanced circuit with almost no offset.

By the way, the integrating circuit 2 has an emitter resistor Re inserted into the emitter side of the transistors 111 and 112 of the differential amplifier 11, and a current whose one end is commonly connected to the resistor Re and whose other end is connected to the ground line 16. It has a source 113. Similarly, the differential amplifier 12 also has a transistor 121.
, 122, and has a current source 123 whose other end is connected to the ground line 16. In the variable G amplifier 3 having such a configuration, the current source 113
．． 123 current value I3t I4 is applied to each differential amplifier 11.
Determine the switching current ratio of 12. Therefore, the gain G■ is given by: Gm=I4/13*re. However, re is the resistance value of the emitter resistance Re. The integrating circuit 2 having the variable G error amplifier 3 operates as an LPF here.

As explained above, although the example of the LPF is shown in the example, the method of inserting the capacitor is changed, a capacitor is inserted in series with the input, and the variable 6-layer amplifier 3 is connected between the output and the ground. By inserting an impedance, the integrating circuit 2 can be made into a differentiating circuit. This results in H
PF can be configured. Furthermore, a BPF can be constructed by cascading these differentiating circuits and integrating circuits.

In the embodiment, a current output differential amplifier is provided in the input stage, its output is received by the next stage buffer amplifier, and the output of the buffer amplifier is further fed back to the input stage.
The present invention is not limited to a circuit that feeds back from the output stage to the input stage in this way.

If a feedback configuration is not adopted, the output on the side that does not output bias current of the differential amplifier circuit in the input stage will be in the opposite phase to the output side of bias current in the operating state. The current value 1a may be supplied to the dummy load circuit via the phase inversion circuit so that it has the same phase as the current. Therefore, the present invention is not limited to circuits such as the above-mentioned filters, but can be applied to amplifier circuits in general.

[Effects of the Invention] As can be understood from the above explanation, in the present invention, an equivalent dummy load circuit is provided, and the output is paired with the bias current output side of the differential amplifier circuit of the current output amplifier on the input side. By taking out the same amount of current as the bias current output side current from the transistor as the output current, the output current of each phase output transistor can be balanced, so the input stage differential amplifier circuit operates in a balanced state. However, no offset occurs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a low-pass filter (LPF) to which the offset canceling circuit of the present invention is applied, and FIG. 2 is a block diagram of a conventional offset-reducing circuit. 1... LPF, 2... Integrating circuit, 3... Variable G-amplifier, 4... Integrating capacitor,
5... Buffer amplifier, 6... Differential amplifier 1 circuit, 7
...Level shift circuit, 8...Dummy load circuit, 9
...Bias circuit.

Claims (1)

[Claims] (1) In an amplifier circuit in which a current output amplifier having a differential amplifier circuit is provided at the input stage, and an amplifier receiving a bias current from the current output amplifier as a next stage amplifier,
An equivalent dummy circuit is provided which has a bias relationship equivalent to the bias relationship of the input transistor to which the bias current of the next stage amplifier is supplied, and whose relationship between the input current and the output current is equivalent to that of the input transistor, and Offset cancellation characterized in that an offset due to the supply of the bias current is canceled by supplying current to the equivalent dummy circuit from an output transistor that is paired with the output transistor that supplies the bias current of the circuit. circuit.