JPH0438826A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To etch semiconductors containing different impurities or concentrations at substantially equal speed by setting the partial pressure ratio of O2 gas to mixture pressure of NF3 gas and the O2 gas to 40% or more in a step of removing the semiconductors containing the different impurities or concentrations simultaneously by using mixture gas of the NF3 gas and O2 gas by plasma etching. CONSTITUTION:A semiconductor surface formed with an N<+> type diffused layer, an N<-> type diffused layer, a P<+> type diffused layer is plasma etched by microwave discharging mixture gas containing NF3 gas and O2 gas. Here, when the partial pressure ratio of the O2 to the pressure of the mixture gas of the NF3 gas and the O3 gas is set to 40% or more, the semiconductors containing different impurities or concentrations are simultaneously etched at substantially equal etching speed. Accordingly, even if a damage layer of the semiconductor is removed, a diffused layer containing high concentration impurity is not excessively etched, but the diffused layers can be etched to necessary minimum limit, and junction leakage of the diffused layer having a shallow junction, improper voltage resistance can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for etching a semiconductor using plasma etching.

(Prior Art) Conventionally, plasma etching performed by microwave discharge using a mixed gas containing NF3 gas and 02 gas has been used as one of the methods for manufacturing semiconductor devices. In this case, it is known that the etching rate of the material to be etched changes greatly depending on the mixing ratio of NF3 gas and 02 gas, and there are various optimum mixing ratios of these gases depending on the material to be etched.

On the other hand, in this etching, semiconductor etching progresses through a chemical reaction with active F atoms dissociated from NF3 gas in plasma, so it is also effective in removing damage from semiconductor surfaces that have been damaged by reactive ion etching. It is used. For example, if a contact hole for electrode connection is made in an insulating film by reactive ion etching,
A damaged layer including an amorphous layer with a depth of about 100 nm is generated on the semiconductor surface, significantly deteriorating the metal/semiconductor junction characteristics. FIG. 6 shows the relationship between the M alloy/Sl Schottky junction characteristics and the amount of damaged layer removed. (a) = (b)
.

(C) shows the relationship between Schottky barrier height, n value, and leakage current with respect to etching depth, and 61 indicates A
j-8t(1%)-Cu(0,5%)/n-3i,
62 is M-8l(1%)-Cu(2,0%)/n-
3t Schottky junction characteristics are shown. As is clear from this figure, in order to obtain a good Schottky junction, it is necessary to perform etching of at least 100 Å or more.

However, in general, diffusion layers with different impurity concentrations have already been formed in the region where the contact hole is to be formed, so if these surfaces are etched at the same time, there is a drawback that the amount of etching will differ depending on the diffusion region. . In particular, when a high concentration of N-type impurities is included, the etching rate is two to three times higher than in other cases, which causes junction leakage and breakdown voltage failure in a diffusion layer having a shallow junction.

(Problems to be Solved by the Invention) In conventional manufacturing methods, when semiconductors having different impurities or concentrations are etched at the same time, there is a problem in that the amount of etching of the semiconductors differs depending on the impurity or concentration.

In view of the above points, the present invention provides a method for manufacturing a semiconductor device in which semiconductors having different impurities or concentrations are simultaneously etched at approximately the same rate.

[Structure of the Invention (Means for Solving the Problem) A method for manufacturing a semiconductor device according to the present invention includes a step of simultaneously removing semiconductors with different impurities or concentrations by plasma etching using a mixed gas containing NF3 gas and 02 gas. 02 for the mixed pressure of NFa gas and 02 gas
It is characterized by having a gas partial pressure ratio of 40% or more.

(Function) When performing plasma etching using a mixed gas containing NF3 gas and 02 gas, the partial pressure ratio of 02 gas to the mixed pressure of NF3 gas and 02 gas is 40% or more, so different impurities or concentrations may be included. Etches the semiconductor at approximately equal rates.

(Example) The present invention will be explained in detail below.

Plasma etching is performed on the semiconductor surface on which the N''' diffusion layer, N- diffusion layer, and P'' diffusion layer are formed by discharging a mixed gas containing NF3 gas and 02 gas using microwaves.The conditions are: NF3 gas The flow rate of the mixed gas of and O2 gas was 500 seconds, the pressure was 50 Pa, and the power was 300 gas.

FIG. 2 shows the etching rate of each diffusion layer with respect to the partial pressure ratio of O2 gas in the mixed gas of NF3 gas and O2 gas in this example, and FIG.
The ratio of the etching rate to the gas partial pressure ratio (the etching rate of the N-diffused layer is assumed to be 1) is shown. As shown in FIG. 2, an N-diffusion region 21, an N-diffusion region 22,
The etching rate of the P diffusion region 23 reaches its maximum when the partial pressure ratio P02/(PNF3 + PO2) of the 02 gas is around 0.2, and as the 02 gas is added from this point on, the etching rate gradually decreases. . However, if we focus on the ratio of the etching rates of each diffusion layer, as shown in FIG.
1. The etching rate 12 of the P diffusion layer relative to the N− diffusion layer is 0.4 (Po2/(PNF3 +PO2)).
It gradually approaches 1 from the vicinity, Po2 / (PNF3
+Po2) is around 0.6, the etching rate of each diffusion layer becomes approximately equal.

Therefore, from FIG. 1, when the partial pressure ratio of O2 to the mixed gas pressure of NF3 gas and O2 gas is 40% or more, semiconductors containing different impurities or concentrations can be simultaneously etched at approximately the same etching rate.

Therefore, even when the present invention is used to remove a damaged layer on a semiconductor surface, each diffusion layer can be etched to the minimum necessary level without excessively etching a diffusion layer containing a high concentration of impurities. It is possible to suppress the occurrence of junction leakage and breakdown voltage failure in a diffusion layer having a junction. Furthermore, since the etching speed is lower than that of the conventional method, the etching depth can be easily controlled by controlling the etching time.

Figure 3 shows a Bi CMO3IC in which bipolar elements including C140S elements and Sishitkey transistors coexist.
FIG. 3 shows a cross-sectional view of the contact hole after the contact hole is formed. An element isolation region 33 is formed on a semiconductor substrate 30, and a silicon oxide film 31 is formed thereon. NMO3
The source region 38' and drain region 39' of the device and the emitter region 37 of the bipolar device contain a high concentration of N-type impurity.
The drain region 39' and the base region 3B of the bipolar element contain a high concentration of P-type impurity. and,
A gate electrode 32 is provided between each source and drain region.
is formed.

Further, the Schottky junction 35 contains a relatively low concentration of N-type impurity, and the collector region is formed with an N+ diffusion region 34 for connection to the N" buried diffusion region.

When each contact hole of this Bi CMO8Ic was formed by reactive ion etching,
A damage layer about 100mm deep is generated on the semiconductor surface. In order to remove this damaged layer, plasma etching is performed by microwave discharging a mixed gas containing NF3 gas and 02 gas. In order to remove these damaged layers, the partial pressure ratio of 02 to the mixed pressure of NF3 and 02 PO2
/ (PNF3 + PO2) - Plasma etching was performed under two conditions: 0.2 and 0.6. The relationship between the etching time and the etching depth of each diffusion layer is shown in the fourth table.
As shown in the figure. 41 to 43 are PO2/ (PNF3 + P
o2) -0, 8, 44 to 46 is 0.2, 41
．． 44 is the N'' diffusion region, 42.45 is the P4 diffusion region,
43 and 46 show the case of N-diffusion region.

Obviously, Po2/(PNP2 + PO2)−
When it is 0.6, there is less dependence on the type of diffusion layer,
It can also be seen that since the etching rate is low, the etching depth can be easily controlled.

Figure 5 shows damage layer removal after reactive ion etching of an npn transistor array pattern with very shallow junctions using PO2/(PNF3 + P
The probability of producing one transistor with respect to the etching depth of the N- diffusion region is shown when two types of conditions, O2)-0.2 and 0.6 are used.

In the case of PO2/ (PNF3 + Po2) - 0.2, the etching depth is about 200 and the transistor generation probability is at a very poor level of about 99.7%, whereas in the case of P02/ (PNF3 + PO2) - 5 if 0,8
In No. 1, even if the etching depth is about 200, the probability of transistor generation remains almost 100%. In other words, the yield of transistor arrays is improved.

Note that although a mixed gas of NF3 gas and 02 gas was used in this embodiment, other gas such as an inert gas may be further added to this mixed gas, for example.

[Effects of the Invention] By using the present manufacturing method, semiconductors having different impurities or concentrations can be etched simultaneously at approximately the same rate.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the ratio of the etching rate of each diffusion region to the partial pressure ratio of 02 gas according to the present invention, and FIG. 2 is a diagram showing the relationship of the etching rate of each diffusion region to the partial pressure ratio of 02 gas according to the present invention. 3 is a cross-sectional view of a Bi CklOS IC according to the present invention, FIG. 4 is a diagram showing the relationship between the etching depth of each diffusion layer and the etching time of the BI CMO9 IC according to the present invention, and FIG. Figure 6 shows the relationship between the etching depth of the N-diffused region and the probability of NPN transistor formation according to the present invention, and Figure 6 shows the relationship between the M alloy/N-81 shot junction characteristics and the amount of damaged layer removed. It is a diagram. 11...N'' diffusion layer for N'' diffusion layer, 12.P'' diffusion layer for N- diffusion layer.

Claims (1)

[Claims] Semiconductors with different impurities or concentrations are mixed with NF_3 gas and O
A method for manufacturing a semiconductor device, characterized in that in the step of simultaneously performing plasma etching and removal using a mixed gas containing _2 gas, the partial pressure ratio of O_2 gas to the mixed pressure of NF_3 gas and O_2 gas is set to 40% or more.