JPH0438787A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To sufficiently secure the accumulated charge quantity of a memory cell, while making the most of low power consumption, high S/N and high integration by varying the potential of a control line, and boosting the potential of a node in the memory cell from one terminal of a capacitor for constituting the memory cell. CONSTITUTION:As for a selected memory cell M11, since the potential of a control line SC1 is low potential OV, the potential of a node N in the selected memory cell M11 becomes OV or VH, and in a data line D1, a signal is read out in accordance with storage information '0', '1'. On the other hand, a word line W1 becomes high potential VH, the control line SC1 becomes low potential OV, and also, a transistor Qy1 is turned on. Subsequently, the potential of a data line is set to OV or VH in accordance with write information from the outside. By lowering the control line SC1 to lower voltage -Vth once, returning it to low potential OV, and setting the word line W1 to low potential OV, write can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory that simultaneously satisfies low power consumption and high reliability.

[Conventional technology]

To improve the conventional semiconductor memory consisting of one transistor and one capacitor memory cell,
There is an invention described in No. 635. The semiconductor memory of the above invention has a plurality of word lines W, , W, as shown in FIG. 1(a).
2 and a plurality of data lines D1. D2, and a plurality of control lines sc1.D2 provided corresponding to the data lines. sc2, and memory cells M11.sc2 arranged at the intersections of each word line, each control line, and each data line. M 2. M20. Consists of M2□,
By selecting the word line and control line, only the memory cells arranged at the intersections of these can be detected on the corresponding data lines. Next, the operation of the conventional semiconductor memory described above will be explained using FIG. Now, storage information 11Q u, 1 is stored in the capacitor of the memory cell.
11 When a low potential or high potential corresponding to II is stored, the node N (
The potential of M1□) lowers the potential of control line SC2 to a lower potential (Ov
) to a high potential (VH), the voltage increases by approximately VH due to capacitive coupling. Even if the potential of the word line W1 is set to a high potential (V o ) in this state, the data line is precharged to VH, so
As a result, the gate and source potentials of the transistor in the memory cell interlayer 2 become approximately equal, and as a result, this transistor is cut off, and the storage contents of the memory cell M□2 are not destroyed.

On the other hand, regarding the selected memory cell interconnect, since the potential of the control line SC is low, the potential of the node N (Mll) in the selected memory cell interconnect is not boosted.
Data line D1 carries storage information II OII, KL
The signal is read out according to I II. That is, when the stored information is LL Q 11 and 1", the potential of the data line D1 differs by Vs. This potential difference causes the information LE OTj
, 1111″, the transistor Qy
Turn on the signal, input it to the sense amplifier SA, and amplify it. Furthermore, the output is rewritten into the memory cell M1□. By doing this, as described in Japanese Patent Publication No. 55-7635, lower power consumption and higher S/N than before.
technology and high integration.

On the other hand, in a one-transistor, one-capacitor memory cell, due to leakage current from the memory cell, it is necessary to refresh the information in the memory cell before it is lost. The lower the refresh frequency, the easier it is to use as a memory, and the higher the reliability.

In order to reduce refresh frequency, it is effective to increase the amount of charge stored in memory cells. Increasing the amount of charge is also an effective means against destruction of information stored in memory cells due to radiation, that is, soft errors. However, the above-mentioned conventional technology did not take this point into consideration.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into account the reduction in the amount of charge stored in memory cells, which occurs with the increase in memory integration and miniaturization of memory cells, resulting in a reduction in memory information retention time and reliability. There was a problem.

That is, as shown in FIG. 2, in the above conventional technology, the high potential of the node in the memory cell is varied from the high potential of the word line (V o ) by Vth (Vth: the threshold value of the transistor of the memory cell) due to its operating principle. Voltage) It is possible to write only to low potentials.

In recent years, with the increasing integration of memory and the miniaturization of memory cells,
From the viewpoint of power consumption and element reliability, it is necessary to lower the operating voltage of memory. On the other hand, the threshold voltage of a transistor in a memory cell cannot be made unnecessarily low in order to ensure the information retention time of the memory. Therefore, in the above-mentioned conventional technology, the amount of charge stored in the memory cell decreases more and more, resulting in problems in terms of information retention time and reliability of the memory.

An object of the present invention is to obtain a semiconductor memory that takes advantage of low power consumption, high S/N, and high integration while ensuring a sufficient amount of accumulated charge in memory cells.

[Means to solve the problem]

The above purpose is to connect a plurality of word lines, a plurality of data lines arranged to intersect with the word lines, a signal detection means provided in common to the data lines, and a connection between the signal detection means and each of the data lines. a plurality of switching means for switching, and a plurality of memory cells provided at the intersections of the word line and the data line, wherein at least some of the memory cells are switched on and off by controlling the potential of the word line. and a capacitor for storing information, one end of which corresponds to a memory cell connected to the data line via a switching element, and a plurality of memory cell groups connected to each of the data lines. A plurality of control lines are provided, each of which is commonly connected to a capacitor in the memory cell group, and the corresponding word line and control line together read and write information stored in each memory cell. In the semiconductor memory that is performed when selected, the potential of the control line is a first potential and the memory cell is in a non-selected state, the potential of the control line is a second potential and the memory cell is selected, and the signal detection means After the data line reaches a predetermined high potential or low potential, the potential of the control line is lowered once from the second potential and raised again, and when the potential of one end of the capacitor is at a high potential, the voltage is increased, This is achieved by operating so that it does not change when the potential is low.

In other words, a pulse having three or more levels is applied to a control line connected to one end of a capacitor in a memory cell, and a memory cell is selected on the control line, and the information of the selected memory cell is set to a high potential. It is designed to have the function of boosting the voltage via the capacitor in the memory cell in the case of .

[Effect]

In order to select a memory cell by both the word line and the control line, a potential is applied to the control line coupled to the unselected memory cell so that the transistor in the unselected memory cell is turned off. On the other hand, a potential is applied to the control line coupled to the selected memory cell so that the information stored in the memory cell is read out to the corresponding data line. Furthermore, the potential of the control line is changed to boost the potential of a node within the memory cell from one end of a capacitor that constitutes the memory cell. By doing so, only the memory cells arranged at the intersections of the word lines and control lines can be detected on the corresponding data lines, and the amount of charge stored in the memory cells can be increased. Therefore, it is possible to improve information retention characteristics and α-ray soft error resistance characteristics.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1(a) is a memory array circuit diagram of a semiconductor memory in which memory cells are selected by word lines and control lines, FIG. 1(b) and FIG. 2 is an operation timing diagram of a conventional memory cell, FIGS. 3 and 4 are diagrams showing other operation timings according to the present invention, and FIG. 5(a) is a diagram of a semiconductor when differentially detecting signals. A memory array circuit diagram of the memory, (b) is its operation timing diagram, FIG. 6 is a configuration diagram of a memory using multiple memory arrays shown in FIG. 1 or FIG. 5 above, and FIG. 7 is an example of a sense amplifier. FIG. 8 is an operation timing diagram of the semiconductor memory of the present invention in page mode operation, FIG. 9 is a memory array circuit diagram of the semiconductor memory using other memory cells, and FIG. 10 is the operation of the semiconductor memory of the present invention. The timing diagram, FIG. 11, is a diagram showing an example of a pulse generation circuit that applies to the control line.

In FIG. 1, (a) shows the configuration of a memory array,
(b) shows the operation at the time of reading, and (c) shows the operation at the time of writing. A low potential (Ov) corresponding to the storage information "0'" II I 11 is applied to the capacitor of the memory cell.
) or a high potential (VH) is stored. For example, when reading out the memory cell M□1, the potential of the node N (Ml□) in the unselected memory cell M12 changes the potential of the control line SC2 from a low potential (Ov) to a high potential (Ov).
V o ), it increases to approximately V o or 2V++ due to capacitive coupling. In this state, even if the potential of the word line W is set to a high potential (V o ), the data line is precharged to VH, so the gate and source potentials of the transistor in the memory cell interconnection 2 become almost equal. , the transistor is cut off and the memory contents of the memory cell M1□ are not destroyed. On the other hand, for the selected memory cell M11, the control tIASC1
Since the potential of the selected memory cell M□ is low (○V),
The potential of the node N (M) in
1”, the signal is read out.

That is, when the stored information is hOII and 1'''', the potential of the data line D1 differs by VS. In order to discriminate between the information LL Q II and LL I 11 using this potential difference, the transistor Q y is turned on and the sense amplifier S
Input to A and amplify. As a result, the potential difference on the data line □ is amplified, and the potential of the data line D1 becomes Ov or VH. After that, the potential of the control line SC□ is lowered to a lower potential (
-vth). As a result, when the node of the selected memory cell has a high potential, the potential becomes VHV th, and when the node has a low potential, the potential becomes 0■ because the transistor of the memory cell is in an on state. After that, the control line S0
When the potential of node 1 is returned to a low potential (Ov), the potential of the node of the selected memory cell is boosted to VH via the capacitor because the transistor is almost in a cut-off state when the potential is high. On the other hand, when the potential is low, the transistor is in an on state, so that potential is held by sense-up, and the potential is unchanged from Ov.

Thereafter, the word line W1 is set to a low potential (0■), and reading of the selected memory cell is completed.

The write operation is performed as shown in FIG. 1(c).

The figure shows the case of writing to memory cell M11, where the word line W0 is set to high potential (VH) and the control line SC0 is set to high potential (VH).
is set to a low potential (Ov), and further the 1-transistor Qyl is turned on. Then, the potential of the data line is set to Ov or Vo according to externally written information. As a result, the node potential in the selected memory cell becomes Ov or VHVth. After that, the control line SC1 is once lowered to a lower potential (V
=h) and then returned to the low potential (Ov) again, the high potential is boosted to Vo as in the read operation. Thereafter, writing can be performed by setting the word line W1 to a low potential (Ov).

Note that, as shown in FIGS. 1(b) and 1(c), in the unselected memory cell M21 arranged at the intersection of the unselected word line W2 and the selected control line SC□, the control line S
When C is lowered to -Vih, the node potential drops to -V, but it does not become a complete on state and does not destroy the information stored in the memory cell. Further, at this time, the potential of the data line has been sufficiently amplified, and does not adversely affect the read operation of the selected memory cell.

As described above, according to this embodiment, the write voltage to the memory cell can be increased compared to the conventional method, and the amount of charge stored in the memory cell can be increased. Therefore, information retention characteristics and α-ray soft error resistance characteristics can be improved.

FIG. 3 shows an operation timing diagram of another embodiment of the present invention. In the operation example shown in FIG. 1(b), the potential of the control line SC is kept at a low potential in the standby state, and when a certain memory cell is selected, the control line connected to the unselected memory cell is set to a high potential. An example was shown in which memory cells are selected by However, when memory cells are arranged in a matrix, for example in an NXM matrix as shown in Figure 5 of Japanese Patent Publication No. 55-7635, and a sense amplifier SA is provided in common, the non-select control line Since the number of selection control lines is greater than the number of selection control lines, when selecting a certain memory cell, it is advantageous to change only the potential of the selection control line from the viewpoint of reducing power consumption and noise. Needless to say. In this case, as shown in Fig. 3, the potential of the control line is set to a high potential (V 11 ) in the standby state, and the potential of the selection control line, for example, SC U in the figure, is set to a low potential (0■). If the potential of the non-selection control line (5C2 in the figure) is maintained at a high potential (VH), only memory cell M□□ can be selected as in FIG.

FIG. 4 shows still another operation timing diagram, and shows an example of an operation that is effective when the threshold voltage of the transistor in the memory cell becomes large. That is, in the operation example shown in FIG. 1(b) or FIG. 3, when the threshold voltage vth becomes large and the relationship with the signal voltage Vs appearing on the data line becomes Vvh≧Vs, The signal voltage Vs that appears is Vs=(VH-Vth)Cs/(Co+Cs).

Here, CD is the parasitic capacitance of the data line, and C8 is the memory cell capacitance. In this case, Vs decreases as V th increases, and the information rr from the sense amplifier □
++, making it difficult to discriminate rr 1 n.

Therefore, in the embodiment shown in FIG. 4, the potential of the selection control line is lowered to below O■ when selecting a memory cell, and the signal voltage appearing on the data line is increased.

The figure shows a case where the potential of the selection control line is set to V1h/2. The non-selection control line S02 is at a high potential (VH
), and the potential of the node in the unselected memory cell (for example, M1□) is set to VH or 2Vo, so that even if the word line is selected, the transistor is in the cut-off state.

On the other hand, the selection control edge SC1 changes its potential to −V th /
Set it to 2. As a result, the potential of the node in the selected memory cell M1□ becomes Vt corresponding to the storage information "0" and "1".
h/2 or Vo Vth/2. Thereafter, when the potential of the selected word line is set to a high potential (V o ), information is read to the data line D1. At this time, the potential difference Vs' output to the data line is Vs'=(
VH-Vth/2)Cs/(Go+Cs). After amplifying this potential difference with a sense amplifier, once lowering the potential of the selection control line SC to -V th and then returning it to O■ as in FIG. 1(b), the potential of the node of the selected memory cell becomes When the potential is high, the transistor is almost in a cut-off state, so the voltage is boosted to VH via the capacitor. On the other hand, when the potential is low, the transistor is in an on state, so that potential is held by the sense amplifier, and the potential remains unchanged at 0. Thereafter, by returning the word line W1 to a low potential (OV) and returning the control line to the same state as the standby state, the read operation including the rewrite operation is completed. According to this embodiment, it is possible to increase the potential difference output to the data line, and information 1'0'', '
In the embodiment shown in FIG. 4, the potential of the selection control line is set to -Vih/2, but as is clear from the explanation of the operation, The above potential needs to be set between -Vih and Ov.In other words, when it is set below Vvh, the potential of the node in the unselected memory cell (M21 in FIG. 4) connected to the selection control line becomes This is because the voltage drops below V th during reading, and the transistor is turned on even though the word line is not selected.

Another embodiment of the present invention shown in FIG. 5 shows an example in which signals from memory cells are detected differentially.

FIG. 5(a) shows the configuration of the memory array, and FIG. 5(b) shows its operation. In the same figure, memory cell M112Mk
□, etc. are arranged in a matrix of kXl, and data lines (D□, Dl, etc.), word lines (W, Wb, etc.), and control lines (SC, SCI, etc.) are provided correspondingly. There is. Each data line is a data line selection signal line Y,
Through a transistor whose gate is coupled to Yl etc.
They are alternately connected to common data lines CD and CDB. This is to equalize the parasitic capacitances of the common data lines CD and CDB. DM, DMk, etc. are dummy cells that output reference signals and are connected to the dummy data line DD.

Dummy data line DD is dummy data line selection signal line YD1
．． It is connected to the common data lines CD and CDB via a 1- transistor having a gate 1- coupled to YD2. The potential of the node in the dummy cell is set to Vd-("VH/2) by the dummy cell reset signal φDHR. Also, the bias potential Vd is applied to one end of the capacitor.
p (eg OV) is given. PD is a circuit that precharges data lines and dummy data lines, and a high potential (Vuu
), the data line and dummy data line are precharged to vH. In such a configuration, the data line and dummy data line are precharged to vH as shown in FIG. 5(b). Also, the potential of the node in the dummy cell is set to Vd-(= V++/2
). After that, the selection control line (SC□ in the figure)
) is set to a low potential (0■), and the selected word line (W in the figure) is set to a high potential (Vu). As a result, the memory cell line and the dummy cell DM are selected, and the data line D
A storage signal is output to dummy data line DD, and a reference signal is output to dummy data line DD.

On the other hand, a high potential (VHH) is applied to the signal line corresponding to the selected memory cell (Y in the figure) among the data line selection signal lines, the data line D□ is connected to the common data line CD, and the storage signal is transmitted. Send to common data line CD. Also, apply a high potential (■ old 1) to YD2 of the dummy data line selection signal lines,
The dummy data line DD is connected to the common data line CDB, and a reference signal is sent to the common data line CDB. Thereafter, the sense amplifier differentially amplifies the storage signal and the reference signal.

After amplification, as shown in FIGS. 1 and 3, the potential of the selection control line SC1 is lowered to -Vth, and then returned to O■ to boost the potential of the node in the selected memory cell. Then, the selected word line and the selected control line are returned to the potential of the standby state in this order, and the read operation is completed. According to this embodiment, in order to differentially amplify signals from memory cells,
Reading can be performed more stably.

FIG. 6 is a diagram showing an embodiment in which a plurality of memory arrays shown in FIG. 1 or FIG. 5 are used to realize 20 memories on one chip. Here, a case is shown in which the total number of memory arrays SMA□□ to SMAmn is mXn. In each memory array, only the memory cells at the intersections of the control line SC and each selected word line W are selected, so that a maximum of rn x n memory cells can be selected at the same time. In order to read the information of a specific memory cell among these, the switch YSW controlled by the signal lines YS1 to YSn reads the information to the common input/output lines 10□ to IOm, and then 1 in
One can be selected and outputted to the outside as an output signal Do. Furthermore, when writing the input signal Dln to a specific memory cell, it can be written through the reverse path in the same manner. In the figure, XD is a word line W selection means, and 5YYD is a control line SC, data line selection signal line Y, and signal line YS selection means.

In the configuration shown in FIG. 6, a maximum of m x n memory cells can be selected simultaneously, but the number can be easily changed by changing the number of word lines and control lines that are simultaneously selected.

For example, by selecting one word line (for example, W□□) and n control lines (for example, Sc, , SCn□, etc.), n memory cells can be selected at the same time.

Further, by selecting one word line and one control line, only one memory cell can be selected. On the other hand, when considering the efficiency of refresh in the system,
In order to shorten the time during which the memory chip is refreshed, it is better to refresh one memory cell for each memory array, i.e., Xn memory cells, at the same time using sense amplifiers in each memory array.

If you select only one memory cell as above,
It is advantageous in terms of power consumption to operate only one of the Xn sense amplifiers in each memory array. In this case, a sense amplifier as shown in FIG. 7 can be used.

FIG. 7(a) shows an example of a differential amplifier composed only of NMO8, and the sense amplifier can be operated by simultaneously selecting two signal lines C3NX and C3NY.

(b) is an example of a differential amplifier configured with CMO8, with two signal line sets (C3Nx, cspx), (C3NY, C
3PY), the sense amplifier can be operated.

Furthermore, when a plurality of memory cells can be selected simultaneously as described above, it is also possible to operate in page mode or static column mode. In this case /R
While the AS signal is at a low potential, column-system address signals change many times, and writing and reading are performed for a plurality of memory cells selected by the word line and control line. Although rewriting operations can be performed in response to changes in column addresses, the timing design of control lines becomes complicated and the operation time becomes longer. Therefore, after all write and read operations to a plurality of memory cells are completed, a rewrite operation is performed.

The operation in this case will be explained with reference to FIG. 8, taking page mode as an example. First, the /RAS signal becomes a low potential, a row address signal is taken into the chip, and correspondingly, the word line W11, the control line 5cm1°5Cn1.・・・・・・、
and data line selection signal Y engineering.

Yn, +... are selected. As a result, information from multiple Megyu Risels is transmitted to each sense amplifier, and then amplified. Next, the /CAS signal becomes a low potential, the first column address is taken into the chip, and correspondingly one of the signal lines YS controlling the switch Ysw is selected (YS□ in the figure). As a result, information is read out to the common attendance line IO, and output to the outside. Furthermore, in the same way, the second column address is taken into the chip, and one of the signal lines YS that controls the switch YSw is selected (YSn in the figure), and the information of another memory cell is transferred to the chip. It is read out by the IO engineer,
Output to the outside. Repeat the above operation. Thereafter, in response to the /RAS signal changing to a high potential, the potential of the control line is lowered to -Vth, returned to Ov again, and then the word line is set to a low potential. As a result, rewriting to a plurality of memory cells is performed simultaneously. Write operations in page mode are performed in the same manner.

As described above, according to this embodiment, since rewriting is performed to a plurality of memory cells at once, the time required for the rewriting operation can be shortened. Therefore, memory usage efficiency can be increased. Further, since the timing for lowering the control line to Vth can be determined by the rising edge of the /RAS signal, timing design becomes easier.

Although the present invention has been described above using a memory cell consisting of one transistor and one capacitor, the present invention can also be applied to a semiconductor memory using other memory cells. For example, three transistors and one
It is also applicable to a memory cell consisting of two capacitors. In the figure, memory cell MC is transistor Q
The memory information is stored at the node N. DRl, DR2 and DW, , DW2 are read data lines and write data lines, respectively; WR, WR2 and wwl, w
w2 are a read word line and a write word line, respectively. SC□ and SC2 are control lines, and a memory cell is selected when both the word line and the control line are selected. In FIGS. 10(a) and (b), memory cell MC1□
An example of a read operation and a write operation is shown below. In a read operation, when the selected read word line WR□ is set to a high potential (VH) and the control line SC1 is set to a low potential (OV), if the potential of the node in the memory cell is high, it is pre-prepared to vH. A current flows from the charged read data line DR to the control line through the transistor Q21Q, and the potential of the read data line decreases. When the potential is low, the transistor Q3 is in a cutoff state, and the potential of the read data line does not change. That is, the stored memory information LL I II ,
A difference is generated in the potential of the read data line corresponding to LL Q 71, and the above potential difference causes information II II II, 1
1011 may be discriminated by a sense amplifier, and a high potential is applied to the data line selection signal line Y1 and inputted to the sense amplifier. On the other hand, the non-selected control line SC2 has a high potential (V n )
Therefore, even if the read word line WR1 is at a high potential (VH), no extra current flows through the unselected memory cell MC2.

Furthermore, since reading is performed non-destructively in this memory cell, there is no need to rewrite. Next, in the write operation, similarly to the read operation, the selected write word line WW is set to a high potential (V u ), the control line SC0 is set to a low potential (0), and VH or OV is set depending on the write information. Information is written into the selected memory cell from the write data line DW set to the potential. At this time, the potential of the node within the memory cell becomes VoVth or 0■.

In this state, the potential of the selection control line S01 is set to a lower potential (
-vth) and then back to OV. As mentioned above, the high potential is boosted to Vu, the low potential remains Ov, and then the selected write word line WW1 is set to a low potential (0
), the write operation is completed and the accumulated voltage can be set to vH.

On the other hand, since the non-selection control line S02 is at a high potential (V u ),
The potential of the node in the unselected memory cell coupled to this is boosted to VH or 2VH, and if the write data line DW is precharged to V)l in advance, the transistor will be in the cut-off state, and the write data line DW, Even if the word line WW1 is at a high potential, information in unselected memory cells will not be destroyed.

Note that the above memory cells also require refreshing,
The refresh operation can be performed by reading information from the memory cell and rewriting it in accordance with the read information.

As described above, according to this embodiment, even in a memory cell in which a read operation is performed nondestructively, the memory cell is arranged at the intersection of a selected word line and a control line during a read operation, write operation, or refresh operation. Only memory cells that have been selected can be selected. Therefore, the number of sense amplifiers and write circuits can be reduced, and no extra power is consumed. Furthermore, since the storage voltage can be increased, information retention characteristics and alpha ray soft error resistance characteristics can be improved.

FIG. 11 shows an example of a pulse generating circuit when a pulse having three levels is applied to the control line as shown in FIG. 4. 1 in the figure is a decoder, and here an example of a NAND circuit is shown. The operation of this circuit is explained in the 11th section.
This will be explained using the operation waveform shown in FIG. 3(c). Signal φPH is 0
When (2), the signal φP is VHl, and when all the address signals ai are Ov, the output of the decoder 1 is vH, the transistor T1 is turned off, T2 is turned on, and the transistor T
The gate potential of T3 and T4 becomes negative potential -V, and T
3 is turned on and VH is applied to the control line. Then the signal φP
When H is set to Vo and the signal φPOD is changed from VH to 0■ in the negative direction, the potential of the signal φP decreases due to coupling via the capacitor C2, and the potential of the signal φP decreases, causing the transistor T
7 is turned off, allowing its potential to become negative. The value can be set to -v1 by appropriately setting the capacitance value of the capacitor C2. This turns off transistor T2. After that, only the decoder to which the address signal ai is input and all of them are VH has an output O2, the transistor T is turned on, and therefore the transistor T3 is turned off and the transistor T4 is turned on.

If the signal φPD is set to VH in advance, the transistor T5 is turned on and 0■ is applied to the control line. Next, the signal φPD is set to -■1 in the same way as the signal φP, and the transistor T5 is turned off, and then the signal φPDD is set to V
When the voltage is changed from o to Ov in a negative direction, the potential of the control line can be made negative due to coupling via the capacitor C. This value can also be set to -Vch by appropriately setting the capacitance value of the capacitor C1. If the signal φPOD is then returned from 0■ to VH, the potential of the control line can be returned to Ov again by coupling via the capacitor C1. Then, when all the address signals ai are set to Ov and the signal φPM is set to Ov, the signal φP becomes V
o, returning to the initial state and applying Vu to the control line. Note that the potential -V□ needs to be equal to or lower than V th here.

This potential can be generated using a circuit similar to the substrate voltage generation circuit widely used in semiconductor memories.

〔Effect of the invention〕

As described above, the semiconductor memory according to the present invention includes a plurality of word lines, a plurality of data lines arranged to intersect with the word lines,
A signal detection means provided in common to the data line, a plurality of switching means for connecting the signal detection means and the data line, respectively, and a plurality of memories provided at the intersections of the word line and the data line, respectively. At least a portion of the memory cell includes a switching element whose on/off is controlled by the potential of the word line, and a capacitor for storing information, and one end of the capacitor is connected to the data via the switching element. A plurality of control lines are provided corresponding to memory cells connected to the line and a plurality of memory cell groups connected to each of the data lines, and each of the control lines is connected in common to a capacitor in the memory cell group. In a semiconductor memory in which reading and writing of stored information in each memory cell is performed when both a corresponding word line and a control line are selected, the potential of the control line is at a first potential and the memory cell is is in a non-selected state, the potential of the control line is at the second potential = 31st, the memory cell is selected, and after the data line has become a predetermined high potential by the signal detection means, the potential of the control line is set to the second potential. Lower the potential once and then raise it again.
By operating the capacitor so that the potential at one end of the capacitor is boosted when the potential is high and does not change when the potential is low, it is possible to increase the amount of accumulated charge in the semiconductor memory, which improves information retention characteristics and α resistance. It is possible to improve line soft error characteristics.

[Brief explanation of the drawing]

FIG. 1(a) is a memory array circuit diagram of a semiconductor memory in which memory cells are selected by a word line and a control line, FIG. 1(b) is a diagram showing an example of the read operation of the memory array, and FIG. 1(C)
2 is an operation timing diagram of a conventional memory cell, FIG. 3 is another operation timing diagram according to the present invention, and FIG. 4 is still another operation timing diagram according to the present invention. FIG. 5(a) is a memory array circuit diagram of a semiconductor memory that detects signals in differential mode, FIG. 5(b) is its operation timing diagram, and FIG. 6 is the same as that shown in FIG.
A configuration diagram of a memory using multiple memory arrays shown in the figure,
7(a) and 7(b) are diagrams each showing an example of a sense amplifier, FIG. 8 is an operation timing diagram of the semiconductor memory of the present invention in page mode operation, and FIG. 9 is a diagram showing an example of the semiconductor memory using other memory cells. Memory array circuit diagram, 10th
FIGS. 11(a) and 11(b) are diagrams showing the operation timing of the semiconductor memory according to the present invention, FIGS. 11(a) and 11(b) are diagrams showing an example of a pulse generation circuit applied to the control line, and FIG. 11(c) is an operation timing diagram. Cs...Capacitor Dl, D,...Data line M, M engineering 1. Mb2...Memory cell Q1...Switching element Qy, Qyz...Switch transistor SA...
・Sense up SC1, SC2, SC, □~SC,1...Control line W1
~Wk, Wwork, ~W1, . . . word lines Y,, Y2. Y engineering□~Yn1...Data line selection signal line (,5-----
--------i-Manozumi 7ri DI, 02------
---D2. Wholesale foot M+, Mo, Mk2-----Mechinasze] and Qm-------------λ1 Tsuchire 2゛° element QYI, QY2--------Trare register λ for switcher
SA ---------------Se〉Sarea SCI
, SC2,5CII ~5Cn2--- f? J, 惺Wf ~Wk, Wo ~Wm+----Word Yl
, Y2. Yll ~Yn2---------Te'fuR
Selection button tV, W. Figure 1 (a) Figure 1 (b) VH 2 Figure 3 Figure AS YSn ℃-y'℃-J' VH -1 person 211111O# (a) (b)

Claims (1)

[Claims] 1. A plurality of word lines, a plurality of data lines arranged to cross these, a signal detection means provided in common to the plurality of data lines, and the signal detection means and the data line. a plurality of switching means for connecting to each of the word lines, and a plurality of memory cells provided at the intersections of the word line and the data line, at least some of the memory cells being turned on and off by the potential of the word line. A memory cell consisting of a switching element whose off-state is controlled and a capacitor for storing information, one end of the capacitor being connected to a data line via the switching element, and a plurality of memory cell groups connected to each of the data lines. A plurality of control lines are provided corresponding to the memory cells, each having a plurality of control lines commonly connected to the capacitors in the memory cell group, and reading and writing of information stored in each memory cell is carried out between the corresponding word line and control line. In a semiconductor memory that is performed when both are selected, the potential of the control line is a first potential and the memory cell is in a non-selected state, the potential of the control line is a second potential and the memory cell is selected, and the potential of the control line is a first potential and the memory cell is selected. After the data line is set to a predetermined high potential or low potential by the signal detection means, the potential of the control line is lowered once from a second potential and then raised again, so that the potential of one end of the capacitor becomes a high potential. A semiconductor memory that operates by increasing the voltage when the voltage is high and not changing when the voltage is low. 2. In the semiconductor memory according to claim 1, a plurality of memory cells are grouped and arranged in a two-dimensional matrix to form respective memory arrays, and the signal detection means detects a plurality of data in each memory array. A common line is provided for each memory array, and the plurality of switching means are provided for each memory array so as to connect the signal detection means and each of the plurality of data lines in the memory array. Features of semiconductor memory. 3. The semiconductor memory according to claim 2, wherein corresponding word lines of memory arrays in different rows are connected to each other. 4. A semiconductor memory according to claim 2, wherein corresponding control lines of memory arrays in different columns are connected to each other. 5. The semiconductor memory according to claim 2, wherein the number of memory cells selected during a read or write operation is different from that during a refresh operation. 6. In the semiconductor memory according to claim 2, an address signal for selecting a plurality of memory cells is taken into the chip in a time-sharing manner by a row address strobe signal and a column address strobe signal, and the row address strobe signal In a semiconductor memory in which a word line and a control line are selected by an address signal taken in by a signal, the operation of once lowering the potential of the control line from a second potential is performed by changing the row address strobe signal from a low potential to a high potential. Semiconductor memory that is characterized by being processed after a change. 7. A semiconductor memory according to claims 1 to 6, characterized in that each memory cell comprises one transistor and one capacitor. 8. A semiconductor memory according to claims 1 to 6, characterized in that a memory cell comprises three transistors and one capacitor. 9. A semiconductor memory according to claims 1 to 6, characterized in that a dummy cell is provided and the signal detection means is a means for detecting a differential signal between the dummy cell and the memory cell.