JPH0438170A - Switching power source circuit - Google Patents

Abstract

PURPOSE:To protect a switching power source circuit and load circuit by stopping the operation of the switching power source circuit when the value of a current signal continuously exceeds a prescribed reference voltage by at least two times. CONSTITUTION:The inverted output signal FFQ of a flip flop circuit 19 opens or closes a switch 34 and connects a constant-current source 35 with an external capacitor 37 and external resistor 38. The capacitor 37 is set so that it can exceed the reference voltage VL of a comparator 36 when a comparator 20 is continuously inverted five times. When the value of the voltage signal V1S of a transistor 25 exceeds a reference voltage VS the output signal FFQ of the flip flop circuit 19 becomes a high level through the comparator 20 and a charging current is supplied to the external capacitor 37. When the charging is continuously made to the capacitor 37 more than five times, a switching power source circuit stops its operation and the transistor 25 is turned off.

Description

[Detailed Description of the Invention] [Industrial Application Field: The present invention is applicable to, for example, PWM (pulse-widt
The present invention relates to a switching power supply circuit suitable for application to an IC for controlling a switching regulator (modulation) type.

[Summary of the Invention] The present invention provides, for example, PWM (pulse-widt
In a switching power supply circuit suitable for application to a switching regulator control IC of the h modulation type, a signal representing the magnitude of the current flowing through the main switching element is supplied, and the value of this signal is equal to or higher than a reference voltage. It has a comparison means whose output is inverted when the value of When the value exceeds the reference voltage of the comparison means, the operation is stopped in relation to the charging and discharging time of the capacitor, thereby protecting the switching power supply circuit and driving the switching power supply circuit in connection with the switching power supply circuit. This is to protect the load circuit that is exposed to the load.

[Background Art] Recently, relatively high efficiency switching power supply circuits have been frequently used due to the demand for smaller and lighter electronic devices. In this case, the switching power supply circuit is equipped with an overcurrent protection circuit from the viewpoint of safety, etc., and the circuit type is, for example,
A current limiter method is used to limit the peak current for each main current waveform.

The configuration of a conventional switching power supply circuit equipped with an overcurrent protection circuit employing this current limiter method is shown in FIG. 4, and the waveforms associated with its operation are shown in FIG. In Figure 4, (1) is the IC power supply/0N10FF circuit, and the terminal (2
) to the unsteady voltage V. C to output the reference voltage V It E p to the terminal (3) and internal circuit components, and if necessary, change the voltage VREF to ○N1
A circuit for turning the signal OFF is provided. (4) is an error amplifier which supplies the voltage signal V- and voltage signal V+ from terminals (5) and (6) and sends the error voltage to one of the feedback terminal (7) and the PWM control comparator (8). Output to input terminal. The other input terminal of this comparator (8) is supplied with the triangular wave signal 03C3 from the oscillation circuit (9), and the output signal CM of the comparator (8)
Pl is supplied to the first input terminal of the AND circuit (10).

The oscillation circuit (9) has an external capacitor (13) for setting the time constant to determine the oscillation frequency of the triangular wave signal 05C3.
), external resistors (14) and (15) are terminals (16),
They are connected via (17) and (18). and,
Square wave signal 03C which is the output signal of this oscillation circuit (9)
1 and reset signal 03C2 are each connected to an AND circuit (10
) and the reset terminal R of the flip-flop circuit (19). A set signal FFS is supplied to the set terminal S of this flip-flop circuit (19) from a comparator (20) for overcurrent protection via an inverter (21), and its output signal FFQ is supplied to the set terminal S of the AND circuit (10). 3 input terminal.

The output signal OUT of this AND circuit (10), that is,
The PWM signal is transmitted via a terminal (11) to a power MOS FE whose drain is connected to one end of a switching power supply transformer (22) to control the on/off of the main current.
T: (hereinafter referred to as transistor) Supplied to the gate of (25>).

A voltage source (51) is connected to the reference input terminal of the comparator (20).
) is supplied with a reference voltage V, and a voltage signal V15 proportional to the magnitude of the main current ■1 is supplied to the comparison input terminal from the terminal (
23). In this case, the voltage signal V
IS appears at the other end of a resistor (24) whose one end is grounded, and the source of the transistor (25) is connected to this resistor (24), so that the main current 1. is supplied.

For example, a DC voltage obtained by rectifying an AC power source (not shown) is supplied to the primary terminal (26) side of the transformer (22), and a diode (27) is supplied to the secondary side of the transformer (22). ) and a capacitor (28) are connected, and a load resistor (31) is connected to the output terminal of this rectifier circuit, in other words, the terminals (29) and (30) connected to the capacitor (28). has been done.

Next, the operation of the above conventional switching power supply circuit will be explained. As understood from FIG. 5, the time to z
j. In the dark, the value of the load resistor (31) is held constant, so the error voltage signal CMP 1 and the pulse width of the output signal OUT are held constant, and the main current 11
The amplitude of the waveform is also held constant.

Next, between time t1 and t2, the load resistor (
31) is gradually decreasing, the pulse widths of the error voltage signal CMP1 and the output signal OUT gradually increase, and the amplitude of the waveform of the main current 11 also gradually increases. In this case, before time t2, the voltage signal V1.corresponds to the amplitude of the waveform of the main current 11. The amplitude of is the reference voltage V of the comparator (20).

Since it is smaller than , the comparator (20) does not invert, and therefore, no change occurs in the set signal FFS.

In this way, at time t3, the load resistor (3
Transistor (25) due to the decrease in resistance value of 1)
When the value of the voltage signal V15 applied to the main current flowing through the circuit exceeds the reference voltage , the set signal FFS becomes low level, so the flip-flop circuit (19) is set, and this flip-flop circuit (19) is set. (19) Output signal F
When FQ becomes low level, transistor (25)
is turned off.

Therefore, the value of the voltage signal V,5 is again the reference voltage voltage V
, the set signal FFS becomes high level, the flip-flop circuit (19) is reset by the reset signal 03C2 at time t4, and the level of the output signal FFQ is made high level, so that the transistor (25 ), the main current will flow again. In this case, in the circuit shown in FIG. 4, the output current ILO flowing through the load resistor (31) and the output voltage V appearing between the terminals of the load resistor (31). As shown in FIG. 6, the relationship between the reference voltage V and the current value IR decreases from the current value IR applied to the reference voltage V, so that the output power can be suppressed to a predetermined value or less.

In this way, even in the above-mentioned conventional switching power supply circuit, since the peak current of each waveform of the main current 11 is limited in relation to the reference voltage V after time t2, the switching transformer (22) It is possible to relatively prevent a decrease in the reliability of power supply circuit components due to heat generation such as the transistor (25), and to achieve an overcurrent protection circuit function.

However, in the above conventional switching power supply circuit,
In actual use, it is not uncommon to set the current value IR applied to the reference voltage VS to a relatively large value. i
ng), and the switching power supply itself has a heat accumulation effect, which may cause deterioration of power supply circuit components and deformation of molded components such as the power supply case.To prevent this, temperature fuses, etc. The problem was that it had to be adopted.

The present invention has been made in view of these points, and it is an object of the present invention to provide an excellent switching power supply circuit that can protect the switching power supply circuit and the load circuit driven in connection with the switching power supply circuit. purpose.

[Means for Solving the Problems] The switching power supply circuit of the present invention, for example, as shown in FIG.
A comparison means (20) is supplied with a signal V+S representing the magnitude of the signal V+S and whose output is inverted when the value of the signal V+S reaches a value equal to or higher than the reference voltage 73;
A capacitor (
37), and when the value of the signal V I S reaches a value equal to or higher than the reference voltage V8 of the comparison means (20) at least twice in a row within a predetermined period of time, the capacitor (37)
), the operation of the switching power supply circuit is stopped in relation to the charging/discharging time of the switching power supply circuit.

[Operations] Therefore, according to the present invention, the value of the signal VIS is determined by the comparison means (20) at least twice consecutively within a predetermined period of time.
When the value reaches the reference voltage 73 or higher, the operation can be stopped in relation to the charging/discharging time of the capacitor (37).

1 Embodiment] An embodiment of the switching power supply circuit of the present invention will be described below with reference to FIG.

In FIG. 1, parts corresponding to those in FIG. 4 are designated by the same reference numerals. In Figure 1, (33) is the IC power supply
Unstable voltage V from terminal (2) in 0N10FF circuit. 0
is supplied to output the reference voltage VIEF to the terminal (3) and internal circuit components, and the voltage V RE
A circuit for 0N10FF is provided. In this case, a latch circuit is adopted as the circuit for 0N10FF, and as described later, this latch circuit changes the state when the 0N10FF circuit is turned off by the output signal CMP3. It is configured to maintain an unstable voltage V. The latch state is set to be released when 0 becomes a voltage value below a predetermined voltage. Note that the latch circuit may be omitted if necessary.

(4) is an error amplifier which supplies the voltage signal V- and voltage signal V+ from terminals (5) and (6) and sends the error voltage to the feedback terminal (7) and the PWM control comparator (
8) is output to one of the input terminals. This comparator (
The other input terminal of 8) is supplied with the triangular wave signal 03C3 from the oscillation circuit (9), and its output terminal is connected to the AND circuit (1
0).

The oscillation circuit (9) has an external capacitor (
13), the external resistors (14) and (15) are connected to the terminals (16
), (17), and (18). Then, the square wave signal O which is the output signal of this oscillation circuit (9)
3CI and reset signal 03C2 are respectively connected to the second input terminal of the AND circuit (lO) and the flip-flop circuit (
19) is supplied to the reset terminal R of 19). The main current 11 is connected to the set terminal S of this flip-flop circuit (19).
A set signal FFS is supplied via an inverter (21) from a comparator (20) (comparing means) that monitors the peak current for each waveform and protects against overcurrent, and its output signal FFQ is supplied to the AND circuit (10). ) is supplied to the third input terminal of the terminal.

Furthermore, the inverted output signal FFQ of the flip-flop circuit (19) is supplied to the opening/closing control terminal of the switch (34) as an opening/closing signal for the switch (34).

One terminal of this switch (34) receives a charging current I in relation to the voltage v, F. The other terminal is connected to a constant current source (35) that supplies the reference voltage VL.
52) is connected to the non-inverting input terminal of a new comparator (36) which is connected to the inverting input terminal, and a capacitor (37) and a resistor (38) are externally connected for externally setting the charge/discharge time. is connected to via a terminal (39).

In this case, the charging/discharging time required for the external capacitor (37), etc. is determined by the comparator (20) that monitors the peak current for each waveform of the main current (1) to protect against overcurrent. ) is inverted five times in succession, the terminal voltage vc of the capacitor (37) is set to exceed the reference voltage V of the new comparator (36). Note that when the comparator (20) is inverted not only 5 times but 4 times, 10 times, 100 times, etc., at least twice in a row within a predetermined time (time t13 to time tla in FIG. 2), In other words, when the value of the voltage signal VIS representing the magnitude of the main current 11 exceeds the reference voltage V at least twice in a row within a predetermined period of time, a new comparator (
36) so that it exceeds the reference voltage VL. Then, the output signal CMP3 of this new comparator (36) is applied to the IC power supply/ON/○FF circuit (33).
It is configured to be supplied to the latch circuit that constitutes the circuit.

Furthermore, the output signal OL'T of the AND circuit (10), that is, the -PWM signal is connected to a power MOSFET (hereinafter referred to as "power MOSFET") as a main switching element whose drain is connected to one end of the transformer (22) and controls the main current 11 on and off. ,
A terminal (11) is connected to the gate of (25)
).

The input terminal V- of the comparator (20) has a voltage of 11
A reference voltage V is supplied from t(51), and the input terminal V-
A voltage signal VIS proportional to the magnitude of the main current (1) is supplied through a terminal (23). In this case, the voltage signal VIS is connected to a resistor (24) whose one end is grounded.
The source of the transistor (25) is connected to the resistor (24), and the main current 11 is connected to the resistor (24).
is supplied.

The primary side terminal (26) of the switching transformer (22)
) side, for example, a DC voltage obtained by rectifying an AC power source (not shown) is supplied, and this switching transformer (22
) has a diode (27) and a capacitor (2
A load resistor (31) is connected to the output terminals (29) and (30) of this rectifier circuit.

Next, the operation of one embodiment of the switching power supply circuit of the present invention will be explained with reference to the waveforms shown in FIG. In FIG. 2, between time tto and t12, time t of the circuit shown in FIG. The operation is similar to that during -t2. That is, when the value of the load resistor (31) is held constant, the error voltage signal CMP 1
, the pulse width of the output signal OUT is kept at a constant value, the amplitude of the waveform of the main current 11 is also kept at a constant value, and when the value of the load resistor (31) gradually decreases, the error voltage The pulse width of the signal CMPI and the output signal OUT gradually increases, and the amplitude of the waveform of the main current 11 also gradually increases. In this case, before time t f 2, the amplitude of the voltage signal VIH corresponding to the amplitude of the waveform of the main current ■1 is smaller than the reference voltage Vs of the comparator (20), so the comparator (20) is not inverted. , therefore, no change occurs in the set signal FFS. In this state, the switching power supply circuit can stably and continuously operate.

Next, at time t13, when the value of the voltage signal VIS applied to the value of the main current ■1 flowing through the transistor (25) exceeds the reference voltage V due to a decrease in the resistance value of the load resistor (31), Since the set signal FFS becomes low level, the flip-flop circuit (19) is set,
Since the output signal FFQ of this flip-flop circuit (19) becomes low level, the transistor (25) turns off. Therefore, the value of the voltage signal VIS becomes smaller than the reference voltage V again, and the set The signal FFS becomes high level, and the reset signal osc2 is activated at time t14.
The flip-flop circuit (19) is reset by this, and the level of the output signal FFQ is made high, so that the transistor (25) receives the main current 1. will flow.

On the other hand, at the time tl1, the output signal FFQ of the flip-flop circuit (19) becomes high level, the switch (34) is closed, and the constant current source 35 is closed.
) from charging current I. is supplied to the capacitors (3, 7). In this case, since the output signal FFQ of the flip-flop circuit (19) is at a high level between time tts and time t14 in FIG. 2, the charging current I0 is continuously supplied to the capacitor (37), and its terminal voltage ■c will increase in pest control. Then, the next time t14-t
15, the output signal FFQ of the flip-flop circuit (19) is at a low level, so the switch (34) is open and the capacitor (3
7) is discharged through the resistor (38), thereby increasing the terminal voltage V of the capacitor (37). is reduced to pest control. In this case, the capacitor (37)
The discharge time constant determined from the resistor (38) and the resistor (38) is at time t1.
The setting is made so that the discharge action does not end during the time period of 4 to tls.

In addition, the hatched part in Figure 2 is the capacitor (3
7) shows the charging period.

In this way, as shown in the waveform of the terminal voltage VC of the capacitor (37) between time t13 and tri (see FIG. 2), the value of the voltage signal VIS applied to the value of the main current 11 changes to the reference voltage V. When the charging current I exceeds 5 times in a row, the charging current I is flowing from the constant current source 35) to the capacitor (37) from that time t17. When the terminal voltage VC exceeds the reference voltage V of the new comparator (36), the comparator (36) inverts;
By setting the output signal CMP3 to the 71 level, the above IC power supply/○N10FF circuit (33)
7 state, the voltage ViEPO value decreases, the switching power supply circuit stops its operation, and the transistor (25)
is turned off.

That is, when the comparator 20 is inverted five times within the time period tlff to tla, the switching power supply circuit stops its state. Note that, as described above, under the action of the latch circuit provided in the IC1t source/0N10FF circuit (33), this state will occur unless the unstable voltage VCC becomes a voltage value below a predetermined voltage, for example, on the negative side. It is retained until the power is turned off.

In this way, according to the above embodiment, the value of the voltage signal V+S applied to the peak current signal of the main current 11 flowing through the transistor (25), which is the main switching element, is changed to the value of the voltage signal V+S applied to the peak current signal of the comparator (20) five times in a row within a predetermined time. Since the operation of the switching power supply circuit is stopped when the value reaches the reference voltage V3 or higher, continuous operation in the current limited operation state is continued for a certain period of time (time between time t13 and t's). This allows for sufficient derating of circuit components such as the transistor (25) that are in a state of intermittent but continuous energization, and also prevents deterioration of power supply circuit components due to the heat storage effect of the switching power supply itself, and prevents the power supply case from deteriorating. This has the effect that deformation of the molded parts does not occur. Also, temperature fuses and the like become unnecessary. Therefore, there is an advantage that the switching power supply circuit and the load circuit driven in connection with the switching power supply circuit can be protected.

In the end, an excellent switching power supply circuit can be obtained that can relatively prevent a decrease in reliability of power supply circuit components caused by heat generation such as the transformer (22) and transistor (25), and can achieve overcurrent protection circuit function. It will be done.

FIG. 3 shows the configuration of another embodiment of the switching power supply circuit of the present invention. In this circuit, a new comparator (40) is further provided so as to input the terminal voltage vc of the capacitor (37), and the voltage of the voltage source (53) that supplies the reference voltage VLS is adjusted, for example, at the time shown in FIG. Capacitor V at point tls.

A voltage between the terminal voltage V Cl and 0 volts is selected, and the latch circuit provided in the IC'IE source/ON10 FF circuit (33) releases its latched state with this output signal CMP 4. By configuring (that I
The code for the C power supply/0N10FF circuit is (54)),
The terminal voltage V of the capacitor (37) after the time point Tie.

It is also possible to operate the switching power supply circuit again when the voltage drops below the reference voltage V.

Note that the examples shown in Figures 1 and 3 above both employ a current limiter method that limits the peak current for each waveform of the main current waveform. Omit the relevant parts,
The switching power supply circuit may be configured only with a time-limited protection function related to charging and discharging the capacitor (37).

Note that the present invention is not limited to the above-described embodiments, and it goes without saying that various configurations may be adopted without departing from the gist of the present invention.

[Effects of the Invention] As described above, according to the present invention, the value of the current signal representing the magnitude of the current flowing through the main switching element becomes equal to or higher than the predetermined reference voltage at least twice in a row within a predetermined time. When this happens, the operation of the switching power supply circuit is stopped, which has the effect of protecting the switching power supply circuit and the load circuits that are driven in connection with the switching power supply circuit. play.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of one embodiment of the switching power supply circuit according to the present invention, FIG. 2 is a waveform diagram explaining its operation, and FIG. 3 is the configuration of another embodiment of the switching power supply circuit according to the present invention. Figure 4 is a circuit diagram of a conventional switching power supply circuit, '! FIG. J5 is a waveform diagram explaining the operation, and a current-voltage characteristic diagram of the circuit shown in FIG. 6 or 4. (20) is a comparator, (37) is a capacitor, (4
0) is a comparator.

Claims (1)

[Scope of Claims] Comparison means that is supplied with a signal representing the magnitude of the current flowing through the main switching element and whose output is inverted when the value of this signal becomes equal to or higher than a reference voltage; and a capacitor whose charging and discharging are controlled according to the output state of the capacitor, and when the value of the signal becomes equal to or higher than the reference voltage of the comparison means at least twice in a row within a predetermined period of time, the capacitor A switching power supply circuit characterized in that the operation is stopped in relation to charging and discharging time.