JPH0438134B2 - - Google Patents
Info
- Publication number
- JPH0438134B2 JPH0438134B2 JP22460784A JP22460784A JPH0438134B2 JP H0438134 B2 JPH0438134 B2 JP H0438134B2 JP 22460784 A JP22460784 A JP 22460784A JP 22460784 A JP22460784 A JP 22460784A JP H0438134 B2 JPH0438134 B2 JP H0438134B2
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- diode
- transistor
- wiring
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0783—Lateral bipolar transistors in combination with diodes, or capacitors, or resistors
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り特にベース、エミツ
タ間にダイオードを接続した回路の構成に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a circuit configuration in which a diode is connected between a base and an emitter.
同一基板上にトランジスタとダイオードを並列
接続した場合、その構造からトランジスタもしく
はダイオードの、もしくは双方の分離のための
PN接合面のうち基板上に露出した部分の一部は
表面配線で覆うことができない。
When a transistor and a diode are connected in parallel on the same substrate, due to the structure, it is necessary to separate the transistor or diode, or both.
A portion of the PN junction surface exposed on the substrate cannot be covered with surface wiring.
従来、この表面配線で覆われない接合面の基板
上露出部に特に配慮がなされなかつたため可動性
イオン等によりコレクタ電極から発生するチヤネ
ルを防止するエミツター電位が加わらず、漏れ電
流が流れる不具合があつた。
In the past, no particular consideration was given to the exposed portion of the board on the bonding surface that was not covered by the surface wiring, which resulted in the problem that an emitter potential was not applied to prevent channels generated from the collector electrode due to mobile ions, etc., and leakage current flowed. Ta.
本発明の目的はかかる漏れ電流の発生のない良
好な半導体装置を提供することにある。 An object of the present invention is to provide a good semiconductor device that does not generate such leakage current.
本発明によれば、エミツタ電極の配線を環状に
設けることによりコレクタから表面に露出した
PN接合部に至るまでにどの方向からもエミツタ
配線を横切らずに通過できないためチヤネルの発
生が無く漏れ電流が流れることを防止する半導体
装置を得ることができる。
According to the present invention, by providing the wiring of the emitter electrode in an annular manner, the wiring exposed from the collector to the surface is
Since it is impossible to pass through the emitter wiring from any direction without crossing the emitter wiring until reaching the PN junction, it is possible to obtain a semiconductor device in which no channel is generated and leakage current is prevented from flowing.
次に図面により本発明をより詳細に説明する。 Next, the present invention will be explained in more detail with reference to the drawings.
第２図はトランジスタとダイオードの接続回路
であり、PNPトランジスタ１のエミツタにダイ
オード２のカソードを接続し、ベースにアノード
を接続している。 Figure 2 shows a transistor-diode connection circuit, in which the emitter of PNP transistor 1 is connected to the cathode of diode 2, and the base is connected to the anode.
第３図は従来の第２図の回路の実施例である。
Ｐ型半導体３とＮ型半導体基板４とＰ型半導体５
でPNP型トランジスタが構成され、Ｐ型半導体
６とＮ型半導体７でダイオードが構成されてい
る。さらに表面全面に絶縁膜を設け、コンダクト
部分８からコレクタ電極９を取り出し、コンダク
ト部分１０からエミツタ電極１１を取り出し、コ
ンタクト部分１２からエミツタ電極１１へダイオ
ードのカソードを短絡し、コンタクト部分１３か
らダイオードのアノード電極１４を取り出しコン
タクト部分１５から取り出したベース電極と短絡
させる。ここで１７は半導体基板４より濃度の高
いＮ型半導体である。 FIG. 3 is an embodiment of the conventional circuit shown in FIG. 2.
P-type semiconductor 3, N-type semiconductor substrate 4, and P-type semiconductor 5
A PNP type transistor is constituted by this, and a diode is constituted by a P type semiconductor 6 and an N type semiconductor 7. Further, an insulating film is provided on the entire surface, the collector electrode 9 is taken out from the conductor part 8, the emitter electrode 11 is taken out from the conductor part 10, the cathode of the diode is short-circuited from the contact part 12 to the emitter electrode 11, and the cathode of the diode is short-circuited from the contact part 13 to the emitter electrode 11. The anode electrode 14 is taken out and short-circuited with the base electrode taken out from the contact portion 15. Here, 17 is an N-type semiconductor having a higher concentration than the semiconductor substrate 4.
第２図の回路を同一基板上に構成する場合、表
面露出部１６の様にPN接合の金属配線（第３図
の斜線部）で覆われない部分が必ず存在し、コレ
クタから発生したチヤネルが表面露出部１６の
PN接合部を通りＰ型半導体６と短絡し、回路機
能を果たさなくなることがあつた。 When the circuit shown in Fig. 2 is constructed on the same substrate, there will always be a part like the surface exposed part 16 that is not covered with the PN junction metal wiring (the shaded part in Fig. 3), and the channel generated from the collector will be of the surface exposed portion 16
There were cases where it passed through the PN junction and was short-circuited with the P-type semiconductor 6, causing the circuit to no longer function.
第１図は本発明の一実施例であり、第３図の従
来例との相異点はエミツタ電極１１を環状配線１
８の様に環状に配置し、コレクタＰ型半導体３か
ら露出部１６のPN接合へ伸びるチヤネルをこの
環状配線１８で阻止しようとするものである。 FIG. 1 shows an embodiment of the present invention, and the difference from the conventional example shown in FIG. 3 is that the emitter electrode 11 is
8, the annular wiring 18 is used to block a channel extending from the collector P-type semiconductor 3 to the PN junction in the exposed portion 16.
この様に表面に発生し易いチヤネルを環状のエ
ミツタ配線により阻止でき良好な回路機能を持つ
半導体装置を得ることができる。
In this way, channels that are likely to occur on the surface can be prevented by the annular emitter wiring, and a semiconductor device with good circuit function can be obtained.
又、上記の例ではPNPトランジスタの例をあ
げたが、各半導体部が逆の導電型を有する場合に
も適用されることは言を待たない。 Further, although the above example uses a PNP transistor, it goes without saying that the present invention is also applied to cases where each semiconductor portion has an opposite conductivity type.
第１図は本発明の一実施例による平面図であ
り、第２図は本発明の適用される回路例であり、
第３図は従来の半導体装置の一例を示す平面図で
ある。
１……PNPトランジスタ、２……ダイオード、
３，５，６……Ｐ型半導体、４……Ｎ型半導体基
板、７，１７……Ｎ型半導体、８，１０，１２，
１３，１５……コンタクト部、９……コレクタ電
極、１１……エミツタ電極、１４……ベース、ア
ノード短絡電極、１６……PN接合表面露出部。
FIG. 1 is a plan view according to an embodiment of the present invention, and FIG. 2 is an example of a circuit to which the present invention is applied.
FIG. 3 is a plan view showing an example of a conventional semiconductor device. 1...PNP transistor, 2...diode,
3,5,6...P-type semiconductor, 4...N-type semiconductor substrate, 7,17...N-type semiconductor, 8,10,12,
13, 15...Contact part, 9...Collector electrode, 11...Emitter electrode, 14...Base, anode short-circuit electrode, 16...PN junction surface exposed part.
Claims (1)
ース、エミツタ相互の電気的導通方向と逆方向導
通型のダイオードを同一基板上に並列に接続した
トランジスタ回路において、トランジスタのエミ
ツタとダイオードとの接続配線を環状に設け、環
状内部にトランジスタのベースとダイオードとの
接続配線を設けたことを特徴とする半導体装置。1. In a transistor circuit in which a diode of a conduction type opposite to the direction of electrical conduction between the base and emitter is connected in parallel on the same substrate between the base and emitter of the transistor, the connection wiring between the emitter of the transistor and the diode is arranged in a ring shape. What is claimed is: 1. A semiconductor device characterized in that a wiring is provided inside the annular shape to connect a base of a transistor and a diode.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22460784A JPS61102061A (en) | 1984-10-25 | 1984-10-25 | Semiconductor device |
| US06/790,669 US4758872A (en) | 1984-10-25 | 1985-10-23 | Integrated circuit fabricated in a semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22460784A JPS61102061A (en) | 1984-10-25 | 1984-10-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61102061A JPS61102061A (en) | 1986-05-20 |
| JPH0438134B2 true JPH0438134B2 (en) | 1992-06-23 |
Family
ID=16816374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22460784A Granted JPS61102061A (en) | 1984-10-25 | 1984-10-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61102061A (en) |
-
1984
- 1984-10-25 JP JP22460784A patent/JPS61102061A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61102061A (en) | 1986-05-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |