JPH0438036A - Atm switch - Google Patents

Abstract

PURPOSE:To easily increase a buffer length with a few wiring number and simple wiring by outputting it to a 1st unit switch that the information is stored in a storage means of a 2nd unit switch in the 1st and 2nd unit switches adjacent to each other. CONSTITUTION:A buffer 10 analyzes path information of an inputted cell, classifies a cell for each desired output port and stores the cell while storing the arrival of order. An MUX 20 receives information representing whether or not the cell is stored and informs whether or not the cell inputted from each cell input line 4011 is stored in the buffer 10 to a pre-stage common buffer ATM switch through a relevant confirmation output line 4021. When it is informed that the outputted cell is surely received by a post-stage common buffer ATM switch through a confirmation input line 5021, the buffer 10 deletes the outputted cell after the end of output from the inside of the buffer 10.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an ATM switch that performs cell switching operations in an ATM communication network that performs information communication using fixed-length short packets called cells. Regarding.

(Prior art) In recent years, STM (Synchronous Traverse
nsferMode), the communication terminal uses the information transfer capability of the communication network when necessary.
Synchronous Transfer Mode)
Interest and expectations are increasing.

ATM transmits information using short packets consisting of fixed-length information called cells, and each communication terminal passes communication network cells as needed.In other words, the information transfer ability of the communication network is transmitted when the communication terminal needs it. This is a transfer mode characterized by the use of . Because all cells have the same length, a periodic structure with a length equal to the cell length is created on the cell transmission path in a communication network (hereinafter referred to as an ATM network), and each cell is transmitted on this periodic structure. be done. Here, if there are no cells to be transmitted, a period of time during which no cells are transmitted is inserted using the periodic structure as a unit.

Compared to STM, ATM has the ability to provide communication terminals with any information transfer speed they need, and improves communication efficiency because it uses the information transfer capacity of the communication network only when the communication terminal needs it. There are advantages such as:

For this reason, ATM is attracting attention as a basic technology for constructing a communication network that can handle voice, data, video, etc. in an integrated manner, that is, a B-ISDN network.

In order to configure an ATM network, a unit switch is required that performs an operation (cell switching) that transfers cells delivered from a plurality of input communication paths to a desired output communication path according to strategy information possessed by the cells.

Since communication terminals connected to the ATM network pass cells to the ATM network when necessary, a plurality of cells may simultaneously go to the same output communication path within a unit switch, that is, blocking may occur. When blocking occurs, one of the plurality of cells causing blocking is transferred to the output communication path, and the remaining cells are temporarily stored inside the unit switch. A cell once stored inside a unit switch is output when the route to which the cell is directed becomes vacant. Therefore, a unit switch is realized by a combination of a buffer that temporarily stores cells when blocking occurs and a switching element that transfers the cells to a desired output communication path.

As mentioned above, cell transmission is performed based on a periodic structure equal to the cell length, and cell switching is a function performed on a cell-by-cell basis, so the operation inside a unit switch has a length equal to the periodic structure on the transmission path. They are often designed to have an operating cycle of .

One type of ATM switch is a common buffer type ATM switch. As reported in ``Study'' (July 20, 1989), the cell loss rate is the lowest when the buffer size is the same among the currently known unit switches, and it is a good choice when constructing a large-scale ATM switch. It is an ATM switch that is an important component and has a configuration in which a plurality of unit switches are connected. A unit switch in a common buffer type ATM switch has a multiplexer (
MIJX) and a demultiplexer (DEMLI) at the output section.
X). In other words, in a unit switch in a common buffer type ATM switch, the switching element is MU
It is separated into X and DEMUX.

A unit switch in a common buffer type ATM switch according to the prior art performs the following operations to realize cell switching.

Cells input from each input port of the unit switch are time-division multiplexed by the MUX within one operation period of the unit switching and input into a buffer. In conventional common buffer type ATM switches, the order of time division multiplexing of cells input from input ports is generally fixed. That is, the order of transferring cells from the input port to the buffer within one operating cycle is fixed.

DEMUX is, within one operation cycle of the unit switch,
All accommodated output ports are sequentially specified, cells destined for the specified output port, which is the specified output means, are read from the buffer, and the read cells are output from the desired output port.

The buffer analyzes the route information of the input cell,
Cells are classified by desired output port and stored while maintaining the order of arrival. Here, in the common buffer type ATM switch according to the prior art, if there is no area in the buffer for newly storing cells input from the input port, that is, an empty area, the input cells are discarded. Further, the buffer outputs the cell that has been accumulated for the longest time among the cells that are directed from the DEMUX to the designated output port. Since cells must be output at the same time in a unit switch, the buffer can input the same number of cells as the number of input ports that the unit switch has during one operation cycle of the unit switch, and , it is necessary to be able to output the same number of cells as the number of output boats. As a result, in the case of a common buffer type ATM switch, the operating speed required of the buffer inside the unit switch becomes extremely high.

By performing the above operations, all the input communication paths and output communication paths accommodated by the unit switch can share and use a single buffer, thereby increasing the buffer utilization efficiency. be able to. However, since all input/output communication paths accommodated use a single storage area as a buffer, the common buffer type A
The unit switch used in the TM switch has the disadvantage that the operating speed required for the buffer is high. Generally, this drawback is solved by increasing the parallelism of information transfer, thereby reducing the number of times information is transferred per unit time.

Here, the buffer is, for example,
As disclosed in Section 6, RAM (Random AccessMe
memory) and a control circuit that creates write/read addresses for the RAM. Therefore, increasing the degree of parallelism in information transfer specifically corresponds to increasing the number of bits of data that the RAM can simultaneously input and output.

The number of cells that can be stored simultaneously inside the buffer, ie, the buffer length, is an important system parameter that determines the cell loss rate. Generally, the longer the buffer length, the lower the cell discard rate.

However, in general, the longer the buffer length, the more complex the unit switch control becomes. Therefore, ATM
When constructing a switch, it is desirable to have a configuration in which the buffer length of the ATM switch can be flexibly set. The common buffer type ATM switch according to the prior art is designed to use general-purpose RAM as a storage area for buffers.
A dedicated LSI for controlling cell writing/reading has been developed, and is configured by a combination of the general-purpose RAM and the dedicated LSI for cell writing/reading control.

However, in order to obtain the operating speed required for the buffer, the RAM is designed to have a large number of data bits that can be input/output simultaneously. There are problems in that the number of wires between the general-purpose RAM and the dedicated LSI for cell write/read control is increased, and the connections between these LSIs are also complicated. Also, A.T.
Since the signals input and output from the M switch are high-speed signals of 150 Mbps or more, ATM
Another problem was that the switch was difficult to implement. Furthermore, the upper limit of the buffer length is suppressed by the control circuit that creates RAM write/read addresses.
There is also the problem that if the demands on the ATM switch change, the necessary buffer length may not be obtained.

Furthermore, in the unit switches in the common buffer type ATM switch according to the prior art, the order of cell transfer to the buffer within one operation cycle between each input port, that is, the order of time division multiplexing in the MUX is fixed. Therefore, compared to the first cell transfer from the input port of the unit switch to the buffer within one operation cycle, there is a higher probability that there is no free space in the buffer when the cell is transferred from the last input port. Therefore, the rate at which cells are discarded differs for each input port. Therefore, when a large-scale ATM switch is configured by connecting common buffer type ATM switches according to the conventional technology,
There were also problems in that the ease with which cells could pass through routes within large-scale ATM switches was different, making call setup difficult.

(Problems to be Solved by the Invention) As explained above, in order to obtain a buffer length that sufficiently reduces the cell discard rate, it is necessary to
A conventional ATM switch configured by connecting chips (chips) includes a dedicated LSI for cell write/read control of unit switches necessary to realize the ATM switch.
There was a problem in that there were a large number of interconnections between the two, making it difficult to implement. Furthermore, since the upper limit of the buffer length is limited, there is a problem that it may not be possible to meet the requirements of the ATM switch.

Additionally, conventional ATM switches have a problem in that when the ATM switches are connected to form a large-scale ATM switch, the ease with which cells can pass through the routes inside the large-scale ATM switch is different, making call setup difficult. There were also points.

The present invention has been made in view of the above points, and the first object of the invention is to easily increase the buffer length with a small number of wires and simple wires, and to improve the buffer control circuit. An object of the present invention is to provide an ATM switch in which the maximum buffer length can be arbitrarily set free from restrictions.

In addition, the purpose of the second invention is to achieve large-scale A
It is an object of the present invention to provide an ATM switch in which the internal route cells of the TM switch have equal ease of passage and call setup is easy.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above-mentioned object, the ATM switch of the present invention includes an input means for inputting predetermined information in fixed length units, and an input means for inputting predetermined information in fixed length units. In an ATM switch having a configuration in which a plurality of unit switches are connected, the unit switch is composed of a storage means for storing fixed-length information for each unit, and an output means for outputting information from this storage means for each unit. A second unit switch of adjacent first and second unit switches among the switches outputs to the first unit switch that the information is stored in the storage means of the second unit switch. The first unit switch is characterized by comprising a confirmation input means for receiving an output from the confirmation output means of the second unit switch.

The other is a plurality of input means for inputting predetermined information in fixed length units, a storage means for storing the information in fixed length units of the input means for each unit, and a storage means for storing the information in fixed length units. The apparatus is characterized by comprising: information input order determining means for varying the input order of information by the input means; and output means for outputting information from the storage means.

(Function) According to the first aspect of the present invention, in an ATM switch configured by connecting a plurality of unit switches, predetermined information having a fixed length input through input means from a unit switch in the previous stage is used. It becomes possible to confirm that cells (hereinafter referred to as cells) have been reliably accumulated in the buffer in the subsequent unit switch. This is because the unit switch at the subsequent stage is provided with a confirmation output means, and the unit switch at the previous stage is provided with a confirmation input means. Note that the unit switch refers to each of a plurality of switches provided inside the ATM switch.

As described above, if there is no free space in the buffer in the subsequent unit switch and the output from the previous unit switch cannot be stored in the buffer inside the subsequent unit switch, the previous unit switch will - Flow control can be performed in which a cell that has been output is held without being discarded, and the cell is output again when a buffer inside a subsequent unit switch becomes available. By performing flow control, the buffers inside the ATM switch system can work together to avoid pronking, and the length of the buffer inside the ATM switch system is equivalently increased. As a result, even if the demands on the ATM switch system change, the buffer length can be easily increased with a small number of wires and simple wiring, and the maximum buffer length can be freely set without being limited by the buffer control circuit. A configurable ATM switch can be obtained.

Further, according to the ATM switch of the second aspect of the invention, it is possible to change the input order of cells to the input means for inputting cells to the storage means for storing cells by the cell input order determining means. Cell inputs from the plurality of input means to the storage means can be averaged and made fair. As a result, when a large-scale ATM switch is configured using the ATM switch according to the present invention, each internal route of the large-scale switch can have the same ease of cell passage, and therefore a large-scale ATM switch that can easily set up a call can be easily configured. You can get an ATM switch.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Figure 1 shows a common buffer type ATM which is an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of a switch.

Figure 1 shows input ports #0 to #3 as multiple input/output means.
, so-called 4 output boats #0 to #3 have 4 each.
It is a common buffer type ATM switch with 4 inputs and 4 outputs. In FIG. 1, the buffer 10 serves as a storage means and temporarily stores input cells, and the MUX 20 time-division multiplexes the cells input from each input port #0 to #3 and inputs the multiplexed cells to the buffer 10.

Then, the DEMUX 30 reads the cells from the buffer and transfers them to each output port #O to #3. Input ports #O to #3 consist of cell input lines 401o to 4013 and confirmation outputs 402o to 402. Note that cells are input to the cell input lines 401° to 4013, and confirmation output lines 402 to 4023 are connected to the corresponding cell input lines 401 to 4013.
The common buffer type ATM at the previous stage (not shown) ensures that the cells input from 4013 are accumulated in the buffer 710.
Shown below. Output ports #0 to #3 are cell output lines 50
1 to 5013 and confirmation input lines 502 to 5023. Note that cells are output from the cell output lines 501 to 5013, and confirmation input/output lines 502 to 5023 ensure that the cells output from the corresponding cell output lines 501 to 5013 are transferred to the buffer of a subsequent common buffer type ATM switch (not shown). You can confirm that the data has been accumulated.

The operation of the ATM switch shown in FIG. 1 will be explained in detail.

Cell input is performed according to a procedure.

Cells input from each cell input line 4011 of the common buffer type ATM switch are transferred to the AT by the MUX 20.
The signals are time-division multiplexed and input to the buffer IO within one operating cycle of the M switch. Hereinafter, i will be an integer from 0 to 3. That is, i corresponds to the number of input/output reports #0 to #3.

The buffer 10 analyzes the route information of the input cells, classifies the cells for each desired output port, and stores them while maintaining the order of arrival. Here, various methods can be considered for accumulating cells in the buffer 10, such as a method using a linked list as disclosed by the present inventor in Japanese Patent Application No. 1-3566, but the effectiveness of the present invention may vary. Since I will not give any details, I will proceed with the explanation without any particular limitations. If there is free space in the buffer 10 and cells can be accumulated, the buffer 10 sends an MU to that effect.
Notify X20. The MUX 20 receives information indicating whether or not the cells from the buffer IO have been stored, and indicates whether or not the cells input from each cell input line 4011 have been stored in the buffer IO through the corresponding confirmation output line 402. Notify the preceding common buffer type ATM switch that the ATM switch does not. In addition, the confirmation output line 4 of the common buffer type ATM switch
02 and the confirmation input line 502 are connected to a control section (not shown), and can be controlled in an integrated manner by this control section.

On the other hand, cell output is performed as follows.

The DEMUX 30 sequentially specifies all the accommodated output ports within one operating cycle of the ATM switch, reads cells directed to the output ports from the buffer 10, and outputs the cells through the read cell output line 501□. In order to realize this operation, the buffer IO needs to have the ability to output the oldest stored cell among the cells directed from the DEMUX 30 to the specified output port.

Additionally, DEMUX 30 monitors the verification input line 502 while outputting cells from each output caponide. If it is notified through the confirmation input line 502 that the output cell has been definitely received by the subsequent common buffer type ATM switch, the buffer 10 is notified of this fact. The buffer 10 confirms that the output cell has been accepted by the common buffer type ATM switch in the subsequent stage 9, and
After the output is finished, the output cell is deleted from inside the buffer 10. If it is notified through the confirmation input line 5021 that the output cell was not definitely received by the subsequent common buffer type ATM switch, the cell is not deleted after output and the next operation is performed. Output again at regular intervals.

FIG. 2 shows the desirable operation timing of the common buffer type ATM switch according to the embodiment of the present invention shown in FIG.

The operation timing of a common buffer type ATM switch, which is an embodiment of the present invention, will be explained in detail below with reference to FIG.

The embodiment shown in FIG. 2 is designed to ensure that the confirmation output line 4021 indicates to a control unit (not shown) that cells are definitely stored in the buffer as early as possible after cell input is started. This is the created operation timing. In order to achieve the above purpose, the number of cells input and output from the buffer 10 is a predetermined number (four in this embodiment).
The cells are divided into small pieces and multiplexed. Furthermore, in this embodiment, the order of time division multiplexing in the MUX 20, that is, the order of inputting cells from each input port to the buffer, is changed according to a predetermined procedure for each operation cycle.
When a large-scale switch is constructed using the common buffer type ATM switch according to this embodiment, a large-scale switch can be obtained in which each internal route has the same ease of cell passage and allows easy call setup.

Here, the predetermined procedure for changing the order of inputting cells from the input ports to the buffer in this embodiment is a procedure for changing the order of inputting cells from the input ports every operation cycle as follows.

Operating cycle t: Input port #0. Input port #1. Input boat #2. Input port #3 order, operating cycle t, + 1 input port #3. Input port #0. Input boat #1. Input port #2 order, operating cycle t+2: input port #21 input port #3. Input port #O1 input port #1 order, operating cycle t+3° input port #1. Input port #2. Input boat #3. Input port #0 order, operation cycle t+4: input port #0 input port #1. The order of input port #29 is input port #3. By periodically changing the order of cell input from input ports #0 to #3 to buffer lO as described above, the buffers from each input port #0 to #3 are Cell input to IO can be averaged and done fairly.

In one embodiment of the invention, cells begin to be input and output from the beginning of the operating cycle. To start the operation cycle, for example, a clock that rises at the start of the operation cycle may be given from the control unit to the common buffer type ATM switch of this embodiment, or the unit switch of this embodiment may similarly create a lock. It may also be possible to apply the same to a common buffer type ATM switch constituted by the unit switch.

Since the cells input and output from buffer 0 are divided into four small pieces, one operating period is divided into 8 cycles, and as shown in Figure 2, the cell output from buffer IO is are assigned alternately. Furthermore, each cycle assigned to a cell input is a subcycle equal to the number of input ports accommodated by the common buffer type ATM switch, so that cell input from each input port is non-blocking as long as there is free space in the buffer. It is further divided into Similarly, each cycle assigned to cell output is accommodated by the common buffer type ATM switch so that cells can be output in a non-blocking manner as long as the buffer 10 accumulates cells destined for each output port #0 to #3. The subcycle is further divided into the number of subcycles corresponding to the number of output ports #0 to #3.

In this embodiment, cell input is performed according to the following procedure.

At the beginning of the cell, route information of a predetermined length indicating the output port to which the cell should go is attached.

In this embodiment, the explanation will proceed assuming that the route information occupies one-eighth of the length of the cell. In the next cycle after the direction information is input from the cell input line 401□ of each input port, the direction of the cell that is being input is analyzed, and an empty space inside the buffer 10 for temporarily storing the cell is saved. It is secured within that cycle (cycle 601). Input ports #0 to #3 for each subcycle of the cycle 801 for securing free space in the buffer 10
The ratio is determined by the procedure for changing the order of inputting cells from the predetermined input ports #0 to #3 to the buffer 10. Input ports #0 to #1 where cells for which free space in the buffer 10 for accumulation has been secured are being input.
The confirmation output line 402□ outputs a confirmation signal at the start of the next cycle (cycle 602). If a free space in the buffer 10 cannot be secured, the confirmation output line 402□ does not output a confirmation signal.

On the other hand, the next cycle after the buffer lo free space securing cycle 601 is assigned to cell input, and at the end of cycle 601, the first cell piece among the cells that are being input is transferred to the MUX 20. ing. A first cell input cycle 803 is then performed to transfer the first cell piece to the buffer 10. M.U.X.20
inputs the first cell pieces to the buffer 10 in a multiplexed manner according to the order determined by the procedure for changing the cell input order from the predetermined input port to the buffer 10. The buffer 10 has a free space securing cycle 6o.
The first cell pieces are sequentially accumulated in the empty area of the buffer 1o defined by 1 in which each cell is accumulated.

At the start of cycle 604, which is assigned to the cell input after cycle 603, the second cell piece of the cell that is being input is input, and in this cycle, the second cell piece is transferred to the buffer lO as in cycle 803. Accumulate in.

Thereafter, cells input from each input boat are accumulated inside the buffer 10 by executing the same procedure as in cycles 805 and 806.

Note that the confirmation output line 402□ is always initialized at the start of an operation cycle. This is because there is no need to maintain the previous state. In addition, if there is no cell input from any input port in any operation cycle (that is, if an empty cell is input), the above +7)/< will be allocated to the input port in order to secure the free area of Nothing may be done in the subcycles assigned to the input port for transferring each cell piece to the buffer 1o. Furthermore, when an empty cell is input, the confirmation output line 402□ does not need to output a confirmation signal. Here, the method of having the common buffer type ATM switch of this embodiment detect that an empty cell has been input is to use, for example, the first bit of the route information as an empty cell display bit, and the state of the empty cell display bit. such as detecting
Various methods can be considered, but since they do not affect the effectiveness of the common buffer type ATM switch according to the present invention, the explanation will be continued without any particular limitation.

On the other hand, in this embodiment, cell output is performed according to the following procedure.

Cell output is determined in each subcycle of cycle 701, which is in time for cell output starting from the beginning of the operation cycle, to output from each output port from among the cells stored in buffer 10. Incidentally, in cycle 701, when outputting a cell with an operation period t in an operation period of 11 cycles,
This is because it takes one subcycle to output a cell from the buffer IO until the cell is output from the output port based on the route information of the cell.

In this case, the longest buffer l for each output port is
The cells stored in O may be output from the output port. Inside the buffer IO, cells are accumulated in such a way that the order in which they arrive can be known for each output port they go to, and as described above, if the cells are output from the cell that has been accumulated in the buffer 1o for the longest time, the cell output will be Easy to control. The order in which the output cells are determined here is, for example, output port #0. Output boat #2. The order may be output boat #3.

The cycle following the cycle 701 in which the output cell is determined is assigned to the cell output from the buffer IO. The first cell piece of the cells selected to be output in cycle 701 is then multiplexed and output from the buffer IO (cycle 702).

The DEMUX 30 receives the cell pieces output from the buffer 10 and outputs them from the cell output line 501 (cycle 703). The multiplexing order here may be the same as the cycle in which the output cells are determined.

Before the output of the first cell piece is finished, the buffer 10 reads out the second cell piece to be output next (cycle 704) and transfers it to the DEMUX 30. Following the output of the first cell piece, the DEMUX 30 begins outputting the second cell piece. Thereafter, cells are output from each output port while similarly executing cell output cycles 705 and 708 from the buffer 10.

On the other hand, at the end of cycle 705, a confirmation input line 5021 informs whether or not a cell has been reliably input to the buffer of the unit switch from the buffer of the subsequent unit. The confirmation input line 502. In each subcycle of cycle 707, it is determined whether or not the cells being output from each output port may be erased from the buffer 10, based on the information notified through. Note that this determination may be made at least after the cycle in which the vacant area of the sofa is secured.

In other words, if a confirmation input line confirmation signal included in an arbitrary output port is being output, the cell being outputted from the output port may be deleted from the Tsuku Sofa 10 after the output of the cell is finished. The means for erasing cells from the bath 10 is realized by, for example, a RAM as a storage area in which the bath 10 temporarily stores cells, and a control circuit that creates write/read addresses for the RAM''M. In this case, this can be easily realized by regarding the address storing the cell that is allowed to be erased from the buffer in this cycle 707 as the address of the free area.

Note that the procedure for changing the cell transfer order in order to obtain the effects of the present invention is not particularly limited to the above-mentioned procedure, and various modifications can be considered. For example, the following procedure may be used. Let i be the input port that was last able to transfer a cell to the buffer in the operation cycle before the operation cycle of interest. In the operation cycle of interest, input port # (i+1) mod
4° input port # (i+2) mod 4° input port # (i+3) mod 4° input port #
Transfer cells to the buffer in order of i. If this is now im2, input port (i+1) mod 4 is input port #3, and if you do the same thing below, input port #0. #
1. It becomes #2. Note that mod is a function that calculates the remainder after division. In other words, according to the above procedure, if the buffer IO becomes full during the operation cycle of interest and cells cannot be input from the intermediate input port,
In the next operation cycle, transfer from the input port to the buffer is started. Therefore, the transfer from each input port to the buffer can be changed. Therefore, the above procedure can suppress the dispersion of cell residence time inside the buffer to a small value. This is an A using common buffer type ATM.
In the TM communication system, this also leads to equalizing the ease with which cells can pass through each path of each common buffer type ATM switch.

Figure 3 shows a common buffer type ATM which is an embodiment of the present invention.
FIG. 3 is a diagram showing a method of obtaining an arbitrary buffer length using a switch. When common buffer type ATM switches according to the present invention are connected in series as shown in FIG.
02□ and confirm, due to the function of the output line 502, the buffers inside each common buffer type ATM switch connected in series will work together, and the common buffer type ATM switches connected in series will By varying the number, a common buffer type ATM switch with an arbitrary buffer length can be obtained. In short, any desired buffer length can be obtained by simply connecting common buffer type ATM switches in series, so any desired buffer length can be obtained with a small number of wiring lines and simple wiring.

Further, FIG. 4 shows an example of a large-scale ATM switch constructed using the common buffer type ATM switch according to the present invention. The large-scale common buffer type ATM switch shown in Fig. 4 is an embodiment of the present invention, in which 4 x 3 4-input 4-output common buffer type ATM switches are lined up and connected using a connection method well known as cross network connection. Has a connected configuration.

Since buffer cells (not shown) inside the common buffer type ATM switch according to the present invention are averaged and transferred fairly, it is possible to equalize the ease with which cells can pass through each route inside the large-scale ATM switch shown in FIG. Furthermore, in the large-scale ATM shown in FIG. 4, each common buffer type ATM
Since the buffers inside the M switch work together, this is a common buffer type AT with an equivalently large buffer length.
It can also be considered as an M switch.

[Effects of the Invention] As explained above, according to the ATM switch of the present invention, the number of wirings connecting each unit switch can be reduced and simplified. Therefore, the buffer capacity within the unit switch can be equally increased. In addition, the maximum buffer length can be set arbitrarily, avoiding the limitations of the buffer control circuit.
An object of the present invention is to provide a TM switch. Further, according to the present invention, it is possible to provide an ATM switch in which the internal routes of a large-scale ATM switch have equal ease of passing cells, and call setup is easy when the scale is increased.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram explaining desirable operation timing of an embodiment of the present invention, and FIG. 3 is a diagram illustrating the configuration of an embodiment of the present invention. Figure 4 explaining how to configure an ATM switch with
The figure is a diagram of a large-scale ATM switch constructed according to an embodiment of the present invention. 10--buffer, 20-MUX, 30-DEMUX
.

Claims (2)

[Claims] (1) An input means for inputting predetermined information in fixed length units, a storage means for accumulating information in fixed length units of this input means for each unit, and outputting information from this storage means for each unit. In an ATM switch having a configuration in which a plurality of unit switches are connected, the second unit switch of the adjacent first and second unit switches among the unit switches is configured such that the information is 2
The information stored in the storage means of the unit switch of the first
A, characterized in that the first unit switch is provided with a confirmation input means for inputting the output from the confirmation output means of the second unit switch.
TM switch. (2) A plurality of input means for inputting predetermined information in fixed length units, a storage means for storing the information in fixed length units of the input means for each unit, and the input means to the storage means An ATM switch comprising: information input order determining means for varying the input order of information; and output means for outputting information from the storage means.