JPH0438016B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a synchronization circuit, and more specifically, a control circuit that advances a control sequence in synchronization with a synchronous clock, by applying a signal asynchronous to the synchronous clock. The present invention relates to a synchronization circuit for synchronizing and capturing data with a synchronous clock.

[Prior art and its problems]

Digital control devices usually have a synchronous clock, and a method is used in which the control sequence progresses in synchronization with the synchronous clock.
In the interface section and external interface section,
In many cases, asynchronous signals are handled, and the asynchronous signals are synchronized in the interface section, taken into the digital control device, and used in the sequence control circuit within the device.

FIG. 4 shows a configuration in which a bus and an external signal path are connected to a digital control device with a built-in synchronous clock. In the figure, DC has a built-in synchronous clock,
A digital control device with certain functions, B is a bus, and OL is an external signal path. Asynchronous signals which are not synchronized with the synchronous clock built into the digital control device DC are received from the bus B and the external signal path OL. Therefore, in order to synchronize this asynchronous signal to the synchronous clock, a synchronization circuit is required at the input from bus B and external signal path OL.

FIG. 5 is a block diagram of an example of a synchronization circuit according to the prior art, and FIG. 6 shows the timing of its operation sequence.

That is, the asynchronous signal from bus B is
_R1 is received, and the output signal S1 (asynchronous external input signal) is sent to the flip-flop for synchronization.
Enter _F1 . Flip-flop _F1 is configured as a D-type (delay type) flip-flop, and D
A signal S1 is input to the input terminal, and a synchronous clock C from a synchronous clock generator CG is input to the T input terminal.

The synchronization circuit shown in FIG. 5 operates at the timing of the operation sequence shown in FIG. 6 in a normal state.

For example, as shown in FIG.
When the signal S1 is received (changes from "0" to "1") between timings _t1 and _t2 , it is set in flip-flop _F1 at the falling edge of timing _t2 of the synchronous clock C, Synchronous clock C
In synchronization with, the output terminal Q of flip-flop _F1
An output signal S2 is obtained from.

Since the signal S2 is a synchronous signal, it is used together with the control signal S5 inside the digital control device (DC, see Figure 4) as well as the control signal S necessary in the combinational circuit CBC.
3, S4, etc., and generates the next flip-flop
F ₂ , F _{3 ,} etc. can be controlled. signal S3,
S4 becomes a stable signal by the next timing _t3 of the synchronous clock C.

FIG. 7 is a diagram showing the relationship between the timing of arrival of an asynchronous external signal and the timing of a synchronous clock, which may be the cause of a failure. In the figure, C indicates the waveform of the synchronous clock C, S1 indicates the waveform of the external signal, and S2 indicates the waveform of the synchronous flip-flop.
This shows the waveform of the Q output S2 of _F1 .

The time required for the external signal S1 to set up the synchronous flip-flop _F1 ( _tSU ) as shown in FIG.
If the timing changes within a range that does not satisfy the
The Q output signal S2 of the synchronous flip-flop _F1 has the waveform shown in or.

If flip-flop F ₁ is inverted at timing t ₁ , then cannot be inverted at timing t ₁ , but inverted at timing t ₂ ,
When is inverted at an irregular timing between timing t ₁ and t ₂ , and when is completely inverted at timing t ₁ and inverted again before the next timing t ₂ , the respective Q output signals S2 This shows the waveform of Although neither of these actions can be said to be normal,
, are synchronized with the synchronous clock C, so that the combinational control circuit CBC can operate normally. The probability of occurrence of or is very small, but it will not become a synchronized signal, so
It is not possible to guarantee the normality of subsequent operations such as the following, and this becomes a cause of intermittent failures that occasionally occur.

In order to prevent the above drawbacks, two stages of synchronous flip-flops F ₁₁ and F ₁ are installed in series as shown in FIG. 8, and in the output signal S2 of FIG _. There is a known means for synchronizing the flip-flop _F1 in the second stage even if an abnormal operation occurs such as sending out a signal. FIG. 9 is a diagram showing the timing relationship of each signal in the conventional circuit shown in FIG. 8. 8th
In the figure, the symbols correspond to those in FIG. 5, and _F11 is a flip-flop similar to flip-flop _F1 , and S11 is the Q output signal of flip-flop _F11 .

In FIG. 8, when an asynchronous external signal _S1 arrives at the timing shown in _FIG . At time _t3 , a signal S2 is generated from the Q output of the synchronous flip-flop _F1 .
This signal S2 is given to the subsequent circuit as a synchronization signal.

Here, as shown in the timing relationship diagram of FIG. 7, if the signal S1 changes at a timing within a range that does not satisfy the time required to set up the flip-flop _F11 , the Q of the synchronous flip-flop _F11 changes.
The output signal S11 is the signal S2 in FIG.
Alternatively, it becomes a signal with the waveform shown in . Among these, even if the waveform _of .
(S2 in FIG. 9), and therefore the next stage circuit operates normally.

In this way, failures that may occur due to variations in the timing of the external signal S1 can be prevented, but since the synchronization clock is required twice to synchronize the asynchronous external signal S1, the synchronization delay time is ignored. become unable. In FIG. 9, td indicates the synchronization delay time, which is one period of the synchronization clock C at the minimum, and two periods at the maximum.

As described above, the conventional technology has a drawback in that when attempting to reliably synchronize asynchronous external signals, the delay time during synchronization becomes long.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization circuit that eliminates the above-mentioned drawbacks of the prior art, ensures synchronization of asynchronous external signals, and minimizes the delay time during synchronization. be.

[Key points of the invention]

The synchronization circuit according to the present invention is a synchronous control circuit that synchronizes an external asynchronous signal to a synchronous clock and uses it for internal sequence control, and a synchronization flip-flop is provided, and two transparent type flip-flops are provided at the front stage of the synchronization flip-flop. latches in parallel, one asynchronous signal from the outside is simultaneously input to both of the two latches, the asynchronous signal from the outside is latched to the two latches at the leading edge of the pulse of the synchronous clock, The outputs of the two latches are input to an OR circuit, and the OR output is input to the synchronization flip-flop,
The synchronizing flip-flop is configured to provide operating timing at the trailing edge of the synchronizing clock pulse.

The pulse width of the synchronization clock is set to a time slightly larger than the total time of the setup time of the synchronization flip-flop, the delay time of the OR circuit, and the hold time of the latch, so that the synchronization timing of the synchronization flip-flop is latching the asynchronous signal from the outside into the two latches by the synchronous clock at a timing earlier than the pulse width of the synchronous clock;
The OR of the output is inputted to the synchronizing flip-flop, and a synchronizing signal is obtained from the synchronizing flip-flop using the synchronizing clock.

According to one embodiment of the present invention, an external asynchronous signal is latched into the two latches at the leading edge of the synchronous clock pulse, and the timing of operation of the synchronous flip-flop is provided at the trailing edge of the pulse.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, B is a bus, R ₁ is a receiver that receives asynchronous external signals from the bus, S1 is its output signal, L ₁ and L ₂ are transparent type latches, S21 and S22 are their respective output signals, and OR is Inputs signals S21 and S22, generates OR output signal S23, and converts the synchronous flip-flop.
The OR circuit C input to _F1 is a synchronous clock and is connected to the respective clock inputs of flip-flop _F1 and latches _L1 and _L2 . In addition, the output signal (non-identical signal) S1 of the receiver _R1 is connected to the latch _L1 ,
Enter both L ₂ .

FIG. 3a shows the connection configuration of the transparent type latch _L1 shown in FIG. 1, and FIG. 3b shows its operation timing. Note that latch _L2 has a similar configuration and operates in the same manner.

In Figure 3a, _L1 is a latch, FF is a D-type flip-flop that is inverted in response to the leading edge (rising pulse) of the synchronous clock C, AND is an AND gate, OR ₁ is an OR gate, S1, S2
1 and C correspond to those in FIG.

FIG. 3b is an operation timing diagram of the latch shown in FIG. 3a.

Now, if the input signal S1 is "0", the flip-flop is in a reset state (Q output is "0", output is "1") by the clock C. AND gate AND has one input (output) as “1”
is in a conductive state, but since the signal S1 is "0", its output is "0". On the other hand, since the Q output of the flip-flop FF is "0", the two inputs of the OR gate _OR1 are both "0", and its output signal S21 is also "0" like the input signal S1.

Now, when the input signal S1 changes from "0" to "1" at time _tA , that "1" is an AND gate.
It is output via AND and OR gate OR ₁ , and its output signal S21 becomes "1" like the input signal S1.

At the leading edge (rising edge) of timing _t2 of the synchronous clock C, the flip-flop FF is inverted, and the Q output is held at "1" and the output at "0".
The Q output becomes "0", the AND gate AND becomes non-conductive, and its output becomes "0", but the Q output "1" is output via the OR gate OR ₁ , and the output signal S21 is determined by the signal S1. Regardless, it is latched to “1”.

Assume that at time _tB , the input signal S1 changes from "1" to "0" and the input signal S1 disappears.
Leading edge (rising edge) of timing _t4 of synchronous clock C
Then, the flip-flop FF is inverted, and the Q output becomes "0" and the output becomes "1". At this time, the AND gate AND becomes non-conductive and the output becomes "0", so the output signal S21 becomes the input signal S1.
It becomes "0", which is the same as "0".

Now, FIG. 2 is a diagram showing the operation timing of the synchronization circuit according to the present invention shown in FIG. 1. In the figure, C indicates the timing of the synchronous clock C, S1,
S21, S22, S23, and S2 indicate the timing of the signals with the same names, t _h is the hold time of the latches L ₁ and L ₂ , t _pd is the delay time of the OR circuit, and t _su is the setup time of the flip-flop F ₁ . Indicate the time for each. Note that t _w is the clock width of the synchronous clock C, and is set slightly larger than the total time of the above-mentioned setup time t _su , delay time t _pd and hold time _th . synchronous flip-flop
The timing of setting _F1 is the timing of the trailing edge (falling edge) of the pulse of synchronous clock C, and the timing of the latching of latches _L1 and _L2 is the timing of the leading edge (rising edge) of the pulse of synchronous clock C, as described above. The timing is right.

In the synchronization circuit according to the invention of FIG. 1, the signal from bus B is received by receiver R ₁ and
As shown in the figure, at timing _tA , the asynchronous external signal S1 (changes from "0" to "1") is input to the latches _L1 and _L2 . Since latches L ₁ and L ₂ are transparent type latches,
After a hold time _th , the output signals S21 and S22 change to follow the signal S1. Similarly, the signal S23 similarly changes with a delay of the OR circuit OR delay time t _pd . At the leading edge (rising edge) of the pulse at timing t ₂ of the synchronous clock C, latches L ₁ and L ₂ latch the signal S1, and at least at the next timing t ₃
Even if there is a change in the signal S1, it does not respond to the leading edge (rising edge) of the pulse. As a result,
At the trailing edge (falling edge) of the pulse at timing _t2 of the synchronous clock C, the synchronous flip-flop _F1 sets a stable signal S23, making it possible to create a signal S2 completely synchronized with the synchronous clock C.

Since transparent type latches _L1 and _L2 are provided in parallel, synchronous flip-flop
The input signal S23 to _F1 can be a reliable and stable signal. That is, even if the signal S1 changes within the range of the set-up time _{t su} preceding the rising edge of the synchronous clock C shown in FIG.
Since the outputs of L ₁ and L ₂ form the input signal S23 to the synchronous flip-flop F ₁ via the OR circuit OR, if either one of the latches L ₁ or L ₂ responds normally, the input signal S23 is Normality is guaranteed. Also, if one latch does not respond and the other latch operates unstablely, for example, as shown in FIG.
Even if an output _{signal like} By operating with the next synchronous clock, malfunctions unlike the conventional circuit shown in FIG. 5 do not occur. Although it is theoretically conceivable that the synchronous flip-flop _F1 may malfunction at the same time, it is actually extremely unlikely that the latch and the synchronous flip-flop _F1 malfunction at the same time, so this does not pose a problem in practice.

〔Effect of the invention〕

Since the present invention is configured as described above, the present invention makes it possible to more reliably synchronize asynchronous signals, and furthermore, it is possible to keep the delay time during synchronization to a minimum (one cycle of the maximum synchronization clock). There is an effect. Since the delay time during synchronization can be minimized, it is effective for synchronization circuits that are becoming faster.

Although the configuration of the present invention inevitably requires a slight increase in the number of circuit elements, in today's world where circuit integration is rapidly progressing, this increase in circuit elements is not a problem and improves the reliability of operation. The effect of shortening the delay time during synchronization is more important, and it is suitable for this type of synchronization circuit that will be required to operate reliably and at high speed in the future.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
3A is a block diagram of an example of the structure of the transparent latch in the embodiment of FIG. 1, FIG. 3B is an operation timing diagram of FIG. The figure shows a general connection configuration in which an asynchronous external signal is connected to a digital control device with a built-in synchronous clock, FIG. 5 is a block diagram of an example of a synchronization circuit according to the prior art, and FIG. normal operation timing diagram of the conversion circuit, 7th
8 is a block diagram of an improved synchronization circuit according to the prior art, and FIG. 9 is an operation timing diagram of the synchronization circuit of FIG. 8. B...Bus, _R1 ...Receiver, _L1 , _L2 ...Transparent latch, OR...OR circuit, _F1 ...Synchronous flip-flop, C...Synchronous clock, S1...Asynchronous external input signal, S2...Synchronized output Signal, FF...flipflop.

Claims (1)

[Claims] 1. In a synchronous control circuit that synchronizes an external asynchronous signal with a synchronous clock and uses it for internal sequence control, a flip-flop for synchronization is provided, and two transparent type latches are placed in parallel before the flip-flop for synchronization, One asynchronous signal from the outside is simultaneously input to both of the two latches, the asynchronous signal from the outside is latched to the two latches at the leading edge of the pulse of the synchronous clock, and the outputs of the two latches are The output of the OR circuit is inputted to the synchronizing flip-flop, and the trailing edge of the pulse of the synchronizing clock provides the operation timing of the synchronizing flip-flop, and the synchronizing clock has a pulse width that is equal to the synchronizing flip-flop. The set-up time of the flip-flop for synchronization, the delay time of the above-mentioned OR circuit, and the hold time of the above-mentioned latch are set to a time slightly larger than the total time, and the timing is earlier than the synchronization timing of the flip-flop for synchronization by the pulse width of the synchronization clock. Synchronization characterized in that the asynchronous signal from the outside is latched to the two latches by the synchronous clock, the OR of the output thereof is inputted to the synchronous flip-flop, and the synchronous clock obtains a synchronous signal from the synchronous flip-flop. circuit.