JPH0438009A - Cpu reset signal shaping circuit - Google Patents

Abstract

PURPOSE:To form a circuit with small size and high reliability inexpensively by providing an input signal latch means and a delayed input signal latch means and outputting only a clock signal consecutive for one period or over as a reset signal. CONSTITUTION:A reset signal to reset a CPU is inputted to an input terminal and a reset terminal of an input signal latch means 10, latched by a clock signal and inputted to a delayed input signal latch means 20 of a next stage. The means 20 outputs a reset signal inputted from the means 10 by using a succeeding clock signal. Thus, noise having a period shorter than the period of the clock signal is absorbed therein and not outputted from the means 20 and only a signal whose period is wider than the period of the clock signal is outputted as the reset signal. That is, only the signal whose period is wider than the period of the clock signal is outputted as the reset signal and the signals whose period is shorter than the period of the clock signal are absorbed and does not appear at the output of a D-FF 21.

Description

[Detailed Description of the Invention] [Summary] Regarding a shaping circuit that shapes the waveform of a reset signal of a CPU, the present invention aims to provide a compact, inexpensive, and highly reliable CPU set number shaping circuit. A human power signal holding means inputs a reset signal inputted to an input terminal and a reset terminal, holds and outputs the inputted reset signal with a clock signal, and disconnects the output when the reset signal is turned off, and the output of the input signal holding means , and delayed input signal holding means for holding and outputting the next clock signal.

[Industrial Field of Application] The present invention relates to a shaping circuit that shapes the waveform of a CPU reset signal.

When resetting a printed board unit on which a CPU is mounted from outside the printed board unit, if a finer pulse than specified is input, there is a high possibility that the CPU will run out of control.

Furthermore, if hot insertion and removal of the printed board unit that generates the reset signal is permitted, a circuit is required to eliminate minute noise pulses generated when the printed board unit is inserted and removed, and to shape the reset signal.

Such a CPU reset signal shaping circuit is small and inexpensive;
High reliability is required.

[Prior Art] FIG. 4 is a diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating a time chart of the conventional example.

In the conventional example described above, the input reset signal is "0".
” level, and therefore the output reset signal is also set to “0” level.

The conventional example shown in FIG. 4 includes a shift register 50 that shifts and outputs a reset signal using a clock signal, and a shift register 5
a logical sum circuit (hereinafter referred to as an OR circuit) 51 that calculates the logical sum of n outputs of 0; a negative logical sum circuit (hereinafter referred to as a NOR circuit) 52 that calculates a negative logical sum of n outputs of the shift register 50; The inverted output of the OR circuit 51 is connected to the set terminal.

S-R inputting the inverted output of the R circuit 52 to the reset terminal
Flip-flop circuit (hereinafter referred to as FF circuit) 53. 5-NAND circuit (hereinafter referred to as NAN) whose inputs are the output of the RFP circuit 53 and the n-th inverted output of the shift register 50.
This is an example constructed from 54 circuits (referred to as D circuits).

The operation of the above circuit will be explained with reference to the time chart of FIG.

■ This is the reset signal to be input.

■ Indicates a clock signal.

■ This is the output obtained by shifting the reset signal of ■ by l clock of ■.

(2) This is the output obtained by shifting the reset signal (2) by two clocks (2).

■ This is the output obtained by shifting the reset signal of ■ by n clocks of ■.

■ This is the output obtained by inputting all outputs of the shift register 50 to the OR circuit 51 and taking the logical sum, so that all outputs are "0".
”, the output is “0”.

(2) This is the output obtained by inputting all the outputs of the shift register 50 to the NOR circuit 52 and performing a negative logical sum, and when all the outputs are "0", the output becomes "1".

(2) The 5-RFF circuit 53 is set by the inverted output of (2), and the 5-RFF circuit 53 is reset by the inverted output (2).

■ A 5-RFF circuit 5 is connected to one terminal of the NAND circuit 54.
By inputting the output 3 of 3, the gate is opened, and the signal 2 is output as a reset signal with the gate being opened.

[Problem to be solved by the invention]

In the conventional example shown in FIG. 4 described above, five ICs are required to form the circuit, resulting in a large mounting area, high cost, and a large number of parts, resulting in low reliability.

SUMMARY OF THE INVENTION An object of the present invention is to provide a CPU reset signal shaping circuit that is small, inexpensive, and highly reliable.

[Means to solve the problem] FIG. 1 shows a block diagram illustrating the invention in detail.

10 in the block diagram of the principle of the present invention shown in FIG. 1 inputs the input reset signal to the input terminal and the reset terminal,
It is an input signal holding means that holds and outputs the inputted reset signal with a clock signal, and stops outputting when the reset signal is turned off. 20 is a delay that holds and outputs the output of the input signal holding means 10 with the next clock signal. The present invention is an input signal holding means, and is a means for solving this problem by outputting only a signal that has continued for one period or more of a clock signal as a reset signal.

[For production]

A reset signal for resetting the CPU is input to the input terminal and the reset terminal of the input signal holding means 10, held and output as a clock signal, and input to the delayed input signal holding means 20 at the next stage.

Since the delayed input signal holding means 20 outputs the reset signal inputted from the input signal holding means 10 with the next clock signal, noise shorter than the period of the clock signal is absorbed and output from the delayed input signal holding means 20. Only a signal longer than the period of the clock signal is output as a reset signal.

[Example] The gist of the present invention will be specifically explained below with reference to the example shown in FIGS. 2 and 3.

FIG. 2 is a diagram for explaining the present invention in detail, and FIG. 3 is a diagram for explaining a time chart of an embodiment of the present invention.

Note that the same reference numerals indicate the same objects throughout the figures.

In the embodiment of the present invention shown in FIG. 2, as in the conventional example shown in FIG. 4, the input reset signal is a "0" level signal, and the output reset signal is also a "0" level signal.

It consists of an inverter (hereinafter referred to as INV) 11 and a D-flip-flop circuit (hereinafter referred to as FF circuit) 12 as the input signal holding means 21 explained in FIG. 1, and a D-FF circuit 21 as the delayed input signal holding means 2. This is an example.

The output of INVll is connected to the reset terminal of the D-FF circuit 12, and it is reset when the output of INVII reaches the "0" level.

Furthermore, since the reset signal to be output is a "0" level signal, the negative output q of the D-FF circuit 21 is taken as the reset signal.

The operation of the above-mentioned circuit will be explained with reference to the time chart of FIG.

(1) Input reset signals, (a) is a normal reset signal, and Q)) is a noise.

(2) This is a signal obtained by inverting the reset signal (a) by INVII.

(3) It is a clock signal.

(4) Convert the inverted reset signal (1) to the clock signal (3)
) is the output of the D-FF circuit 12.

The output of INVll is connected to the reset terminal of the D-FF circuit 12, and when the inverted reset signal (2) becomes "0", the output of the D-FF circuit 12 is reset to "0". Become.

(5) This is the output Q of the D-FF circuit +1, which is the output of the D-FF circuit divided by 4, which is clocked by the clock signal (3).

(6) This is the negative output Q of the D-FF circuit 41, and this signal becomes CP and becomes a reset signal.

Due to the above-described operation, only a signal having a period equal to or longer than the clock signal is outputted as a reset signal, and a signal having a period equal to or less than the clock signal is absorbed and does not appear on the output side of the D-FF circuit +1.

In the above embodiment, the reset signal is a "0" level signal, but it is of course possible to shape a "1" level reset signal with a similar configuration.

By configuring as described above, the number of ICs configuring the circuit is reduced to two, making it possible to reduce the mounting area and cost by 60% compared to the conventional example, and further improving reliability.

〔Effect of the invention〕

According to the present invention as described above, it is possible to provide a small, inexpensive, and highly reliable CPTJ reset signal shaping circuit that shapes a reset signal for resetting a CPU.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart of the embodiment of the present invention, and FIG. 4 is a conventional example. FIG. 5 is a diagram illustrating a time chart of a conventional example. In the figure, 10 is an input signal holding means, 11 is an INV, 12.21 is a D-FF circuit, 20 is a delay signal holding means, 50 is a shift register, 51 is an OR circuit, and 52 is an NO
R circuit, 53 is 5-RFPFF times 54 is NAND
The circuits and are shown respectively. Fig. 2 A diagram explaining a time chart of an embodiment of the present invention Fig. 3 A block diagram explaining a detailed explanation of the present invention Fig. 1 Fig. 4 A diagram explaining a time chart of a conventional example Fig. 5

Claims (1)

[Claims] A waveform shaping circuit for a reset signal that resets a CPU, which inputs an input reset signal to an input terminal and a reset terminal, holds and outputs the input reset signal as a clock signal, and outputs the input reset signal as a clock signal. An input signal holding means (10) that cuts off the output when turned off, and a delayed input signal holding means (20) that holds and outputs the output of the input signal holding means (10) at the next clock signal. A CPU reset signal shaping circuit characterized by: