JPH0437380A - Dropout compensation device in video disk player - Google Patents

Abstract

PURPOSE:To attain picture display without disturbance by keeping a level of a video format signal to a prescribed level forcibly over the existence period of a disable signal. CONSTITUTION:A signal reproduced from a recording signal fed from three channels of signal lines (hereinafter referred to as reproduced signal Y) is fed to an FF detection circuit 73 and a latch circuit 74. When a value [FF]H is included in the reproduced signal Y fed to the circuit 73, the output is kept to a high level for a period of [FF]H and the output is kept to a low level for a period other than the period of [FF]H. The latch circuit 74 applies time adjustment to delay the supplied reproduction Y by a time for the detection of the circuit 73 and the output confirmation and to give the result to a terminal (a) of a selection circuit 75. The output of the FF detection circuit is given to the selection circuit 75. The part of the period of the reproduction signal Y of one preceding line is replaced for the period of [FF]H, that is, a period when a dropout exists so as to compensate dropout.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a dropout compensation device in a video disc playing device.

Background Art In a video disc performance device, a drop in the level of a so-called RF multiplied signal obtained from a pickup that carries a video format signal (an information signal consisting of a horizontal and vertical synchronization signal portion and an information signal portion; the same shall apply hereinafter) is detected. For example, Japanese Patent Application Laid-Open No. 58-43684 discloses that the occurrence of a so-called dropout is known and a dropout compensation operation is performed on a video format signal obtained by RF multiplied signal demodulation using a dropout detection signal indicating this.
It is known from the publication no.

By the way, during special playback involving jump operations such as scans and searches, the continuity of the read signal is lost, and if this is subjected to image playback processing as it is, the image will be distorted.

Summary of the Invention [Object of the Invention] Therefore, the present invention provides a dropout compensation device for a video disc performance device that can display an image without disturbance not only when a dropout occurs but also during special playback involving a jump operation. The purpose is to

[Structure of the Invention] A performance means for reading a recorded signal from a video disk carrying a recorded signal including a video format signal consisting of a horizontal and vertical synchronization signal section and an information signal section, and a performance means for demodulating the signal read by the performance means to reproduce the above-mentioned signal. demodulating means for obtaining a video format signal; dropout detection means for detecting a dropout occurring in the read signal or the video format signal and generating a dropout detection signal;
Level shift means for forcibly maintaining the video format signal at a predetermined level over the period in which the dropout detection signal exists; and dropout compensation that performs dropout compensation processing for the period in which the video format signal is at the predetermined level. and a control means for generating a disable signal, the level shifting means forcing the level of the video format signal to the predetermined level over the period in which the disable signal exists. The structure is such that it is maintained in a consistent manner.

[Operation of the Invention] In the dropout compensation device for a video disk performance device according to the present invention, a dropout occurring in a read signal or a video format signal is detected to obtain a dropout detection signal.

The level of the video format signal is forcibly shifted to a predetermined level over the existence period of this dropout detection signal, and when the control means issues a disable signal, the video format signal is also forcibly shifted to the predetermined level. shift.

Example Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a system configuration diagram that divides a high-definition signal into three channels and records them on a recording medium (in this case, a laser video disc). In FIG. 1, a brightness signal Ya and two types of color difference signals Pr and P are output from a high-definition signal source 1.
An analog signal of b is output. Here, the luminance signal Ya has a frequency band of 30 MHz (hereinafter abbreviated as band), and the color difference signals Pr and Pb have a band of 15 MHz. FIG. 2 shows a schematic diagram of signal waveforms of Ya, Pr, and Pb, and high-definition H has a horizontal scanning line pulse period, which is the reciprocal of the line frequency of 33.75 KHz, and is about 29.63 μS.

These high-definition signals are supplied to the encoder 2 shown in Fig. 1, but practically the above band is not required.
The luminance signal Ya is supplied to the AD converter 4Y via a 22 MHz low-pass filter 3Y. The color difference signals Pr and pb are supplied to A-D converters 4R and 4B through 11 MHz low-pass filters 3R and 3B, respectively. A sampling clock for the AD converter group 4 is supplied from a timing pulse generation circuit 5.

In the A-D converter 4Y, the analog luminance signal Ya is converted into an 8-bit digital luminance signal Y by a 74.25 MHz clock, and is supplied to the Y process circuit 6Y. Further, the analog color difference signals Pr and Pb are 74.25/2 MH in the A-D converters 4R and 4B.
z (-37,125 MHz) clock into 8-bit digital color difference signals PR and PB, which are sent to the pi process circuit 6R and the P8 process circuit 6, respectively.
B is supplied.

FIG. 3 is a more detailed block diagram of each of the above process circuits. Here, the color difference signals PR and PB undergo so-called line sequential processing in which they are transmitted alternately for each H line, so in order to prevent aliasing noise, the P2 process circuit 6R and PB
In the process circuit 6B, vertical digital pre-low-pass filters 19 and 20 are provided.

The luminance signal Y supplied to the Y process circuit 6Y and the color difference signals P, P8 supplied to the PR process circuit 6R and Pa process circuit 6B and passed through a pre-low-pass filter are the write clock, write enable, etc. from the timing pulse generation circuit 5. The first channel HFO16Y, 16R,
16B, 2nd channel FIFO 17Y, 17R, 17B
, are written to the third channel FIFOs 18Y, 18R, and 18B. At this time, the synchronizing signal component is deleted and the color difference signal is processed line-sequentially, with the first .
It is divided into three channel signals, second and third. FIG. 4(a) shows the arrangement of the digital high-definition signals Y, PR, P after A-D conversion supplied to each process circuit, and FIG. 4(b) shows the arrangement of the first channel of each process circuit. FIFO16Y.

Write enable signal YWI to 16R and 16B.

RWI and BWI. FIG. 5(a) shows that the first channel FIFO 16Y is activated by this write enable signal.

This figure shows the arrangement of luminance signal data YD1 and color difference signal data RDI and BDI written to 16R and 16B. Fig. 4 (Fig. 4) and Fig. 5 (a) are compared.
In the figure (ω), the synchronizing signal component denoted as H-3YNC is deleted and the signals for every three lines are written into the FIFO, and the color difference signal is processed line-sequentially with PR and PR alternating. 5th issue), Figure 5 (C) shows the second channel FIFO 17Y, 17R, 17B, respectively.
This figure shows the arrangement of luminance signal data and color difference signal data written to the second channel FIFOs 1-8Y, 18R, and 18B.

Note that the write speed to the FIFO follows the write clock of the timing pulse generation circuit 5. The light clock YWφ of the luminance signal Y is 74.25 MHz, and the color difference signal P
R, PB write clock RWφ, BWφ is 74.25
/ 2 MHz = 37.125 MHz. On the other hand, the read clock for reading from the FIFO is given from the timing pulse generation circuit 5, and the read clock YRφ, RRφ, for the luminance signal Y and the color difference signals PR, P,
All BRφs are 33.75 MHz. Here, find the clock ratio for writing and reading.

74.25 MHz +33.75 MHz -2,2
-(1)37.125MHz +33.75MHz
=1.1- (2) From the above equation (1), the time axis of the luminance signal Y has been expanded by a factor of 2.2, and (2)
From the formula, it follows that the time axis of the color difference signal pR,p has been expanded by 1.1 times. The time-axis expanded signals divided into three channel signals are output as the first channel signal V1, second channel signal v2, and third channel signal V from the first, second, and third FIFO for each process circuit. be done. The output channel signals are combined by a wired-OR circuit (not shown) for each channel, and are added with a disc synchronization signal and a disc code signal given from the timing pulse generation circuit 5, and are then combined into D-A in FIG.
It is supplied to converters 7a, 7b, and 7c. Figure 6 (a
) is the first channel signal v1. that is supplied to the DA converter. The arrangement of the second channel signal V2 and the third channel signal 3 is shown. In Fig. 6 (ω), the luminance signal Y has about 29.63 μs of the IH line of the original high-definition signal, of which 3.77 μs of the synchronizing signal component has been removed, and about 25.86 μs or 2.2 μs of the video signal component only. The time axis is expanded twice and the data is read out at a clock rate of approximately 56.89 μs or 33.75 MHz.

56.89 u s x 33.75 MHZ = 192
0-(3) From equation (3), Figure 6 (Tan's Y, , Y2...
The digital luminance signal components of . . . are in units of 1920×8 bits. Similarly, the color difference signal component is 25.86μs x 1.1-28.45μs...
...(4) 28.45 us X33.75 MHZ
=960・−(5)(4) From equation (5), Figure 6 (PRI+PR2 of ω...PB□,
PR□, 1.1.・The digital color difference signal component is 960
×8 bit unit. Further, a guard interval of 8 clocks is provided between the luminance signal component and the color difference signal component.

Also, the added synchronization signal is for 112 clocks, 1920+960 +8+112-3000...
- (6) From equation (6), 3000 clocks are set as one new line and supplied to the D-A converters 7a, 7b, and 7c. Three channel signals V, , V2 and V3 consisting of a luminance signal component, a color difference signal component, a synchronization signal or a disc code signal and a synchronization signal are sent to D-A converters 7a and 7.
At b and 7c, the digital signal is converted into an analog signal at the timing of the 33.75 MHz clock provided by the timing pulse generation circuit 5.

Since the luminance signal in the 22 MHz band is time-axis expanded by 2.2 times, a band of 10 MHz is sufficient since 22 MHz + 2.2 = 10 MHz, and the color difference signal in the 11 MHz band is time-axis expanded by 1.1 times. Since it has been
Similarly, 10MHz from 11MHz+1.1 = 10MHz
The band z is sufficient. Therefore, the D-A converter 7a,
The outputs of 7b and 7c are a 10MHz low-pass filter 8a.
, 8b, 8c block unnecessary high-frequency components after D-A conversion, and the encoder 2 outputs chl, ch2 . Output as three analog signals on ch3. 6th issue) shows a schematic diagram of the output signal waveform, in which the analog luminance signal component Ya and the analog color difference signal component Pr or pb are combined into one new line of disk H. In Figure 6, the color center level is set to a value that divides the signal peak level and pedestal level into two equal parts.This is necessary when playing back the video signal from the disc after recording. .

The signals for each channel output from the encoder 2 are supplied to the selection circuit 9, and three channel signals chl and ch2 are output.
．． One of the channels 3 is selected individually or sequentially and supplied to the FM modulation circuit 10. In the FM modulation circuit 10, the supplied channel signal is li, 61 M
Hz ~14.91 MHz (deviation 3.3M
The signal is output as a low frequency FM video signal (Hz) and supplied to the synthesis circuit 11.

On the other hand, a digital audio signal output from a high-quality digital (PCM) audio source 12 separate from the high-definition signal source 1 is supplied to an EFM encoder 13, encoded, output, and supplied to a synthesis circuit 11. In the synthesis circuit 11, the FM video signal and the encoded digital audio signal are added to form one signal, which is output as an RF multiplied signal from the output terminal 14. The system controller 15 manages the series of operation controls described above.

The RF multiplied signal outputted from the output terminal 14 is amplitude-limited by a limiter (not shown) and shaped into a square wave. As a result, a multiplexed signal is obtained in which the repetition frequency represents video signal information and the change in duty represents audio information. The square wave shaped signal is applied to a light modulator of a laser cutting machine device (not shown), and the three channel signals are recorded on three discs per channel, respectively.

Figure 7 (ω, +b), (C) shows three disks A,
The formats of the video signals recorded in B and C are shown. In Figures 7(a), <b>, and (C), the line number is the number of disc H from the 6th edition),
One frame consists of 375 lines, 375 lines x 3 - 1125 lines... (7) Above (7)
), it is possible to record 1125 H-line high-definition signals per frame on three discs.

Note that in this example, recording was performed independently on three discs, but by using a cutting machine device (not shown) having an optical modulator that emits three independent laser beams, data can be recorded on one disc. It is also possible to record three tracks simultaneously.

As described above, a wideband high-definition signal can be divided into three channel signals, each of which can be independently recorded on three discs as a video signal of IOMH2 or lower. In this way, three high-definition signals were recorded.
A method for reproducing original high-definition signals from a set of recording discs using three independent video disc players will be described in detail.

FIG. 8 is a block diagram of a high-definition signal reproduction system. In FIG. 8, a first player 21, a second player 22, and a third player 23 simultaneously play a set of three high-definition signal recording disks and supply reproduced video signals and the like to a decoder 24. FIG. 9 shows the configuration of each player. A video disc 40 is rotationally driven by a spindle motor 41, and a recorded video signal is read by a pickup 42. The pickup 42 includes a laser diode, an objective lens, a collimator lens, a focus actuator, a tracking actuator, a photodiode, and the like. The output of the pickup 42 is supplied to an RF amplifier 43 and, at the same time, to a focus servo circuit (not shown) and a tracking servo circuit (not shown). RF amplifier 43
The RF video signal output from the RF video signal is supplied to a dropout detection circuit 44 and an FM demodulation circuit 45.

The RF video signal supplied to the FM demodulation circuit 45 is demodulated and output, and is output from the player via a low-pass filter 46. The reproduced output signal waveform is shown in Figure 6 (
This is equivalent to a). However, so-called dropouts may occur due to scratches on the video disc 40, adhesion of dust, etc. The dropout detection circuit 44 detects these dropouts and sets its output to a high level (Hi) during the dropout period.

It is widely known that dropout compensation is performed using a CCD or the like, which is an analog delay element that replaces and compensates for the signal one line before. However, although the broadband high-definition signal is divided into three channels to narrow the band as in this embodiment, a high-speed CCD is required to compensate for the reproduced video signal in the 10 MHz band. Further CC
Replacing the signal one line before by D does not provide sufficient characteristics as a video signal. Therefore, compensation for dropout is performed in the decoder 24 at the digital signal stage using a line memory, which will be described later. Incidentally, in order to control the speed of the spindle motor 41 within the player, a synchronizing signal component in the video signal is required.

Therefore, the output of the low-pass filter 46 further passes through a low-frequency low-nox filter 47 and is supplied to a dropout compensation circuit 48 for a synchronizing signal. This circuit is C0D
48a, a selection circuit 48b, etc., 11
．． Since the 25 KHz synchronization signal and the 30 Hz frame pulse signal are compensated for, a relatively slow CCD 48a can be used.

The dropout detection signal (hereinafter abbreviated as DO3) output by the dropout detection circuit is supplied to the decoder 24 that performs dropout compensation for the reproduced video signal, and at the same time, is supplied to the selection circuit 48b. Selection circuit 4
8b is connected to the a side in the figure when DO3 is at a low level, that is, when no dropout occurs, and transmits a real-time video signal to the synchronization separation circuit 49. When dropout occurs, DO3 becomes high level, the selection circuit 48b is connected to the b side, and the 1 from the CCD 48a is
The reproduced video signal before the line is transmitted to the synchronization separation circuit 49.

A synchronization separation circuit 49 extracts a synchronization signal (PBH) and a frame pulse signal (PBFI) from the supplied video signal.
) is separated and extracted and supplied to the spindle servo circuit 50. The synchronization signal (PBH) and frame pulse signal (PBF) supplied in the spilldle servo circuit 50
P) is the reference synchronization signal (!I
IEFH) and a reference frame signal (ADFP), and the speed of the spindle motor 41 is controlled.

On the other hand, the EFM audio signal component in the recording signal of the video disc 40 passes through the pickup 42 and the RF amplifier 43 to the EFM audio signal component.
The signal is supplied to the FM demodulation circuit 51.

The EFM demodulation circuit 51 performs processing such as EFM demodulation and error correction, and outputs each of the L channel and R channel as 8-bit digital audio signals, which are supplied to DA converters 52L and 52H. Here, the digital audio signal is converted into an analog audio signal, and the low-pass filters 53L and 53R
It is then output from the player.

The player controller controls the above series of operations within the player, and is connected to the main controller within the decoder 24 via a serial interface. As will be described in detail later, this serial interface communicates with the main controller at the frame signal cycle, which is the so-called V cycle, to exchange necessary information. Furthermore, when the player operates abnormally, a player disable signal is immediately output to the main controller through a connection line separate from the serial interface, regardless of the V cycle.

In FIG. 8, three channels of reproduced analog video signals with output signal waveforms as shown in FIG. 25, 26 and 27. The signal processing circuit 25 includes an automatic level control circuit 25a, a pulse generation circuit 25b, an A-D conversion circuit 25c, and the like.

FIG. 10 is a diagram showing the signal processing circuit 25 in more detail. In FIG. 10, the supplied playback video signal is input to the ALC/AG which performs level shift and gain control.
C circuit 55, the output of which is passed through a low-pass filter 5.
6, the signal is supplied to a limiter circuit 57 provided to prevent troubles when the signal is excessive. Limiter circuit 5
The output of 7 is supplied to the A-D converter 25c and sample and hold circuits 58 and 59. In the sample and hold circuit 58, the voltage at the pedestal level shown in FIG. In the integration circuit 60, the supplied pedestal level is compared with the reference pedestal level, and the difference is integrated and outputted via a limit circuit (not shown), and then supplied to the ALC/AGC circuit 55, where the pedestal level of the reproduced video signal is Level shifted so that the level is equal to the reference pedestal level. Similarly, in the sample hold circuit 59, the sampling pulse SP
2, the voltage at the color center level shown in FIG. be done.

The reproduced video signal supplied to the ALC/AGC circuit 55 is also supplied to the waveform shaping circuit 62 at the same time, where it is amplified, filtered, impedance converted, etc., and then sent to the sync separation circuit 63, pedestal clamp circuit 68, and disk frame pulse separation circuit 72. Supplied. Synchronous separation circuit 63
The separated synchronization signal is supplied to the ramp generation circuit 64 through a dropout sync gate circuit (not shown), etc., which stops transmission of the synchronization signal at the time of dropout. In the slope wave generation circuit 64, a capacitor (not shown) is charged and discharged in accordance with the supplied synchronization signal, and a slope wave is generated and supplied to the comparators 65, 66, and 67. Comparators 65 and 66 are window comparators that maintain the output at a high level or low level within a specified voltage range (see Figure 6).
Voltage ranges corresponding to the timing (time) for appropriately sampling and holding the color center level and pedestal level are determined. Since the ramp wave supplied to the converter is a voltage proportional to the passage of time with the synchronization signal as the time reference, by supplying the outputs of these window comparators as sampling pulses SP2 and SPI to the sample and hold circuits 59 and 58. Appropriate sample holds are made.

Waveform shaping circuit 6 supplied to pedestal level circuit 68
The signal from SPI 2 is the output of comparator 66.
The pedestal level is clamped to a predetermined voltage, regenerated as DC, and supplied to the H sink separation circuit 69. Furthermore, the gate pulses before and after the rising edge of the synchronizing signal are given to the H-sync separation circuit 69 by the comparator 67, and within the range of the gate pulse, the rising point of the synchronizing signal pulse is again accurately detected, and this rising point is detected as the leading edge of the pulse. A pulse is output. This output is connected to the pulse width expansion circuit (
(not shown), and the trailing edge of the pulse is extended and supplied as one input to the PLL circuit 70. P.L.
The L circuit 70 includes a phase comparator, a loop filter, a limiter, a VCO that generates a 33.75 MHz clock, and the like.

Frequency dividing circuit 7 as output of vCO or output of PLL circuit 70
1. Here, the 33.75 MHz clock is frequency-divided to 1/3000 and output as a 11.25 KHz pulse from the frequency divider circuit 71, and the output is sent to the PL.
It is supplied as the other input of the L circuit 70, and the phase is compared with the 11.25K H2 synchronization signal from the reproduced video signal in a phase comparator. By feeding back the phase difference to the VCO, the 33°
．． A 75 MHz clock pulse is generated and supplied to the AD converter 25c. In the A-D converter 25c, the reproduced analog video signal is converted into an 8-bit reproduced digital video signal (hereinafter simply referred to as a reproduced signal) using a 33.25 MHz clock pulse.

Since the pedestal level and color center level are adjusted to the reference level in the ALC/AGC circuit 55 mentioned above, the reproduction signal expressed in hexadecimal after A-D conversion has a pedestal level of [20]H and a color center level of [20]H. The level is [80]n. Further, during recording, the value of the color center level is set to a value that is equal to two parts between the signal peak level and the pedestal level, so the peak value of the reproduced signal is [EO]H. Therefore, values from [E1]H to [FF]5 (maximum output value of the AD converter) do not exist as a reproduced signal.

In the disk frame pulse separation circuit 72, the frame pulse (PBFP) of the reproduced video signal is separated and extracted and output as a 30 Hz pulse.

Therefore, the pulse generation circuit 25b outputs a 33.75 MHz clock, an 11.25 KHz synchronization signal (PBH), and a disk frame pulse (PBFP).
The signal is supplied to the write timing circuit 28 in FIG.

The signal processing of the signal processing circuit 25 is exactly the same in the signal processing circuits 26 and 27 in which internal blocks are omitted in FIG. 8. The reproduced signals outputted from these three channel signal processing circuits 25, 26 and 27 are supplied to circuits 29, 30 and 31 that perform time axis compression and time axis correction (hereinafter abbreviated as TBC circuit).

The write timing circuit 28 is a 3-channel clock.
Synchronization signal (PBH), reproduction frame pulse (PBFP)
), three channels of write control signals synchronized with the playback signal are generated and the TBC circuit 29 of each channel is generated.
．． 30 and 31.

The 8-bit playback signal supplied to the TBC circuit contains time axis fluctuations (jitter) caused by disk eccentricity, etc., so each playback signal is synchronized, that is, by the write control signal containing jitter. FIFO in TBC circuit
(not shown).

At the time of writing, the synchronization signal component and the like of the reproduced signal are deleted, and only the video signal component is written into the FIFO at the timing of the 33.75 MHz clock. Therefore, in the video signal format diagram of Fig. 7 f+b+, (C), the color difference signal for 960 clocks and the luminance signal for 1920 clocks, excluding the H synchronization and guard sections, of the lines from line numbers 13 to 374. written. Furthermore, the FIFO is FIFO for luminance signal and FIl'Q for color difference signal.
are provided separately. When reading from FIFO, the luminance signal is 1/2.2 and the color difference signal is 1/1.
．． 1, the luminance signal is sent to the Y processing circuit 32, and the color difference signal is sent to the PR/P processing circuit 33.
The three channels are connected by wired OR and supplied.

On the other hand, each player 21. , 22 and 23 are supplied to each 'rBC, and when a dropout occurs, that is, when DO5 is at a high level, the signal from [20]H to [EO]H is output from [20]H to [EO]H. Write the value of [FF]H instead of the 8-bit playback signal with the value.

The main controller 34 provides selection control signals (hereinafter abbreviated as SEL) to the 3-channel TBC circuits 29, 30, and 31 to control reading from each TBC circuit, and controls the Y processing circuit 32 and PR. /Pa
The readout order of three channels of reproduction signals supplied to the processing circuit 33 is controlled.

The read timing circuit 35 generates a read clock without time axis fluctuation (jitter) and supplies it to each TBC circuit. Therefore, the playback signal read out after being time-base compressed by this read clock is supplied to the Y processing circuit 32 and the PR/PR processing circuit 33 as a playback signal from which jitter has been removed. Furthermore, the sync trigger signal (SYNCTRG) output from the read timing circuit 35 is sent to the ROM in the Y processing circuit 32 and the PR/FB processing circuit 33.
A synchronization signal of the high-definition signal is applied to the ROM.
read out.

FIG. 11 is a block diagram of a portion of the Y processing circuit 32 that performs signal identification and signal replacement processing. In FIG. 11, a reproduction signal of a luminance signal (hereinafter abbreviated as reproduction Y) supplied from three channels of signal lines connected by wired OR is supplied to an FF detection circuit 73 and a latch circuit 74.

[FF]H in the reproduction Y supplied to the FF detection circuit 73
If the value is included, detect it and use [FF])
The output is held at a high level during the period l, and held at a low level during periods other than [FF]H. The latch circuit 74 is
A time adjustment operation is performed in which the supplied reproduction Y is delayed and transmitted to the a side of the selection circuit 75 by the time period in which the FF detection circuit 73 performs a detection operation and determines the output. The output of the FF detection circuit is given to the selection circuit 75, and when the level is low, the selection circuit 75 is connected to the a side, and the output of the latch circuit 74 is supplied to the line memory 76 and the next stage circuit (not shown). be done.

The line memory 76 delays the reproduction Y by one line and supplies its output to the b side of the selection circuit 75. When the output of the FF detection circuit 73 is at high level, the selection circuit 75
The reproduction Y of the previous line is supplied to the next stage circuit and line memory 76.

Therefore, when dropout occurs, D.

When S becomes high level, playback Y is [F F] H during that period.
Therefore, during the [FF]H period, that is, the dropout period, dropout compensation is performed by replacing the portion of the reproduction Y of the previous line during that period.

The circuit of FIG. 11 includes not only the Y processing circuit 32 but also the P R/
The reproduced color difference signals PR and P are also stored in the P B processing circuit 33.
Two circuits are provided for B and perform the same operation. Furthermore, P
The R/PB processing circuit 33 performs a process of returning the line-sequential color difference signal to line-sequential. This method is to perform an arithmetic mean of two consecutive lines of color difference signals PR and PB, and insert the average value between the two lines to compensate. Since video signals, especially color difference signals, have strong line correlation, such compensation can sufficiently reproduce the original high-definition color signal.

In this way, the playback signal with dropout compensation and line-sequential return processing of the color difference signal is the playback luminance signal Y.
1, the Y processing circuit 32 and the PR/PR processing circuit 3 are used as the three reproduced signals of the reproduced color difference signal PR and the reproduced color difference signal PB.
3 and output from D-A converter 36Y, 36R and 3
6B.

These three reproduced signals are the same as in FIG.

However, as described above, the even lines of the PR signal and the odd lines of the PB double signal are the arithmetic average of the preceding and succeeding line signals.

Further, when a character multiplexing command is given to the read timing circuit 35 from the main controller 34, the character data (DIS) is read from a character ROM (not shown) in the circuit.
P) is supplied to the Y processing 32 and PR/PB processing circuit 33, and is superimposed (superposed) on the reproduced signal and output.

The (digital) reproduction signals supplied to the D-A converters 36Y, 36R, and 36B are converted into analog reproduction signals, and the luminance signal Ya is passed through a 22MHz low-pass filter 37.
In Y, the color difference signals Pr and Pb are supplied to 11 MHz low-pass filters 37R and 37B. Unnecessary high-frequency components, noise, etc. are removed by each low-pass filter, and the result is output from the decoder. The output analog signal Ya.

P" and pb are color display indicators (not shown)
The high-definition signal is reproduced and displayed.

By the way, it goes without saying that for a set of three high-definition signal recording discs, it is essential that the combination is correct. Therefore, three players 21, 22.
In step 23, it is necessary to determine the type of disc at the start of disc performance. This determination is made in Figure 7 (at, (b), (C)), which shows the recorded signal in one frame.
This is done using the disc code recorded on the line number pads 10-12. FIG. 12 shows the HD-LD disc code format showing the contents of this disc code.

In this example, the disk used is CAV (constant angular velocity)
In FIG. 12, the lead-in area corresponds to 1200 frames on the inner circumference of the recording section.

The 11th line of this lead-in area contains a 2-byte read TOC (Table of Contents).
) contains data. FIG. 13 shows the contents of this TOC data, in which necessary TOC information is recorded in units of 300 bytes. There are 2 bytes of TOC in one frame, so one TOC in 150 frames.
It is a unit of information. In this classification of TOC data, the disc ID is an absolute number unique to the disc (including the front and back sides).

These TOC information is read by the player, and as described above, is communicated with the main controller 34 in V cycles through the serial interface to exchange the TOC information and other necessary information. The operation of the disk combination determination subroutine executed by the main controller 34 will be explained with reference to FIG.

When three discs have been loaded into each player, the main controller 34 moves to step S1 and waits to receive information that all three discs have been clamped, and when it determines that all clamping has been completed. searches for a lead-in frame and sends a command to read the disc ID (step S2). Upon receiving the disc ID, it is determined whether or not the ID number matches the ID number stored in the memory when the disc was played last time (step S3). When it is determined that the disc ID matches the previous ID, the disc ID is an absolute number unique to that disc, and since it is known from the previous performance that the combination of three discs is correct,
A frame 1 search command is transmitted to immediately start playback (performance) without reading other TOC information (step S4), and then the program moves to the main routine. Last ID
If it is determined that the numbers do not match, a command to read the TOC information of the three discs is sent to each player again (step S5). When the read TOC information is received from each player, the disc number and disc side data in the TOC information are compared and decoded.
It is determined whether the disc numbers and disc sides of the two discs match (step S6). When it is determined that the three disc numbers and disc sides match,
The disk ID numbers of these three disks are replaced with the old ID numbers in the memory and stored (step S7), and then the process proceeds to step S4, where a command to start playback (performance) is sent. If it is determined that the disc numbers and disc sides of only two of the three discs match, and the disc number or disc side of the remaining one disc does not match, the disc number and disc side of only two of the three discs match. Step S8 to send a tray open (eject) command
), sends a park (stop) command to the two players with matching discs installed (step S
9), proceed to the main routine. If it is determined that the disc numbers or disc sides of the three discs do not match, a tray oven (eject) command is sent to all three players (step 510), and the process moves to the main routine.

In addition to TOC information, information such as the operating status of the player is exchanged through communication between the main controller 34 and the player (controller) through a serial interface and a player disable signal line. Figure 15
This is the transmitted data that gives commands to the “TRAY” data is 0 for open, 1 for parked state, 2 for play.
state. The "ADRESS" data represents a frame number and is valid in the play state and instructs each player to play the transmitted frame.

Conversely, the main controller 34 receives the 15th
Received data as shown in Figure (b) arrives.

"ERROR" data is a positive number if the player's pickup is searching for the designated frame with respect to the designated frame number transmitted from the main controller 34, and is zero if it is on the designated frame. . Also, if the spindle lock is released, it becomes a negative number.

"ADRESS" in the 15th edition) represents the current position frame number of the player's pickup.

In the case of normal playback, the main controller 34 transmits the same frame number to each player.

When the frame number received from each player matches the transmitted frame number, the playback signal of that player is output, and for the players that do not match, the playback signal is used as a squelch.

The operation performed by the main controller 34 to monitor the player and perform squelch control will be described with reference to FIG. 15(C). The main controller 34, which has moved to the player monitoring subroutine, sets the designated frame Fl (Nl) and transmits it to each player (step 511), and also receives the current position frame FC from the player within the same V period (step 511). 12).The designated frame number corresponding to 20F is Fl+N-1) which was transmitted during the previous V cycle, so it is determined whether FC and Fl-1, match. (step 813).

If it is determined that they match, it is determined whether or not a disable signal has been received via the player disable lines i, j, k (step 514), and when it is determined that no disable signal has been received. is the player's “
5TATUS" information (step 515). This "5TATUS" information represents the servo status of the player's slider servo, tracking servo, spindle servo, and focus servo. In step S15, the servo status (status) is determined. When it is determined that the servo is normal, it moves to the main routine without squelching.When it is determined that the servo status is not normal, the level of abnormality differs depending on whether it is abnormal or so-called semi-normal. For example, in normal conditions, the slider and tracking servo are closed, but in the case of special playback that includes a jump operation such as a scan operation,
The tracking servo repeats close and oven. In step S16, it is determined whether or not such a jump motion is included, and when it is determined that a jump motion is included, the squelch is not performed and the process moves to the main routine. When it is determined that there is no jump operation, it is determined that there is an abnormality, and the 2-bit SEL signal in the main controller 34 is set to high level [11]a to perform squelch (step 517). When it is determined in step 813 that the specified frame and the current position frame do not match, step S
17, and when the disable signal is received in step S14, the process immediately moves to step S17 (without waiting for V cycle communication) and squelching is performed.

The SEL signal is given 2 bits (Sl, S2) to the TBC circuits 29, 30 and 31 in FIG.
0 core a, [01 core B [10] B.

[11] There are four types of binary values of B. Even if the combination of the three discs is correct, the main controller 34 must determine which of the three discs is installed in the three players.

In Figure 7 Kuta, Yama> (C), Y Pr or P
The number in parentheses following <b is the line number of the original high-definition number, and in the case of FIG. 7, the discs are recorded in the order of disc A-disc B-disc C. Therefore 3
In order to synthesize the channel playback signals in the correct order,
SEL of the TBC circuit supplied with the reproduction signal of disk A
Let the signal be [00]8. Let the SEL signals of the time axis compression circuits supplied with the playback signals of disks B and C be [01]a and [10]a, respectively. During squelch, the SEL signal is set to [11]B as described above.

The operation of the subroutine of the main controller 34, which plays the three players, reproduces the signals, jumps, and performs the search, will be explained according to FIG. 16.

The main controller 34 that has started the search operation proceeds to step 318 and sets the search target frame F. Next, the first player 21 and the second player 22
The tentative target frames FITT and F2TT are the target frame F. , and the provisional target frame F3□7 of the third player 23 is commanded to the current frame Fc (step 519). That is, the first player 21 and the second player 2
2 is given priority and jumped, and the third player 23 is given the current frame F. output a still image. Next, the SEL signals of the first player 21 and the second player 22 are set to [11]a (step 520) to perform squelch.

Next, it is waited to see whether the jump has ended, that is, whether the current frames FIC and F2C of the first and second players coincide with the target frame FTP (step 521).

If they match, the third player's provisional frame F 3T
T is commanded to the FTP (step 522), the squelch of the first and second players is canceled, and the third player is set to squelch (step 823). It waits to see if the third player has finished jumping (step 524), and when the jump has finished and the target frame has been reached, the third player's squelch is canceled (step 525). The search is terminated by canceling the squelch of all three players, and the process proceeds to the main routine.

The operation of each of the above players is illustrated as shown in the song in Figure 16. In FIG. 16, the movement of the reading points of the first and second players is A-CD, and the movement of the reading point of the third player is A-B-D.

In this embodiment, a still image is output, but each player may be made to perform playback. Main controller 34 at that time
In the operation, after step 21, a step of instructing the first and second players to play is performed, and step S22 is performed as F3T.
Let T = F IC = F 2C. Then, in the 16th episode), the movement of the reading points of the first and second players becomes A-C-D', and the movement of the reading point of the third player becomes A-C-D'.
-B'→D'.

The execution operation of the main processor 34 in another embodiment of such image display search will be explained according to FIG. 17 (J and <b>).
. An intermediate frame F is set between the two.

After setting FTP (step 526), F is set by calculation (step 527), and the main controller 34
commands a tentative target frame for each player (step 528). The first player has the current frame F. , the second player is commanded an intermediate frame F, and the third player is commanded a target frame FTF. Therefore the 17th
When the first player remains FC, the movement of the reading point becomes A-B, and the movement of the reading point of the second player becomes A-B.
C, and the third player's reading point moves from A to D. Therefore, the main controller causes only the first player to output still images. Therefore, the second and third players are set to squelch (step 529), and a wait is made to see if the second player reaches the intermediate frame F1 (step 530).
.

When F, is reached at tm in FIG. 17<b), the second player is made to output a still image of F, and the first player is instructed to jump to FTP (step 53).
1). Next, the second player's squelch is canceled and the first player is set to squelch (step 532), and a wait is made to see if the third player has reached F''rp (step 833).
. In the 17th game), the first player's reading point moves from BE to E, and the second player's reading point moves from C to E. When the third player reaches the FTP at time tb, the third player's squelch is canceled and the second player is made to squelch (step 534). Therefore, the third player outputs the target frame FTP as a still image, and the movement of the reading point becomes D-F. The movement of the reading points of the first and second brakers becomes E-F. Waiting for whether the first and second players have reached the target frame FTP (step 535);
When the second player reaches FTP at time tc, the squelches of the first and second players are canceled (step 536), the squelches of all three players are canceled, and the process moves to the main routine.

Comparing FIG. 16 (Ten and 17th appearance), it can be seen that by setting the intermediate frame F, the time tc for all three players to reach the target frame F''rp is shortened.

Next, a method of performing a scanning operation using three players will be explained according to FIG. Figure 18 (in J,
When the scanning operation is started, the main controller 34 sets the provisional target frame F. □ and number of frames to jump K
is set (step 537). Then the first and second
Player's interim frame F ITT + F 2TT
is commanded to the tentative target frame FTT, and the third player's tentative frame F3TT is the current frame F. command (
Step 538). Next, the first and second players are made to squelch (step 539).

In step S40, the first and second players
Wait to see if it has been reached. When it is determined that the FTT has been reached, a new provisional target frame F is created by adding the next jump frame number K to the FTT of the previously set provisional target frame.
TT is set (step 541). The third player's provisional frame F3↑T is then directed to this new provisional target frame FT↑ (step 542), and the first and second
The player's squelch is canceled and the third player is squelched (step 843). Next, the third player waits to see if the provisional target frame FTT has been reached (step 54).
4). When the FTT is reached, a new provisional target frame is set again (step 545), and the squelch of the third player is canceled (step 546). Next, press the command button (
In step 547), it is determined whether or not a scan end command has been received by an operation (not shown), and if it is determined not to have been received, the process moves to step 538 and the scan operation is repeated again. When it is determined that the scan end command has been received, the process moves to step 348 and instructs the same FTT to the three players (step 548), and waits to see if all three players have reached the FTT (step 548). Step 549
). When all three machines reach FTT, the process moves to the main routine. At this time, of course, all squelches are canceled. The above assumes forward scanning, but in the case of backward scanning, the value of K is made negative. (in Figure 18), the movement of the reading point of the third player is A-B, →B2→B
3..., and the movement of the reading points of the first and second players becomes A-C, -C2-C,...

Note that the player may be instructed to reproduce without instructing the player to output a still image. In that case, in FIG. 18(a), after step 38 and step S44, a step of instructing the third player to play is executed, and step S4
Next, the step of instructing the first and third players to play is executed.

In addition, in the above embodiment, the TBC circuits 29, 30, 31
Although the squelch operation is performed when the SEL signal is [111B], the circuit may be changed so that the level of these output signals is set to the highest level [FF]H.

In this way, in the case of special playback such as search, scan, etc., the dropout compensation circuit can be used to compensate by replacing the output signal of the player currently playing as the playback signal of the player currently jumping instead of squelch. That's what I do.

In FIG. 8, a synchronization/clock separation circuit 38 is for displaying a reproduction signal in synchronization with an external video.

The audio selection circuit 39 selects two audio channel signals from a total of six channels of audio signals output from the three players and supplied to the selection circuit 39 in accordance with a command (AUDIOSEL) from the main controller 34. and output it.

If the selected audio signal is lost for some reason, it can automatically switch to the audio signal of another channel.

Furthermore, in the case of scanning or searching, if the audio signal of the player that is playing back is selected, the audio signal will not stop and become silent even during scanning or searching.

Note that during the search operation, if audio is designated by operating a command button (not shown), the disc with the audio designation may be jumped with priority. In this case, in FIG. 16, after step 318, the step of setting the audio specified disc number to M is executed.

In addition, step S19 is performed as FMTT-FTT, FLT-
FC (L”FM).

As described in detail, the dropout compensation device for a video disc player performance device according to the present invention has the following features:
This makes it possible to display images without disturbance not only when dropouts occur, but also during special playback.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a recording system as an embodiment of the present invention, Fig. 2 is a waveform diagram of a high-definition signal, Fig. 3 is a block diagram of a part of the recording system of Fig. 1, and Fig. 4 (
a) is the arrangement diagram of the high-definition signal, and FIG. 4(b) is the first
FIG. 5(a) is a time chart of control signals occurring in the system shown in the figure. (b), (c), Figure 6 (a) is an arrangement diagram of signals in the system of Figure 1, Figure 6 (b) is a waveform diagram of signals in Figure 1, Figure 7 (a), (b) and (c) are arrangement diagrams of recording signals of three discs recorded by the recording system of FIG. 1, FIG. 8 is a block diagram of a reproduction system as an embodiment of the present invention, and FIG. Figures 10 and 11 are block diagrams of some of the circuits in Figure 8, Figure 12 is Figure 7(a),
(b) An arrangement diagram of the disc code in the recording signal shown in (C), FIG. 13 is a lead-in diagram of the disc code shown in FIG. 12, an arrangement diagram of TOC data,
Figure 5 (C), Figure 16 (a), Figure 17 (a), Figure 18
Figure (a) is a flowchart of a subroutine executed by the main controller in the playback system of Figure 8, and Figures 15 (a) and (b) are transmission and reception data of communication between the main controller and the player in the playback system of Figure 8. Tables showing Figure 16 (b), Figure 17 (b), Figure 18 (
b) is a graph showing the movement of the player's reading point in the playback system of FIG. 8; Explanation of symbols of main parts 1... High-definition signal source 2... Encoder 5... Timing pulse generation circuit 6Y...Y
Process circuit 6R...pa+process circuit 6B...PB process circuit 9...Selection circuit 12...PCM audio source 13...EFM encoder 21.22.23...Player 24... Decoder 29.30.31...Circuit for time axis compression and time axis correction 34...Main controller 39...Audio selection circuit 48...Dropout guarantee circuit 73...FF detection circuit 76... ...Line memory Figure 3 Applicant: Pioneer Corporation

Claims (3)

[Claims] (1) A performance means for reading a recorded signal from a video disk carrying a recorded signal including a video format signal consisting of a horizontal and vertical synchronization signal section and an information signal section, and demodulating the signal read by the performance means to format the video format signal. demodulating means for obtaining a signal; dropout detection means for detecting a dropout occurring in the read signal or the video format signal and generating a dropout detection signal; A dropout compensation device comprising a level shift means for forcibly maintaining a signal at a predetermined level, and a dropout compensation means for performing dropout compensation processing for a section where the video format signal is at the predetermined level, the dropout compensation device comprising: A dropout compensating device, comprising control means for emitting a signal, wherein the level shift means forcibly maintains the level of the video format signal at the predetermined level over the period in which the disable signal exists. (2) The dropout compensation device according to claim 1, wherein said control means issues said disable signal when said performance means is in a state other than a normal performance state. (3) The demodulating means emits a status indicating signal indicating normal, semi-normal, and abnormal operating status of the demodulating means, and the control signal generates the disable signal in response to the status indicating signal. 1. The dropout compensator according to 1.