JPH0437336A - Cross connection device - Google Patents

Abstract

PURPOSE:To adjust out of synchronism with a small capacity of memory even when a propagation delay time difference generated due to decentralized installation of devices is large by giving a timing signal to each data interface section while shifting the phase by the phase difference. CONSTITUTION:A synchronization adjustment section 4 controls a data interface section to allow it to fetch input data #1-#n with an initial in-phase timing signal and the data together with the timing signal are sent to time switches 21-2n. Each of the data #1-#n is subject to channel exchange according to the timing signal and the data #1-#n together with the timing signal are fed to a memory section 31 of a time division spatial switch section 3. The timing signal is returned to the synchronization adjustment section 4. The synchronization adjustment section 4 detects a phase difference of each timing signal and adjusts the phase of the timing signal corresponding to the phase difference so as to shift the timing signal given to each of data interface sections 11-1n. Thus, the capacity of the memory is enough to be small for the fine adjustment of the phase and the capacity is considerably reduced.

Description

[Detailed Description of the Invention] [Summary] A cross-connect device that switches channels of data input via a plurality of data interface units using a timing signal in a time switch unit and a time-division space switch unit, respectively. Regarding synchronization adjustment, the aim is to be able to adjust the synchronization deviation with a small capacity memory even if the propagation delay time difference that occurs due to distributed installation becomes large. First, the timing signal to each data interface section is Send out the phase as the same phase,
The phase difference of each timing signal sent to the memory section of the time-division space switch section via each data interface section and each time switch in sequence is detected, and the subsequent transmission to each data interface section is performed by the phase difference. A synchronization adjusting section is provided which allows each timing signal to be simultaneously applied to the memory section by shifting the phase of each timing signal and applying the timing signal.

Field of Industrial Application] The present invention relates to a cross-connect device, and more particularly, the present invention relates to a cross-connect device, in which data input through a plurality of data interface sections is channel-switched by a time switch section and a time division space switch section, respectively, using a timing signal. This relates to synchronization adjustment of cross-connect devices.

Cross-connect equipment that performs line switching in new synchronization, that is, high-order group synchronous networks, handles a very large number of line signals, and as a result, the equipment becomes large-scale and must be concentrated in one location and installed within the station building. Sometimes I can't do it.

Therefore, if the devices are installed at arbitrary locations within the station building, data synchronization will be out of sync due to the difference in propagation delay time caused by the difference in distance between the installation locations, so synchronization adjustment must be performed.

[Conventional technology]

FIG. 4 shows a conventionally used cross-connect device, and in the figure, 1n. 1n is a data interface section which inputs, for example, two input data #1n#2 respectively by timing signals; 2112.1n; , 30 are time switches 2+, 2 . , the time-division space switch unit further inputs each output data channel-exchanged by the timing signals accompanying those data, and the memory (elastic memory) 331n33□ and the time switch 2. ．． 2. 6, a data interface section 1.11, and a memory 33.6. ．． This is a reference timing generation circuit that provides a timing signal to 33□. In this circuit configuration, a time switch, a data interface section (output section), and a time division multiplexing/demultiplexing section subsequent to the time division space switch are omitted for simplicity of illustration.

In such a conventional example, the data interface section 1n. 1n or time switch 2. ．． 2. .

Due to the difference in the installation location, the distances between the data interface section and the reference timing generation circuit and between the data interface section and the time switch differ by, for example, several meters, as shown in the figure.

This creates a propagation delay time difference, and the data interface sections 1, . The timing signal to 1n is shifted, and the input data #1° #2 is time-switched 2. ．． 2. ．． The timing of the output will also be different.

Therefore, in order to adjust this kind of data synchronization deviation,
From the reference timing generation circuit 6 to the memories 33, . 33. The data input timing to the space switch 32 is made to coincide with the timing signal sent to the space switch 32.

[Problem to be solved by the invention]

In the case of the conventional example described above, when the system configuration is small-scale, the difference in distance between the timing signal lines to each data interface section and the transmission path from each data interface section to each time switch is small; The memory capacity required to absorb the phase shift caused by this is small.

However, in large-scale systems, if space considerations are taken into account on the user side, the system itself may be divided to some degree and installed within the station building, so differences in the distance of the transmission paths may be This poses a problem in that it can become very large, and as a result, a memory with a very large capacity must be used.

Therefore, the present invention provides a cross-connect device that performs channel switching of data input through a plurality of data interface sections using a timing signal at a time switch and a time-division space switch section, respectively, which are installed in a distributed manner. It is an object of the present invention to make it possible to adjust synchronization deviation with a small capacity memory even if the propagation delay time difference caused by the above becomes large.

[Means for Solving the Problem] The first section shows the principle of the cross-connect device according to the present invention. is sent out as the same phase, and each data interface section 1n to 1n
．． and detects the phase difference of the timing signal sent to the memory section 31 of the time division space switch section 3 via each of the time switches 2 to 27 sequentially, and sends only the phase difference to each data interface section 11 to 1fi. The above problem is solved by providing a synchronization adjustment section 4 that shifts the phase of subsequent timing signals so that the timing signals are simultaneously provided to the memory section 31.

[For production]

In FIG. 1, the synchronization adjustment unit 4 first sends timing signals to each of the distributed data interface units 1 to 1n with the same phase.

This timing signal causes the synchronization adjustment unit 4 to output the input data #.
1 to #n and send them to time switches 21 to 2 together with timing signals, respectively, and time switches 2 to 2. ~2
．． In l, each data #1 to # is processed according to the timing signal.
0 is channel-switched and sent to the memory section 31 of the time division space switch section 3 together with the timing signal.

The timing signals sent to this memory section 31 are sent to the synchronization adjustment section 4, respectively.

The synchronization adjustment unit 4 detects the phase difference between each timing from the timing signals returned in this manner.

Then, the phase of subsequent timing signals to each data interface unit II to 1o is adjusted to be shifted by the phase difference.

In that case, adjustment is performed so that each timing signal is applied to the memory section 31 at the same time.

Therefore, each time switch 21-2. ．． Data #1 to #n sent to the time-division space switch section 3 from the memory section 31
Since the signals are simultaneously input to the memory section 31, there is no need for memory capacity for time delay adjustment in the memory section 31.

[Embodiment] Fig. 2 shows an embodiment of the cross-connect device according to the present invention. In this embodiment, input data is synchronized as two systems #1 and #2 (n = 2). I'm making adjustments.

The synchronization adjustment section 4 shown in FIG. The synchronous timing signal generation circuit 43 shifts the reference timing based on the comparison result of the comparison circuit 42. Note that the memory section 31 in FIG. 1 corresponds to a combination of memories 31n and 31□, and the other configurations are the same as the configuration of the conventional example shown in FIG. 4, so a description thereof will be omitted.

The operation of the embodiment having such a configuration will be explained below with reference to the time chart of signals 1 to 2 of each section shown in FIG.

When the reference timing signal ■ generated from the reference timing generation circuit 41 is sent to the synchronous timing signal generation circuit 43, the synchronous timing signal generation circuit 43 generates the timing signals ■ and ■ synchronized with the reference timing signal ■ as data, respectively, as an initial state.・Interface parts 11 and 12
send to

The data interface units 11 and 12 that receive these timing signals ■ and ■ output timing signals ■ and ■ corresponding to the respective timing signals ■ and ■, respectively, and also output data ■ synchronized with the respective timing signals ■ and ■. (#l) and pig ■ (#2) are output.

These data ■ and ■ are given to the time switches 2 and 2z by timing signals ■ and ■, respectively, and are output as data [phase] and ■ that have been switched on the time axis (channel exchange), and are transmitted in a time-division space. Switch part 3
The data is sent to memories 31+ and 312 of .

At this time, the timing signals ■ and ■ are sent from the time switches 21 and 22 along with the data [phase] and ■ to the memory 31n.
The timing signals ■ and ■ are sent back to the input terminals of the memories 311 and 31 □ and are also sent to the phase comparator circuit 42 .

The phase comparison circuit 42 compares the timing signals ■ and ■ with the reference timing signal ■, and as shown in FIG. m, and transmits this comparison result to the synchronous timing signal generation circuit 43.

In response to this, the synchronous timing signal generation circuit 43 outputs the timing signal ■ n bits earlier than the reference timing signal ■, and outputs the timing signal ■ m bits earlier than the reference timing signal ■.

When input data #1 and #2 are sent to the memories 31 and 31□ in the same manner as above using the timing signals ■ and ■ generated from the synchronous timing signal generation circuit 43 in this way, the input data to the memories 311 and 31□ are Timing signal ■
and (2), data [phase] and (2) are in phase matching with the reference timing signal (2) as shown in FIG. 3, and are in a synchronized state.

After this, the phase comparison circuit 42 holds the timing start of the synchronous timing signal generation circuit 43 as before so that the timing signals ■ and ■ are outputted n and m bits earlier than the reference timing signal ■, respectively. let

In this way, the input data to the memories 31n and 31□ [
phase] and ■ and the timing signals ■ and ■ are synchronized and also match the reference timing signal ■, the memory 311
The time (delay time) for accumulating the data read from 312 and sent to the switch 32 via a multiplexing circuit (not shown) is almost unnecessary, and the memory capacity is sufficient only for fine adjustment. , capacity can be significantly reduced.

〔Effect of the invention〕

As described above, according to the cross-connect device according to the present invention, the timing signal is first sent from each data interface section to the memory section of the time division space switch section via each time switch in sequence, and is also sent to the memory section of the time division space switch section. By comparing the phase of the timing signal and detecting the phase difference based on the difference in the distance of the transmission path, the phase of each timing signal is shifted by the phase difference and is applied, so that each timing signal can be applied to the memory section at the same time. With this configuration, the memory section does not require a capacity for synchronization adjustment, and the circuit scale can be reduced.

In addition, compared to the method of determining the difference in the transmission path by measurement etc. in advance and always fixing it to a constant value to obtain synchronization, it is possible to automatically perform accurate synchronization adjustment according to the situation of the transmission path. becomes.

It is.

In FIG. 1, engineering, ~I, ... data interface section, 21-2
．． ,...Time switch, 3...Time division space switch section, 31...Memory section, 4...Same! tll adjustment section.

In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] Data input via a plurality of data interface units (1_1 to 1_n) are transferred to time switches (2_1 to 2_n) by each timing signal, respectively.
In a cross-connect device that performs channel exchange between n) and time-division space switch unit (3), first each data interface unit (1_1 to 1_n)
The timing signals are sent with the same phase to the memory section (31 ), and by shifting the phase of each subsequent timing signal to each data interface unit (1_1 to 1_n) by the phase difference and applying it to each data interface unit (1_1 to 1_n), each timing signal is A cross-connect device characterized in that it is provided with a synchronization adjustment section (4) for simultaneously providing signals to the section (31).