JPH0437188A - Wiring structure - Google Patents
Wiring structureInfo
- Publication number
- JPH0437188A JPH0437188A JP14499890A JP14499890A JPH0437188A JP H0437188 A JPH0437188 A JP H0437188A JP 14499890 A JP14499890 A JP 14499890A JP 14499890 A JP14499890 A JP 14499890A JP H0437188 A JPH0437188 A JP H0437188A
- Authority
- JP
- Japan
- Prior art keywords
- porous glass
- electroless plating
- plating solution
- plating
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000005373 porous glass Substances 0.000 claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 238000007772 electroless plating Methods 0.000 claims abstract description 16
- 238000007747 plating Methods 0.000 claims abstract description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052802 copper Inorganic materials 0.000 claims abstract description 7
- 239000010949 copper Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 12
- 230000003197 catalytic effect Effects 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 230000002378 acidificating effect Effects 0.000 abstract 1
- 230000007935 neutral effect Effects 0.000 abstract 1
- 230000006866 deterioration Effects 0.000 description 6
- 239000003513 alkali Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007654 immersion Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 150000002941 palladium compounds Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分骨〕
この発明は、めっきによる電気伝導体、特にめっきによ
り電気的に接続された厚膜抵抗体を搭載する配線構造体
に関Tるものである。[Detailed Description of the Invention] [Industrial Application] The present invention relates to a wiring structure equipped with a plated electrical conductor, particularly a thick film resistor electrically connected by plating. be.
第2図1第8図は〜電子通信学会OPM 86−68(
1986年)P29−84に記載された従来の配線構造
体の断面図である。図において、】は基板、例えばアル
ミナセラミック基板、2はめつき触媒作用を有する多孔
質カラス、4はこの多孔質カラスと直接に接触する、銅
を主体とする無電解めっきから析出する金属めっき、例
えば銅めっき、5は厚膜抵抗体である。Figure 2 1 Figure 8 ~ Institute of Electronics and Communication Engineers OPM 86-68 (
1986) is a sectional view of a conventional wiring structure described in P29-84. In the figure, ] is a substrate, e.g., an alumina ceramic substrate, 2 is a porous glass having a catalytic action for plating, and 4 is a metal plating deposited from electroless plating mainly composed of copper, which is in direct contact with the porous glass, e.g. Copper plating, 5 is a thick film resistor.
次に製造工程について説明する。はう珪酸鉛系ガラス粉
末、パラジウム化合物、有機溶媒を適量含有するペース
ト状混合物(以下活性ペーストと言う)を基板1上にス
クリーン即刷法にて形成する。適時乾燥後に大気中65
0℃にて焼成する○はう珪酸鉛系ガラスは溶融するから
、これら工程により基板1上に網目構造の多孔質ガラス
2が形成される。この多孔質カラス2はパラジウムを含
有するため、めっき触媒作用を有する。これら工程の後
、有機材料例えばポリイミドからなるレジスト層6を形
成し、必要に応じてパターンを形成する。その後嗣を主
体とするPH12〜18の無電解めっき液に浸漬するこ
とにより、亀気伝導体4P形成する。Next, the manufacturing process will be explained. A paste-like mixture (hereinafter referred to as active paste) containing appropriate amounts of lead silicate glass powder, a palladium compound, and an organic solvent is formed on the substrate 1 by a screen printing method. 65 in the atmosphere after timely drying
Since the lead silicate glass fired at 0° C. is melted, a porous glass 2 having a network structure is formed on the substrate 1 through these steps. Since this porous glass 2 contains palladium, it has a plating catalytic effect. After these steps, a resist layer 6 made of an organic material such as polyimide is formed, and a pattern is formed if necessary. Thereafter, the conductor 4P is formed by immersing it in an electroless plating solution with pH 12 to 18 mainly containing heirlooms.
第8図は、導体材料と電気的に直接に接続された厚膜抵
抗体5を塔載する配線構造体の断面図である。FIG. 8 is a sectional view of a wiring structure mounting a thick film resistor 5 that is directly electrically connected to a conductive material.
製造工程は、基板1上に酸化ルテニウムを主成分とする
厚膜抵抗体をスクリーン印刷法にて付与後焼成する。そ
の後、活性ペースト2、レジスト層6、電気伝導体4B
、上記と同じ方法にて形成する。In the manufacturing process, a thick film resistor mainly composed of ruthenium oxide is applied onto the substrate 1 by screen printing, and then fired. After that, active paste 2, resist layer 6, electrical conductor 4B
, formed by the same method as above.
基板1及び厚膜抵抗体5と、を人伝導体4との密着は、
網目構造の多孔質ガラス2の内部に電気伝導体を形成し
ている鋼粒子が入り込み、アンカー効果によって確保し
ている。The close contact between the substrate 1 and the thick film resistor 5 and the human conductor 4 is as follows.
Steel particles forming an electrical conductor enter the porous glass 2 having a network structure, and are secured by an anchor effect.
従来の構造では、多孔質ガラス2が、PH12〜18の
無電解めっき液に浸漬中において、多孔質ガラス2の表
面の一部がアルカリによって変質劣化し、その後のヒー
トサイクル試験等により多孔質ガラスの一部にマイクロ
クランクが発生し・基板・及び厚膜抵抗体と、電気伝導
体の密着強度を低下させる間曜点があった。In the conventional structure, while the porous glass 2 is immersed in an electroless plating solution with a pH of 12 to 18, a part of the surface of the porous glass 2 deteriorates due to alkali, and a subsequent heat cycle test etc. There were some spots where micro-cranks occurred in some parts of the board, reducing the adhesion strength between the substrate, the thick film resistor, and the electrical conductor.
この発明は、上記のような問題点を解決するためになさ
れたもので、多孔質ガラスの表面の変質を防止すること
によりヒートサイクル試験等による密着強度の低下を防
いだ配S構造体を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and it is possible to obtain an S-distributed structure that prevents deterioration of adhesion strength due to heat cycle tests etc. by preventing deterioration of the surface of porous glass. The purpose is to
この発明に係る配線構造体は、多孔質ガラスと電気伝導
体の間に、PII9.5以下の無電解めっきかう析出す
るインサート層を形成したものである。The wiring structure according to the present invention has an insert layer deposited by electroless plating with a PII of 9.5 or less between the porous glass and the electrical conductor.
この発明による配線構造体は・多孔質ガラス上に、PH
9,5以下の無電解めっき液から析出されるインサート
層を形成することにより、多孔質ガラスをめっき膜で覆
うこととなり、そのため、その後の工程であるPH12
〜18の無電解めっき液に浸漬することによる多孔質カ
ラスの表面の変質劣化を防ぐことができる。The wiring structure according to the present invention has PH on porous glass.
By forming an insert layer deposited from an electroless plating solution of 9.5 or less, the porous glass is covered with a plating film, and therefore the subsequent step of PH12
It is possible to prevent deterioration and deterioration of the surface of porous glass due to immersion in the electroless plating solution of ~18.
以下この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第111において、Iは基板、2はめつき析出触媒作用
を有する多孔質ガラス、3はPH9,5以下の無電解め
っき液から析出される金属めっきのインサート層、4は
銅を主体とする電気伝導体、5は酸化ルテニウムを主体
とする厚膜抵抗体、6は有機材料からなるレジスト層で
ある。In No. 111, I is a substrate, 2 is a porous glass having a plating deposition catalytic action, 3 is a metal plating insert layer deposited from an electroless plating solution with a pH of 9.5 or less, and 4 is an electrically conductive layer mainly composed of copper. 5 is a thick film resistor mainly made of ruthenium oxide, and 6 is a resist layer made of an organic material.
次に製造工程について説明する。従来例と同じく、基板
1上に厚膜抵抗体5と、網目!ll造をもつ多孔質ガラ
ス2と、レジスト層6を形成した後に、PH9,5以下
の無電解めっき液、例えば中性もしくは酸性の無電解N
1めつき液に浸漬することにより、多孔質カラス2上に
インサート層3を形成する〇その後、pH12〜18の
無電解めっき液に浸漬することにより銅を主体とする電
気伝導体4を形成する。Next, the manufacturing process will be explained. As in the conventional example, there is a thick film resistor 5 on the substrate 1 and a mesh! After forming the porous glass 2 having a structure of
1. An insert layer 3 is formed on the porous glass 2 by immersion in a plating solution. After that, an electrical conductor 4 mainly made of copper is formed by immersion in an electroless plating solution with a pH of 12 to 18. .
この発明における配S構造体は、多孔質ガラス2が、P
H9,5以下の無電解めっき液から析出されるインサー
トNll3によって覆われるため、その後工程のPH1
2〜18の無電解めっき液に浸漬することによってうけ
ていた多孔質カラス表面のアルカリによる変質劣化を防
ぐことができる。In the S distribution structure in this invention, the porous glass 2 is P
Because it is covered with the insert Nll3 deposited from the electroless plating solution with H9.5 or less, the PH1 in the subsequent process is
It is possible to prevent the deterioration of the porous glass surface caused by alkali by immersing it in the electroless plating solutions No. 2 to 18.
以上のように、この発明によれば、多孔質ガラスとPH
12〜18の無電解めっき液から析出される電気伝導体
の間にPH9,5以下の無電解めっき液から析出される
インサート層を挿入することによって、多孔質ガラス表
面が受けるアルカリによる変質劣化3防止することが可
能となり、耐ヒートサイクル性等、信噌性の良好な配l
s構造体を得ることができる。As described above, according to the present invention, porous glass and PH
By inserting an insert layer deposited from an electroless plating solution with a pH of 9.5 or less between the electrical conductors deposited from the electroless plating solution of Nos. 12 to 18, the porous glass surface undergoes alteration and deterioration due to alkali 3. It is now possible to prevent
s structure can be obtained.
第1図は、本発明の一実施例による配S構造体の断面図
、第2図、第8図は、従来の配線構造体の断面図である
。
図中、1は基板、2は多孔質カラス、3はインサート層
、4は銅を主体としたIE電気伝導体5は厚膜抵抗体、
6はレジスト層である。
なお図中同一符号は同一または相当部分を示す。FIG. 1 is a sectional view of an S distribution structure according to an embodiment of the present invention, and FIGS. 2 and 8 are sectional views of conventional wiring structures. In the figure, 1 is a substrate, 2 is a porous glass, 3 is an insert layer, 4 is an IE electrical conductor mainly made of copper, and 5 is a thick film resistor.
6 is a resist layer. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
を有する多孔質ガラスと、めつきにより形成された銅を
主体とする電気伝導体とを有する配線構造体において、
上記多孔質ガラスと直接に接触する導体材料がPH9.
5以下の無電解めつきから析出する金属めつきからなる
インサート層であり、かつ、このインサート層が上記銅
を主体とし、めつきにより形成された電気伝導体と電気
的に接触していることを特徴とする配線構造体。In a wiring structure having at least a substrate, porous glass having a plating deposition catalytic action on the substrate, and an electrical conductor mainly made of copper formed by plating,
The conductive material that comes into direct contact with the porous glass has a pH of 9.
It is an insert layer consisting of metal plating deposited from electroless plating of 5 or less, and this insert layer is mainly made of the above copper and is in electrical contact with the electrical conductor formed by plating. A wiring structure characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14499890A JPH0437188A (en) | 1990-06-01 | 1990-06-01 | Wiring structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14499890A JPH0437188A (en) | 1990-06-01 | 1990-06-01 | Wiring structure |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0437188A true JPH0437188A (en) | 1992-02-07 |
Family
ID=15375094
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14499890A Pending JPH0437188A (en) | 1990-06-01 | 1990-06-01 | Wiring structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0437188A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017155255A (en) * | 2016-02-29 | 2017-09-07 | 株式会社村田製作所 | Forming method of metal layer |
-
1990
- 1990-06-01 JP JP14499890A patent/JPH0437188A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017155255A (en) * | 2016-02-29 | 2017-09-07 | 株式会社村田製作所 | Forming method of metal layer |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB1424642A (en) | Layer circuits | |
JPH04256306A (en) | Chip type solid electrolytic capacitor with fuse and manufacture thereof | |
JPH0437188A (en) | Wiring structure | |
JPS62196899A (en) | Multilayer device and manufacture of the same | |
US4898805A (en) | Method for fabricating hybrid integrated circuit | |
US4946709A (en) | Method for fabricating hybrid integrated circuit | |
JPH10340625A (en) | Conductive paste, its manufacture, and printed wiring board using the paste | |
JPS6352796B2 (en) | ||
JP2000340596A (en) | Manufacture of semiconductor device | |
JP3688889B2 (en) | Wiring board manufacturing method | |
JP2685890B2 (en) | Electrode forming method for chip parts | |
EP0232026A2 (en) | Multilayer systems and their method of production | |
JPH0258893A (en) | Thick film integrated circuit and its manufacture | |
JPS61121389A (en) | Ceramic wiring board | |
JPS63186492A (en) | Manufacture of circuit board | |
JP4646373B2 (en) | Wiring board and manufacturing method thereof | |
JPS5938314B2 (en) | Method of plating thick film paste | |
JPS6194394A (en) | Manufacture of thin film circuit board | |
JPH03109793A (en) | Manufacture of wiring circuit board with resistor | |
JPH0385795A (en) | Manufacture of multilayer interconnection ceramic board | |
JPH03175690A (en) | Ceramic printed wiring board | |
JP2002100705A (en) | Wiring substrate and manufacturing method therefor | |
JPH05275832A (en) | Thick film circuit board | |
JPH043991A (en) | Formation of wiring conductor of thick film integrated circuit | |
JPS63186496A (en) | Manufacture of circuit board |