JPH04370952A - Signal transmission circuit - Google Patents

Abstract

PURPOSE:To prevent the breaking of a MOS integrated circuit with an output buffer even when a MOS integrated circuit with an input buffer reaches no supply with a power source by monitoring a supply power source to the input buffer and brining the output side to a high impedance state when the power source is abnormal. CONSTITUTION:A MOS integrated circuit 2 and a MOS integrated circuit 6 are connected through a signal conductor 100 by using an output tri-state buffer 3 for the MOS integrated circuit 2 and an input buffer 7 for the MOS integrated circuit 6. A power source monitor circuit 200 is driven by the same power source 5 as the MOS integrated circuit 6, and power-source interruption information is output to a signal conductor 201 when an output from the power source 5 is lowered up to voltage, by which the MOS integrated circuit 6 is not operated normally. When power-source interruption information is transmitted over the enable terminal of the output tri-state buffer 3 of the MOS integrated circuit 2 through the power-source interruption signal conductor 201, the output tri-state buffer 3 of the MOS integrated circuit 2 is controlled under the state of high impedance at that time.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD The present invention relates to a signal transmission circuit, and in particular to a MOS (Metal Oxide S) used in a transmission device, etc.
emiconductor) It relates to a circuit that protects the output buffer of an integrated circuit.

0002

[Prior Art] In general, the output buffer of a MOS integrated circuit is equipped with a mechanism (for example, a current limiting device) to suppress the current flowing through the output buffer in order to avoid device destruction of the MOS integrated circuit itself when an excessive current flows. (e.g., incorporating a limiting resistor) is adopted. Further, the input buffer of the MOS integrated circuit uses a mechanism (for example, incorporating a diode clamp circuit for input signals) to protect the input circuit from electrostatic damage, latch-up, and the like.

The conventional circuit will be explained with reference to FIG.

In the figure, communication between MOS integrated circuit 2 and MOS integrated circuit 6 is performed by connecting output buffer 9 of MOS integrated circuit 2 and input buffer 7 of MOS integrated circuit 6. Further, the MOS integrated circuit 2 is supplied with power by the power supply 1, and the MOS integrated circuit 6 is supplied with power by the power supply 5.

In such a configuration, when a predetermined power supply is applied to both the MOS integrated circuit 2 and the MOS integrated circuit 6, the output buffer 9 of the MOS integrated circuit 2 and the MOS
It performs electrically normal operation with the input buffer 7 of the integrated circuit 6. However, especially when the output of the power supply 5 of the MOS integrated circuit 6 drops or the power supply is cut off, the power supply of the MOS integrated circuit 6 and the input buffer 7 of the MOS integrated circuit 6 are equivalently connected by a diode. become a state. As a result, the input buffer 7 of the MOS integrated circuit 6 enters a low impedance state, so that the input buffer 7 of the MOS integrated circuit 6 becomes
A large current flows in the direction of the OS integrated circuit 6. In this case, M
The output buffer 9 of the OS integrated circuit 2 is damaged or the MO
Even if the output buffer 9 of the S integrated circuit 2 is current-limited, the maximum rated current continues to flow, and eventually the MO
There is a risk that the output buffer 9 of the S integrated circuit 2 may be destroyed.

As described above, in conventional circuits, when the input buffer and output buffer between MOS integrated circuits having different power supplies are directly connected, when the power is no longer supplied to the MOS integrated circuit having the input buffer, However, the disadvantage is that the MOS integrated circuit having the output buffer is destroyed.

[0007]

OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to provide a signal transmission circuit that can prevent destruction of a MOS output buffer.

[0008]

[Structure of the Invention] A signal transmission circuit according to the present invention includes a MOS output buffer, a MOS input buffer that receives an output signal of this output buffer, a clamp circuit that protects this input buffer, and supplies power to the input buffer. a power supply circuit; a monitoring circuit for monitoring power supply to the input buffer; and control for placing the output buffer in a high impedance state when an abnormality in the power supply is detected by the monitoring circuit. It is characterized by having a circuit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram of a signal transmission circuit according to the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals.

In the figure, the connection between the MOS integrated circuit 2 and the MOS integrated circuit 6 is made via a signal line 100 using the output tri-state buffer 3 of the MOS integrated circuit 2 and the input buffer 7 of the MOS integrated circuit 6. .

The power supply monitoring circuit 200 is driven by the same power supply as the power supply 5 of the MOS integrated circuit 6, and the power supply monitoring circuit 200 monitors a decrease in the output of the power supply 5, and the output of the power supply monitoring circuit 200 is a power-off signal. Via line 201, MO
It is connected to the enable terminal of the output tri-state buffer 3 of the S integrated circuit 2.

Note that the MOS integrated circuit 2 is supplied with power by the power supply 1, and the MOS integrated circuit 6 is supplied with power by the power supply 5.

In such a configuration, when a predetermined power is applied to both the MOS integrated circuit 2 and the MOS integrated circuit 6, the output of the power supply monitoring circuit 200 is stopped, and the MOS integrated circuit is outputted via the power-off signal line 201. The enable terminal of the output tristate buffer 3 of the circuit 2 becomes enabled. As a result, electrically normal operation is performed between the output tristate buffer 3 of the MOS integrated circuit 2 and the input buffer 7 of the MOS integrated circuit 6.

In this state, the configuration is similar to that of the interface between the MOS integrated circuit 2 and the MOS integrated circuit 6 described in the conventional circuit (FIG. 2).

Here, since the power supply monitoring circuit 200 is driven by the same power supply 5 as the MOS integrated circuit 6, if the output of the power supply 5 drops to a voltage that does not allow the MOS integrated circuit 6 to operate normally, the power supply monitoring circuit 200 sends a signal indicating power-off information. Output to line 201. When power-off information is given to the enable terminal of the output tri-state buffer 3 of the MOS integrated circuit 2 via the power-off signal line 201, the output tri-state buffer 3 of the MOS integrated circuit 2 is controlled to a high impedance state at that point. be done.

As a result, the signal line 100 becomes a high impedance state, so that even if the input buffer 7 of the MOS integrated circuit 6 becomes a low impedance state as described in the conventional circuit, the signal line 100 becomes a high impedance state. The current no longer flows into the MOS integrated circuit 2.
It is possible to prevent the output tri-state buffer 3 from being destroyed.

Here, the power supply monitoring circuit 200 is operated by the power supply from the power supply 5, and uses, for example, a ground level signal as a power failure detection output, and outputs a ground level signal when the power supply 5 is normal. If the output of the power supply 5 drops in voltage or the power is cut off, the output of the power supply detection circuit 200 may be opened. As a result, the MOS integrated circuit 2
An abnormality in the power supply of the MOS integrated circuit 6 can be detected on the side. Furthermore, it is clear that a power supply dedicated to the power supply monitoring circuit 200 may be provided.

[0019]

As explained above, the present invention monitors the power supply to the input buffer and sets the output side to a high impedance state when the power supply is abnormal, thereby improving the output between MOS integrated circuits driven by different power supplies. MO with an input buffer in a configuration where the buffer and input buffer are directly connected
Even if the power supply to the S integrated circuit is cut off, the MOS integrated circuit having the output buffer can be prevented from being destroyed.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a signal transmission circuit according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a conventional signal transmission circuit.

[Explanation of symbols]

1,5 Power supply 2,6 MOS integrated circuit 3 Tri-state buffer 7 Input buffer 200 Power supply monitoring circuit

Claims (1)

[Claims] 1. A signal transmission circuit comprising a MOS output buffer, a MOS input buffer that receives an output signal of the output buffer, a clamp circuit that protects the input buffer, and a power supply circuit that supplies power to the input buffer. characterized by comprising a monitoring circuit that monitors the power supply to the input buffer, and a control circuit that sets the output buffer to a high impedance state when an abnormality in the power supply is detected by the monitoring circuit. signal transmission circuit.