JPH04369985A - Video signal recorder - Google Patents

Abstract

PURPOSE:To simplify the interpolation processing for head clogging even to a recorder recording video data compressed by an efficient encoding by allocating each block to a plurality of heads with the least correlation of the location on a two-dimensional block. CONSTITUTION:An A/D converter 1 outputs digital video data to a data divider 2. The data divider 2 stores four frame of the digital video data from the A/D converter 1, divides a screen into blocks for each picture element, allocates each block to two heads, and outputs the block data allocated to each head to efficient encoders 3 and 4 by each head. When each divided block is allocated to a first head 11 and to a second head 12, it is allocated to the data divider 2 so that each block a hound's-tooth check, dispersing the error. The polarization of data is prevented while interleaving each allocated block using M system.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal recording apparatus for dividing a video signal into blocks, performing high-efficiency encoding processing on each block, and recording the resulting data on a recording medium such as a magnetic tape.

0002

[Prior Art] In digital recording and reproducing apparatuses that digitize analog video and audio signals and record them on recording media such as magnetic tapes, magnetic disks, and optical disks, and that reproduce the recorded data, errors due to burst errors are detected. It is common to perform interleaving to distribute the information. FIG. 14 shows, for example, a conventional composite digital VT described in Broadcasting Technology, July 1986 issue.
It is a figure showing the composition of R. In the figure, 50 is a video A/D that converts analog video data into digital data.
A video A/D converter 50 outputs digital video data to an outer code error correction encoder 52. The outer code error correction encoder 52 adds an outer code to the digital video data and outputs it to the interleave circuit 54 . The interleaving circuit 54 interleaves the input video data and outputs the interleaved data to the data mixer 56 . On the other hand, 51 is an audio A/D converter that converts analog audio data into digital data, and the audio A/D converter 5
1 outputs digital audio data to the outer code error correction encoder 53. The outer code error correction encoder 53 adds an outer code to the digital audio data and outputs it to the interleave circuit 55 . The interleave circuit 55 interleaves the input audio data and outputs the interleaved data to the data mixer 56 . The data mixer 56 synthesizes the video data interleaved by the interleave circuit 54 and the audio data interleaved by the interleave circuit 55, and then outputs the synthesized data to the inner code error correction encoder 57. The inner code error correction encoder 57 adds an inner code to the data combined by the data mixer 56,
Output to modulator 58. The modulator 58 records and encodes the error correction encoded data. The recorded encoded data is amplified by a recording amplifier 59 and then sent to a magnetic head 6.
0 is recorded on a magnetic tape (not shown).

[0003] Reference numerals 61 to 70 in the figure indicate structural members on the regeneration system side. Data reproduced from the magnetic tape by the magnetic head 60 is amplified by a head amplifier 61 and then input to a demodulator 62 . The demodulator 62 records and decodes the reproduced data, and sends the recorded and decoded data to the inner code error correction decoder 6.
Output to 3. The inner code error correction decoder 63 performs error correction using the inner code, and then outputs the result to the data switcher 64. The data switcher 64 separates the reproduced data into video data and audio data, and outputs the separated video data to a deinterleaving circuit 65 and the separated audio data to a deinterleaving circuit 66, respectively. The deinterleave circuit 65 is
The separated video data is deinterleaved and returned to the original arrangement, and is output to the outer code error correction decoder 67. The outer code error correction decoder 67 performs error correction on the video data using the outer code and outputs it to the video D/A converter 69. The video D/A converter 69 converts the reproduced video digital data into an analog signal and outputs it. On the other hand, the deinterleaving circuit 66 deinterleaves the separated audio data to restore the original arrangement and outputs it to the outer code error correction decoder 68. The outer code error correction decoder 68 performs error correction on the audio data using the outer code and outputs it to the audio D/A converter 70 . The audio D/A converter 70 converts the reproduced audio digital data into an analog signal and outputs the analog signal.

Next, the operation will be explained. In the recording system, the analog video signal and the analog audio signal are respectively recorded as video A.
After being digitized by a /D converter 50 and an audio A/D converter 51, it is synthesized simultaneously with error correction encoding, and the synthesized data is recorded and encoded by a modulator 58, and then recorded by a recording amplifier 59.
Recording is performed by the magnetic head 60 via the magnetic head 60. In the error correction encoding, outer codes are added to the video data and audio data by outer code error correction encoders 52 and 53, respectively, and the data to which the outer codes are added are interleaved by interleave circuits 54 and 55, respectively. After processing, the data is combined by a data mixer 56, and an inner code is added by an inner code error correction encoder 57. As a result, cross-interleaving processing is performed in which error correction parity words are added before and after interleaving. In the reproduction system, the digital data reproduced by the magnetic head 60 is first sent to the demodulator 6 via the head amplifier 61.
2, and the inner code is corrected by the inner code error correction decoder 63. Next, the decoded output is separated into video data and audio data by a data switcher 64, and deinterleaved circuits 65 and 66 respectively.
Deinterleave processing is performed to restore the original arrangement, and outer code error correction decoders 67 and 68 correct the outer code.
Analog signals are reproduced through A/A converters 69 and 70.

[0005] The interleave method in a digital recording/reproducing apparatus having the above configuration is a method in which pixels are first replaced within a scanning line, and then one pixel is taken out from each scanning line and rearranged, and generally burst errors etc. This is done for the purpose of distributing errors during decoding for concentrated errors. Specifically, it is performed as follows. Pre-shuffling the video data for each horizontal line,
Main shuffle the pre-shuffled data. Pre-shuffling is a process that cyclically shifts the sample sequence of video data by k samples for each horizontal line, and main shuffling considers the allowable size of burst errors and detects burst errors that occur within this size. When deshuffling is performed to restore the original time series, the shuffling is used to arrange samples with errors due to burst errors on the playback screen according to a predetermined rule.

[0006]

[Problems to be Solved by the Invention] Conventional interleaving methods aim at error dispersion for burst errors of a certain size within a specific range due to scratches on the magnetic tape, etc. However, with this method, head clogging occurs. If a burst error with a size larger than a certain range occurs, continuous errors are likely to occur and effective interpolation processing is difficult. Incidentally, in recent years, in order to be compatible with digital VTRs and the like, a method of compressing and recording video data by subjecting the video data to high efficiency encoding processing has been widely used. In this case, the screen is divided into several blocks in advance, and high-efficiency encoding processing is performed on each block. When data is processed block by block in this way, consecutive errors become very noticeable.

[0007] In such high-efficiency encoding processing,
Since compression is performed using image correlation, if sample-based interleaving is performed as in the past, the image correlation will be lost and large compression will not be possible. Therefore, it is necessary to perform interleaving in units of blocks. Furthermore, when high-efficiency encoding processing is performed on a block-by-block basis, the amount of information is not necessarily constant because the encoding is adaptive to the image content. Therefore, in order to record within a specific track, it is necessary to estimate the total amount of information in order to control the amount of information in blocks by variable length encoding.

The present invention has been made in view of the above circumstances, and is suitable for recording devices that compress and record video data using high-efficiency encoding. It is an object of the present invention to provide a video signal recording device that facilitates interpolation processing for burst errors caused by clogging or the like.

Another object of the present invention is to be able to disperse bias in the amount of information due to image correlation even in a recording device that compresses and records video data using high-efficiency encoding, so that it can be efficiently recorded on a storage medium. It is an object of the present invention to provide a video signal recording device that allows high performance and has little deterioration in image quality.

0010

[Means for Solving the Problems] A video signal recording device according to the first invention of the present application is arranged so that when each divided block is assigned to a plurality of magnetic heads, the correlation between block positions is minimized in two-dimensional directions. For example, each block is allocated to two magnetic heads in a staggered pattern.

The video signal recording device according to the second invention of the present application allocates each divided block to a plurality of recording heads so that the correlation between block positions is minimized in two-dimensional directions, and also assigns each divided block to a plurality of recording heads. The present invention is characterized in that it is configured to perform interleaving such as randomization with different random patterns by using different M sequences for each allocated block.

0012

In the first aspect of the invention, each block is allocated to a plurality of heads in such a way that the correlation between the two-dimensional block positions is minimized, thereby dispersing errors caused by head clogging. For example, the allocation pattern of blocks to two heads is a houndstooth pattern. In this way, even if one head becomes clogged and incorrect data is recorded, interpolation processing can be performed based on nearby accurate data recorded by the other head.

In the second invention, in addition to the first invention, blocks allocated to a plurality of heads are further interleaved using different M sequences. In this way, the bias in the amount of information due to image correlation is dispersed, and data is efficiently recorded on the recording medium.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to drawings showing embodiments thereof.

(First Embodiment) FIG. 1 is a block diagram showing the configuration of a first embodiment of the video signal recording apparatus of the present invention. In the figure, numeral 1 denotes an A/D converter that converts input analog video data into a digital signal, and the A/D converter 1 outputs digital video data to a data divider 2. The data divider 2 stores four frames of digital video data from the A/D converter 1, divides the screen into blocks for each plurality of pixels, assigns each block to two heads, and divides the block data assigned to each head. is output to high-efficiency encoders 3 and 4 for each head. The high efficiency encoder 3 compresses the video data for the first head and outputs the compressed data to the error correction encoder 5. The error correction encoder 5 performs error correction on the video data and outputs it to the modulator 7. The modulator 7 records and encodes the error correction encoded video data and outputs it to the recording amplifier 9. The data amplified by the recording amplifier 9 is recorded on the magnetic tape 80 by the first head 11, which is a recording member mounted on the rotating drum 90. On the other hand, the high efficiency encoder 4
The video data for the head is compressed and the compressed data is output to the error correction encoder 6. The error correction encoder 6 performs error correction on the video data and outputs it to the modulator 8. The modulator 8 records and encodes the error correction encoded video data and outputs it to the recording amplifier 10. recording amplifier 10
The amplified data is recorded on the magnetic tape 80 by the second head 12, which is another recording member mounted on the rotating drum 90.

Next, the configuration of the reproduction system will be explained. The data reproduced from the magnetic tape 80 by the first head 11 is amplified by the head amplifier 13 and then by the demodulator 15.
is input. The demodulator 15 records and decodes the input reproduced data and outputs it to the error correction decoder 17. The error correction decoder 17 performs error correction on the reproduced data and outputs it to the high efficiency decoder 19. The high-efficiency decoder 19 expands the reproduced video data and outputs it to the data synthesizer 21. On the other hand, the data reproduced from the magnetic tape 80 by the second head 12 is amplified by the head amplifier 14, and then
The signal is input to the demodulator 16. The demodulator 16 records and decodes the input reproduced data and outputs it to the error correction decoder 18. The error correction decoder 18 performs error correction on the reproduced data and outputs it to the high efficiency decoder 20. The high-efficiency decoder 20 expands the reproduced video data and outputs it to the data synthesizer 21. The data synthesizer 21
The reproduced data originating from the head 11 and the reproduced data originating from the second head 12 are combined and output to the interpolator 22 and the D/A converter 23. The interpolator 22 performs interpolation processing on the video data when error correction cannot be performed, and outputs the processed data to the D/A converter 23. The D/A converter 23 converts digital video data into an analog signal and outputs it.

FIG. 2 shows the data divider 2 and data synthesizer 2.
1 is a diagram showing the configuration of FIG. In the figure, reference numeral 30 denotes a 4-frame memory on the recording side that stores video data for 4 frames. Video data is input to the 4-frame memory 30 from an input terminal 31 and written in accordance with the address from the write address counter 32. Further, reading of data from the 4-frame memory 30 is performed by dividing the address generated by the read address counter 33 into a first output and a second output according to the address after being interleaved in the ROM 34. The first output is assigned to the first head 37 via the output terminal 35, while
The second output is assigned to the second head 38 via the output terminal 36. In the figure, 41 is a 4-frame memory on the playback side that stores 4 frames of video data, and the 4-frame memory 41 receives the first input playback video data played back by the first head 37. Second input reproduced video data inputted via the terminal 39 and reproduced by the second head 38 is inputted via the input terminal 40, and these first input and second input are input from the write address counter 42. Written according to the address. Further, data is read from the 4-frame memory 41 according to the address generated by the read address counter 43 after being deinterleaved in the ROM 44, and reproduced video data is outputted via the output terminal 45.

Next, the operation will be explained. In the recording system shown in FIG. 1, a video signal digitized by an A/D converter 1 is first stored for four frames in a data divider 2.
The video is read out in such a way as to perform high-efficiency coding blocking and allocation of each block to two heads in a staggered manner. Four frames of video data are written via the input terminal 31 to the address of the four-frame memory 30 generated by the write address counter 32. The address generated by the read address counter 33 is divided vertically into five by the ROM 34 as shown in FIG.
The video data is highly efficiently coded and blocked into 30 blocks divided horizontally into 6 blocks, and the addresses are converted and read out so that each block is interleaved to be divided into two heads in a houndstooth pattern. The output to the heads is recorded on the first head 37 and the second head 38. Here, when reading from the 4-frame memory, if the position of the high-efficiency coding block is determined as shown in FIG. 3, the first output is {1, 3, 5, 8, 10, 12, 13,
15, 17, 20, 22, 24, 25, 2
7, 29} block, and the second output is {2, 4, 6,
7, 9, 11, 14, 16, 18, 19, 2
1, 23, 26, 28, 30} blocks, the blocks allocated to each head are arranged in a staggered pattern as shown in FIG.

Compression processing is performed on blocks assigned to each head by high-efficiency encoders 3 and 4, respectively. The compressed video signals are subjected to error correction encoding by error correction encoders 5 and 6, respectively. The error correction encoded data is recorded and encoded by modulators 7 and 8, and then recorded on magnetic tape 80 by first head 11 and second head 12 via recording amplifiers 9 and 10, respectively.

In the reproduction system, data reproduced by the first head 11 and the second head 12 is recorded and decoded by demodulators 15 and 16 via head amplifiers 13 and 14, respectively, and is recorded and decoded by error correction decoders 17 and 18. Error correction decoding is performed to perform error correction. If the data cannot be corrected, an error flag is attached to the data. Next, high efficiency decoders 19 and 2
0, the playback compressed video data is expanded. The expanded reproduced video data is taken into the data synthesizer 21, deinterleaved block by block, and returned to the original image block position. The input data from each head is written to the address of the 4-frame memory 41 generated by the write address counter 42, and the address generated by the read address counter 43 is deinterleaved by the ROM 44 to return it to the original image block position. The data is read and output according to the address converted to perform the following. For data that cannot be error corrected and has an error flag attached, the interpolator 22 performs interpolation processing using the upper, lower, left, and right blocks, and the D/A converter 23 converts it into an analog playback video signal and outputs it. .

[0021] When performing the interleaving process in which the screen is allocated block by block to the two heads in a houndstooth pattern as described above, the data for which error correction is impossible due to clogging in one head is as shown in Fig. 4. are distributed in a houndstooth pattern. Therefore, since the upper, lower, left, and right data are left correctly, it is possible to perform effective interpolation processing using these accurate data.

(Second Embodiment) FIG. 5 is a block diagram showing the configuration of a second embodiment of the video signal recording apparatus of the present invention.
Portions in the figure with the same numbers as those in FIG. 1 (first embodiment) indicate the same members, so their explanations will be omitted. In Figure 5, 2
4 stores four frames of digital video data from the A/D converter 1, blocks the screen into blocks for each plurality of pixels,
This is an interleave circuit that performs interleaving that assigns each block to two heads.
After combining the playback video data from two heads,
This is a deinterleave circuit that returns the original data order.

FIG. 6 is a diagram showing the configuration of the interleaving circuit 24. The interleaving circuit 24 includes a high-efficiency encoding blocking processing section 46 that divides the screen into a plurality of blocks, and a high-efficiency encoding blocking processing section 46 that divides each divided block into two blocks. A block division processing unit 47 for allocating heads, a first randomization processing unit 48 that randomizes the data allocated to the first head 37 using a random pattern generated by an M sequence and reads it as a first output, and a second head. The second randomization processing section 49 randomizes the data assigned to 38 using a random pattern generated by a different M sequence and reads it out as a second output.

Next, the operation will be explained. First, regarding the operation of the recording system, other operations except for the operation within the interleaving circuit 24 are the same as those in the first embodiment described above, so a description thereof will be omitted, and emphasis will be placed on the operation of the interleaving circuit 24. Explain in detail. First, in the high-efficiency encoding blocking processing section 46 in the interleave circuit 24, four frames of video data are divided into 60 blocks, in which the screen is divided into 6 vertically and 10 horizontally, as shown in FIG. Next, in the block division processing section 47, each block is allocated to two heads in a staggered pattern as shown in FIG. Then, in the first randomization processing section 48 and the second randomization processing section 49,
Data assigned to each head is randomized using random patterns generated by different M sequences, and then read out.

In addition, in the operation of the reproduction system, the other operations except for the operation in the deinterleaving circuit 25 are the same as those in the first embodiment described above, so a description thereof will be omitted and only the de-interleaving circuit 25 will be described. Interleave circuit 25
Only the operation will be explained. The reproduced video data decompressed by the high-efficiency decoders 19 and 20 is input to the deinterleaving circuit 25, where it is deinterleaved in block units and returned to the original image block position. 22 and the D/A converter 23.

In the second embodiment, different M
By using the sequence, the positions of blocks assigned to the first head and the second head are distributed, thereby reducing adjacent errors. Here, the M sequence is a binary sequence with a period of 2m -1 generated by a primitive polynomial on GF (2m), which is an apparently random sequence, and is widely used as a pseudo-noise sequence for simulations, etc. It is. Random interleaving can be performed by using this M sequence and reading blocks in the order of the M sequence. Furthermore, M sequences generated by different primitive polynomials are different random sequences. As an example, primitive polynomial 1 on GF(25). X5 +X2 +1, 2. X5 +X4
The M sequence generated by +X3 +X+1 has an initial value of 1 and 31, respectively. {1, 2, 4, 8, 16, 5
,10, 20, 13, 26, 17,7,14,
28, 29, 31, 27, 19, 3, 6, 1
2, 24, 21, 15, 30, 25, 2
3, 11, 22, 9, 18}, 2. {31,5,1
0, 20, 19, 29, 1, 2, 4, 8, 16,
27, 13, 26, 15, 30, 7, 14,
28, 3, 6, 12, 24, 11, 22, 23
, 21, 17, 25, 9, 18, 31, 5, 1
0, 20, 19, 29}, resulting in a random sequence with a period of 31. For example, interleaving circuit 24
When the order of the blocks read from the screen is as shown in FIG. 11 on the screen, if an uncorrectable scratch (hatched area) has occurred on the upper part of the magnetic tape 80 as shown in FIG. do. In FIG. 8, A, B
represent tracks recorded by the first head 11 and the second head 12, respectively. In such a case, the error correction position on the screen will be as shown in FIG. 12, and the error can be dispersed and interpolated using nearby data.

In the video signal recording device of the second embodiment,
High-efficiency encoding methods generally block image samples.
(for example, 8×8 samples), and after orthogonal transformation in block units, variable length encoding is performed. Since this kind of high-efficiency encoding uses a compression method that quantizes and encodes adaptively to the image content within a block, the sum of each block's compressed information within one screen or within several screens is not necessarily a constant amount. Must not be. However, when recording this compressed information on magnetic tape, it is necessary to record the compressed information of one screen or several screens in a specific track in order to simplify special playback/editing and playback signal processing circuits. If the amount of compressed information increases due to the content of the compressed information, it will not be possible to record it in a specific track, and if the amount of compressed information is small, some tracks will not be recorded within the specific track. Therefore, in order to be able to always record information within a characteristic track, the amount of information after compression is estimated from the information before high-efficiency encoding, and finally the information of one screen or several screens is focused into a specific track. The amount of information in each block is controlled by variable length encoding.

Now, consider a case where an image with a large amount of information in the center as shown in FIG. 9 is input as a video input. For example, if the high-efficiency encoding block is 60 blocks with the screen divided into 6 vertical and 10 horizontal blocks, and high-efficiency encoding is performed on each block, each block will eventually be divided into 1 to 10 blocks as shown in Figure 10.
The amount of information shall be . If the information of each of these blocks is read horizontally from the upper left and subjected to high-efficiency encoding processing in that order, blocks with a large amount of compressed information will be partially concentrated due to image correlation in the horizontal direction, resulting in a cumulative amount of information. Changes become drastic. The straight line represented by a broken line in Fig. 13 is the transition of the ideal accumulated information amount, and if it deviates significantly from this, the amount of information will not be settled within the final determined amount, so information amount control is performed, resulting in a decrease in the accuracy of compressed information, and thus the image quality. This may cause deterioration. Therefore, when the blocks read out from the interleave circuit 24 are randomly extracted and read out as shown in FIG. 11, blocks with a large amount of compressed information are distributed because the blocks are processed regardless of image correlation. Therefore, the cumulative amount of information in one screen changes as shown in FIG. 13, approaching the ideal transition of the cumulative information amount, and there is no need to increase the amount of information control, and it is possible to prevent a decrease in the accuracy of compressed information. The deinterleaving circuit 25 on the reproduction side writes in the order randomly extracted on the recording side, and returns to the original image position.

[0029]

As described above, in the first invention, since the blocks of the screen are assigned to a plurality of heads in such a way that the positional correlation is minimized, even if the heads become clogged, the errors are dispersed and the errors are dispersed. A highly reliable corrected screen can be obtained on the playback side.

[0030] In the second invention, since the blocks of the screen are allocated to a plurality of heads so that the correlation of positions is minimized, and the data to each head is interleaved using a different M sequence, the image correlation is It disperses the unevenness of the amount of information caused by this, making it easier to change the total amount of information, and enables highly efficient encoding without reducing the accuracy of compressed information more than necessary.Even if scratches on the magnetic tape or head clogging occur, the system can
A highly reliable corrected screen can be obtained, and image quality deterioration is reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a video signal recording device of a first invention.

FIG. 2 is a diagram showing the configuration of a data divider and a data synthesizer in FIG. 1;

FIG. 3 is a diagram showing a high-efficiency encoding block in the first invention.

FIG. 4 is a diagram showing allocation of blocks to each head in the first invention.

FIG. 5 is a block diagram showing the configuration of a video signal recording device of a second invention.

FIG. 6 is a diagram showing a configuration of an interleaving circuit in FIG. 5;

FIG. 7 is a diagram showing allocation of blocks to each head in the second invention.

FIG. 8 is a diagram showing an example of a recording format on a magnetic tape and scratches on the magnetic tape in the second invention.

FIG. 9 is a diagram showing an example of an input image in the second invention.

10 is a diagram showing an example of data when the example input image shown in FIG. 9 is compressed by high-efficiency encoding; FIG.

FIG. 11 is a diagram showing an example of the reading order of data interleaved by the interleave circuit in the second invention.

12 is a diagram showing an example of error distribution when an uncorrectable scratch occurs on the magnetic tape as shown in FIG. 8 in the second invention; FIG.

13 is a diagram showing the cumulative transition order of data that is compressed by high-efficiency encoding and read out in the order shown in FIG. 11 in the second invention; FIG.

FIG. 14 is a block diagram showing the configuration of a conventional video signal recording device.

[Explanation of symbols]

2 Data divider 3 High-efficiency encoder 4 High-efficiency encoder 11 First head 12 Second head 24 Interleaving circuit 30 4-frame memory 33 Read address counter 34 ROM 46 High-efficiency encoding blocking processing section 47 Block division processing section 48 First randomization processing section 49 Second randomization processing section 80 Magnetic tape

Claims (2)

[Claims] 1. A video signal recording device that performs high-efficiency encoding processing on a digital video signal and records the data after the high-efficiency encoding processing on a recording medium using a plurality of recording members, wherein the video signal is A video signal recording device comprising: means for forming blocks into blocks for each of a plurality of pixels; and means for allocating each block to each recording member so that the correlation between the positions of each block is minimized. 2. A video signal recording device that performs high-efficiency encoding processing on a digital video signal and records the data after the high-efficiency encoding processing on a recording medium using a plurality of recording members, wherein the video signal is means for dividing each block into blocks for each of a plurality of pixels; means for allocating each block to each recording member so that the correlation between the positions of each block is minimized; A video signal recording device comprising: means for changing the arrangement using an M sequence.