JPH0436872A - Design backup system for electronic parts mounting process - Google Patents
Design backup system for electronic parts mounting processInfo
- Publication number
- JPH0436872A JPH0436872A JP2141427A JP14142790A JPH0436872A JP H0436872 A JPH0436872 A JP H0436872A JP 2141427 A JP2141427 A JP 2141427A JP 14142790 A JP14142790 A JP 14142790A JP H0436872 A JPH0436872 A JP H0436872A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- electronic components
- section
- design
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013461 design Methods 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004458 analytical method Methods 0.000 claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 claims abstract description 25
- 238000004088 simulation Methods 0.000 claims abstract description 18
- 238000012545 processing Methods 0.000 claims abstract description 15
- 238000004364 calculation method Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 claims 1
- 238000011161 development Methods 0.000 abstract description 11
- 230000035882 stress Effects 0.000 description 11
- 239000000047 product Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 230000008646 thermal stress Effects 0.000 description 6
- 238000002076 thermal analysis method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000008707 rearrangement Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Landscapes
- Supply And Installment Of Electrical Components (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は高信頼度モジュールを短期間に製造する電子部
品実装工程設計支援システムに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic component mounting process design support system for manufacturing highly reliable modules in a short period of time.
従来の電子部品実装工程設計支援システムは経験則に基
づきプリント配線基板用パターン設計装置を用いて、試
作用の電気的な配線パターンの作成と電子部品の配置デ
ータを生成し、プリント配線基板製造装置を用いて通常
の製造工程により試作用のプリント配線基板を製造し、
部品搭載機で画像処理により電子部品及び配線パターン
を認識し、前記電子部品の配置データに基づいて所定の
位置へ部品を搭載した。組立製造の完了した試作用プリ
ント配線基板は各種信頼性試験により評価され、主に電
子部品の接続部の信頼性の向上を図るため別途バッチ処
理により熱、応力、振動、流れの各種シミュレーション
を行い、各種電子部品の接続部に加わるストレスを低減
するよう再度電子部品の配置及び配線パターンを修正し
前記プリント配線基板用パターン設計及び製造装置へフ
ィードバックすることを行っており、前記工程を数回繰
り返した後、最終の組立完了済みプリント配線基板を得
ていた。尚この種のシステムとして関連するものには、
例えば特開昭61−74399号、同62−27164
.1号等において論じられている。Conventional electronic component mounting process design support systems use a pattern design device for printed wiring boards based on empirical rules to create electrical wiring patterns for prototypes and generate placement data for electronic components. Prototype printed wiring boards are manufactured using normal manufacturing processes using
A component mounting machine recognized electronic components and wiring patterns through image processing, and mounted the components at predetermined positions based on the electronic component placement data. The prototype printed wiring boards that have been assembled and manufactured are evaluated through various reliability tests, and various simulations of heat, stress, vibration, and flow are conducted through separate batch processing to improve the reliability of the connections between electronic components. In order to reduce the stress applied to the connections of various electronic components, the placement and wiring patterns of electronic components are revised again and feedback is fed back to the printed wiring board pattern design and manufacturing equipment, and the process is repeated several times. After that, the final assembled printed wiring board was obtained. Related systems of this type include:
For example, JP-A-61-74399, JP-A No. 62-27164
.. This is discussed in No. 1, etc.
」二記従来技術では最終製品を得るまでに数回の試作段
階を経る必要が有り、開発期間の短縮の大きな障害とな
っている。また、実際の電子部品及びプリント配線基板
を用いて、試作を繰り返すため、全体の開発コストを押
し」二げる問題があった。2. In the conventional technology, it is necessary to go through several trial production stages before obtaining the final product, which is a major obstacle to shortening the development period. Furthermore, since trial production is repeated using actual electronic components and printed wiring boards, there is a problem in that the overall development cost is increased.
本発明は、前記電子部品実装工程の設計支援システムの
一貫自動化と高信頼化を図って開発期間を短縮し、試作
段階を省力化することで全体の開発コストを低減し高信
頼度の製品を短期間に得ることを目的としている。The present invention aims to consistently automate and increase the reliability of the design support system for the electronic component mounting process, thereby shortening the development period and saving labor in the prototyping stage, thereby reducing the overall development cost and producing highly reliable products. The aim is to obtain it in a short period of time.
上記目的を達成するために、プリント配線基板。 To achieve the above purpose, printed wiring board.
電子部品の諸元及び過去の配置データを蓄積し、熱、応
力、振動、流れの各種シミュレーションを行う解析処理
装置へオンラインでデータ転送し、゛ 3 ゛
仮想配置したプリン[・配線基板を対象にCRT上で解
析を実行した後、得られた最適配置データをプリン]・
配線基板用パターン設計及び製造装置へデータ転送しこ
こで初めて配線設計をおこない、これによりプリント配
線基板を製造して、前記最適配置データを基に部品搭載
機の搭載処理を制御し、得られたプリン]・配線基板上
に電子部品を搭載し組立完了した最終製品を得るもので
ある。The specifications and past placement data of electronic components are accumulated, and the data is transferred online to an analysis processing device that performs various simulations of heat, stress, vibration, and flow. After performing the analysis on the CRT, print the obtained optimal placement data]・
The data is transferred to the wiring board pattern design and manufacturing equipment, where the wiring is designed for the first time, the printed wiring board is manufactured using this data, and the mounting process of the component mounting machine is controlled based on the optimal layout data.・Electronic components are mounted on a wiring board to obtain a final product that has been assembled.
また、上記他の目的を達成するためにCRT上で電子部
品をプリント配線基板上に仮想配置し、所望の信頼性を
得るまでシミュレーションを繰り返す工程をすべてCR
T上で行うものである。In addition, in order to achieve the other objectives mentioned above, the entire process of virtually arranging electronic components on a printed wiring board on a CRT and repeating simulations until the desired reliability is achieved is completely covered by CR.
This is done on T.
プリント配線基板、電子部品の諸元及び仮装置データに
関する蓄積データは、オンラインにより解析処理装置に
データ転送される。CRT上で電子部品をプリント配線
基板上に仮想配置し、所望の信頼性を得るまでシミュレ
ーションを繰り返す。Accumulated data regarding specifications of printed wiring boards, electronic components, and temporary device data are transferred online to the analysis processing device. Electronic components are virtually placed on a printed wiring board on a CRT, and simulations are repeated until desired reliability is achieved.
シミュlノージョン完了後得られた最適配置データをプ
リント配線基板用パターン設計及び製造装置ヘデータ転
送し、ここで初めてプリント配線基板を製造する。これ
によって、シミュレーションの工程がインライン化され
るので高信頼度の製品を短期間に得ることができる。ま
た、シミュレーションの工程はすべてCRTJ二で行う
ので試作段階が不要となり開発設計コス1〜が低減でき
る。After the simulation is completed, the obtained optimal layout data is transferred to the printed wiring board pattern design and manufacturing equipment, where the printed wiring board is manufactured for the first time. This allows the simulation process to be done in-line, making it possible to obtain highly reliable products in a short period of time. In addition, since all the simulation steps are performed on the CRTJ2, there is no need for a prototype stage, and development and design costs can be reduced.
以下本発明の一実施例を第1図を用いて説明する。第1
図は本発明を実施するための電子部品実装工程設計支援
システムの基本構成例である。同図において先ず蓄積デ
ータ部1は実装対象となる電子部品とプリント配線基板
の寸法9種類、パターン等の各諸元をデータ・ベースと
して有している。解析部2は前記蓄積データ部1から提
供されてきた各データを基にモデル化し、熱・応力・振
動・流れ及び熱と応力、熱と流れの達成問題等の各種シ
ミュレーションを行い、その結果をCRTSa上にグラ
フィック表示する。設計部5はプリント配線基板の配線
パターンの生成と電気的結線及び電子部品のレイアウト
を行い、その結果をCRT3b上にグラフィック表示す
る。部品搭載機13の構成例としては部品吸着装置12
.電子部品用ステージ11.画像処理装置10.処理部
6.プリント配線基板用ステージ91部品搭載用アーム
8゜等からなる。処理部6はプリント配線基板と電子部
品を画像処理装置10で認識し、電子部品用ステージ1
1を駆動させて所定の電子部品を部品吸着装置12で持
ち上げる。つぎに部品搭載用アーム8とプリント配線基
板用ステージ9を駆動させ所定の位置まで移動したのち
アライメントを行いプリント配線基板」二に電子部品を
搭載することを制御する。製造部14は電子部品の最適
配置データを基に配線その他のパターンフィルムを製作
し、通常のプリント配線基板製造工程に引き渡す。An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows an example of the basic configuration of an electronic component mounting process design support system for implementing the present invention. In the figure, first, the stored data section 1 has nine types of dimensions, patterns, and other specifications of electronic components and printed wiring boards to be mounted as a data base. The analysis section 2 creates a model based on each data provided from the accumulated data section 1, performs various simulations such as heat, stress, vibration, flow, heat and stress, heat and flow achievement problems, and reports the results. Graphically displayed on the CRTSa. The design section 5 generates a wiring pattern for a printed wiring board, lays out electrical connections and electronic components, and displays the results graphically on the CRT 3b. An example of the configuration of the component mounting machine 13 is the component suction device 12.
.. Stage 11 for electronic components. Image processing device 10. Processing unit 6. It consists of a stage 91 for printed wiring boards, an arm 8° for mounting parts, etc. The processing unit 6 recognizes the printed wiring board and electronic components using the image processing device 10, and sets the stage 1 for electronic components.
1 is driven to pick up a predetermined electronic component with a component suction device 12. Next, the component mounting arm 8 and the printed wiring board stage 9 are driven and moved to a predetermined position, and then alignment is performed to control the mounting of electronic components on the printed wiring board. The manufacturing department 14 manufactures wiring and other pattern films based on the optimal placement data of electronic components, and transfers them to a normal printed wiring board manufacturing process.
次に第1図の設計支援システムを用いた電子部品実装工
程を第2図及び第3図を用いて説明する。Next, an electronic component mounting process using the design support system shown in FIG. 1 will be explained with reference to FIGS. 2 and 3.
先ず、蓄積データ部1−から電子部品の仮想配置データ
、寸法、ビン数、材料物性値等を、また、プリント配線
基板の仮想配線データ、ピアホール位置9層数、材料物
性値等の各諸元が解析部2にオンラインでデータ転送さ
れる。解析部2はそのデータに基づいてCR,T g
a上で電子部品及びプリン]・配線基板のモデル化を行
い、電子部品をプリント配線基板上に仮想配置する。第
2図(a)は電子部品を仮想配置したプリント配線基板
のモデルのレイアウト図である。同図においてプリント
配線基板21上には発熱量の多い各種論理回路素子24
゜27、各種記憶素子22.26.抵抗25.コンデン
サ23゜が混在して配置されている。このモデルを対象
に使用環境を想定した熱・応力・振動・流れ等の各種解
析を行い、結果をCRT3a上にグラフィック表示する
。解析結果として、部品24aに大きな応力値や高い温
度分布が発生し許容値を超えている場合、24bに移動
して再度解析を行い、部品24、aに発生する大きな応
力値や高い温度分布が許容値以下に低減する配置になる
まで、解析を繰り返す。その際、配線パターンの引き回
し可能な範囲で解析を行なう。ここで実際の使用環境条
件。First, from the stored data section 1-, virtual arrangement data, dimensions, number of bins, material property values, etc. of electronic components are obtained, as well as various specifications such as virtual wiring data of the printed wiring board, number of layers of peer hole positions, material property values, etc. The data is transferred to the analysis section 2 online. The analysis unit 2 calculates CR, T g based on the data.
[Electronic components and printed circuit board] - Model the wiring board and virtually place electronic components on the printed wiring board. FIG. 2(a) is a layout diagram of a model of a printed wiring board in which electronic components are virtually arranged. In the figure, on the printed wiring board 21 are various logic circuit elements 24 that generate a large amount of heat.
゜27, various memory elements 22.26. Resistance 25. Capacitors 23° are arranged in a mixed manner. Various analyzes of heat, stress, vibration, flow, etc. are performed on this model assuming the usage environment, and the results are displayed graphically on the CRT 3a. As a result of the analysis, if a large stress value or high temperature distribution occurs in the part 24a and exceeds the allowable value, move to 24b and perform the analysis again to confirm that the large stress value or high temperature distribution occurring in the part 24,a is The analysis is repeated until a configuration that reduces the amount below the allowable value is achieved. At that time, analysis is performed within the range where the wiring pattern can be routed. Here are the actual usage environment conditions.
部品の耐熱性、要求される信頼性等の制約条件から要求
仕様として論理回路素子24..21のジャンクション
温度Jcが約150°C以下に、またはんだ付は部の温
度差△Tは約80’ C以下に、さらに振動に対して約
1.0Hz〜200Hzを除いた周波数特性を持つよう
に電子部品を設計・配置する必要がある。The logic circuit element 24. .. 21 junction temperature Jc is about 150°C or less, and the temperature difference △T at the soldering part is about 80'C or less, and the frequency characteristics for vibration are kept except about 1.0Hz to 200Hz. It is necessary to design and arrange electronic components.
そこで解析手順の一例として熱解析の場合において、第
2図(a)のように仮想配置した場合の論理回路素子2
4のJcとΔTの解析を行なうと、Jcは約150°C
以上に、また八Tは約】25″C以」二に達した。そこ
で第2図(b)に示すように、発熱量の多い論理回路素
子24と27を移動・分散させ再度解析を行なうと、J
cは約1.25″Cに、また八Tは約100°Cに低減
した。更に、第2図(C)に示すように、論理回路素子
24と27を移動・分散させ解析を繰り返していき、最
終的にはJcは約100°Cに、また八Tは約60°C
に低減し、上記所望の仕様を十分に達成する電子部品の
再配置を決定することができた。以上熱解析の例を挙げ
たが、熱解析及び応力解析の練成問題としてシミュレー
ションした結果を第3図に示す。第3図(a)では発熱
量の多い論理回路素子24の集中している部分のプリン
ト配線基板21の温度が著しく高くなったり偏った温度
分布を示している。この温度分布に基づき発生する熱応
力によりプリント配線基板21は局部的に大きく変形し
、論理回路素子24及びそのはんだ接続部に大きな熱応
力が加わる。そこで第3図(b)に示すように、CR,
T 3 a上で論理回路素子24を移動し、プリント配
線基板21上の両端に分散配置することで発生ずる温度
分布も均一化する。Therefore, as an example of the analysis procedure, in the case of thermal analysis, the logic circuit elements 2 are virtually arranged as shown in FIG. 2(a).
When analyzing Jc and ΔT in 4, Jc is approximately 150°C.
In addition, the 8T reached about 25"C or higher. Therefore, as shown in FIG. 2(b), when the logic circuit elements 24 and 27, which generate a large amount of heat, are moved and distributed and the analysis is performed again, J
c was reduced to approximately 1.25''C, and 8T was reduced to approximately 100°C.Furthermore, as shown in Figure 2(C), the logic circuit elements 24 and 27 were moved and distributed and the analysis was repeated. Finally, Jc becomes about 100°C, and 8T becomes about 60°C.
We were able to determine the rearrangement of the electronic components to fully achieve the desired specifications. Examples of thermal analysis have been given above, and FIG. 3 shows the results of a simulation as a practice problem for thermal analysis and stress analysis. In FIG. 3(a), the temperature of the printed wiring board 21 in the portion where the logic circuit elements 24 which generate a large amount of heat are concentrated is extremely high, and the temperature distribution is uneven. The printed wiring board 21 is locally significantly deformed due to the thermal stress generated based on this temperature distribution, and a large thermal stress is applied to the logic circuit element 24 and its solder connection portion. Therefore, as shown in FIG. 3(b), CR,
By moving the logic circuit elements 24 on T 3 a and distributing them at both ends of the printed wiring board 21, the resulting temperature distribution is also made uniform.
この温度分布に基づき発生する熱応力によりプリント配
線基板21の変形も小さくなり、論理回路素子24及び
そのはんだ接続部に発生する熱応力も低減する。以上の
ようにして、プリント配線基板上の電子部品24は再配
置され、低熱応力の電子部品の再配置データが得られる
。次にこの再配置データは設計部5にオンラインで転送
される。設計部5は解析部2からの再配置データをもと
にして、プリント配線基板の配線パターンの修正を行う
。Thermal stress generated based on this temperature distribution reduces the deformation of the printed wiring board 21, and also reduces the thermal stress generated in the logic circuit element 24 and its solder connections. In the manner described above, the electronic components 24 on the printed wiring board are rearranged, and the rearrangement data of the electronic components with low thermal stress is obtained. This relocation data is then transferred to the design department 5 online. The design section 5 corrects the wiring pattern of the printed wiring board based on the rearrangement data from the analysis section 2.
最終的に得られた配線パターン・データは製造部14に
転送される。ここでパターンフィルムを製造した後通常
のプリント配線基板製造工程により初めて実際のプリン
ト配線基板を製造する。部品搭載機】3の処理部6は設
計部5からオンラインで転送されてきた配線パターン及
び電子部品の最適配置データに基づいて、製造部14か
ら得られたプリント配線基板上に各種電子部品を搭載し
、電子部品の実装工程が完了する。The finally obtained wiring pattern data is transferred to the manufacturing department 14. After manufacturing the pattern film, an actual printed wiring board is manufactured for the first time through a normal printed wiring board manufacturing process. [Component mounting machine] The processing section 6 of 3 mounts various electronic components on the printed wiring board obtained from the manufacturing section 14 based on the wiring pattern and optimal placement data of electronic components transferred online from the design section 5. Then, the electronic component mounting process is completed.
以上の解析手順の流れ図を第4図に示す。まず電子部品
及び基板の各種データを蓄積データ部1の電子部品及び
基板の諸元データベースを利用しながら入力する。次に
解析部2のなかでモデル化と自動分割をCRT表示をみ
ながら行なう。分割終了後、有限要素法、境会要素法、
差分法等の数値解析により、熱・応力・振動・流れの各
種解析を行ない解析結果をCRT表示させる。解析結果
からプリント基板及び電子部品の要求仕様を満足するか
判定し、合格ならば設計部5によりプリント基板の配線
パターンの設計を行ない、不合格ならば再度モデル化と
自動分割をCRT表示をみながら行なう。設計部5にお
いてプリント基板の配線パターンを作成する際、プリン
ト配線基板の製造上非常な困難を伴う場合あるいは電気
的特性が所望の値を満足できない場合に、再度解析部2
にフィード・バックされてモデルを修正しシミュレーシ
ョンを行い配線可能な最適配置まで繰り返される。最終
的に得られた配線パターン・データは、プリント配線基
板の製造部14及び部品搭載機の処理部6に転送され全
体の解析が終了する。本実施例によれば、プリント配線
基板上に要求仕様を満足する電子部品配置を行うことが
できるので、高信頼度の製品を得ることができる。また
シミュレーションの部分がインライン化されており、製
品の試作が不要となるので、開発から製造期間までを短
縮することができ、さらに試作に係わる開発コストの低
減となる。A flowchart of the above analysis procedure is shown in FIG. First, various data on electronic components and circuit boards are input using the specification database of electronic components and circuit boards in the stored data section 1. Next, modeling and automatic division are performed in the analysis section 2 while looking at the CRT display. After the division is completed, the finite element method, boundary element method,
Various analyzes of heat, stress, vibration, and flow are performed using numerical analysis such as the finite difference method, and the analysis results are displayed on a CRT. It is determined from the analysis results whether the required specifications of the printed circuit board and electronic components are satisfied, and if it passes, the design department 5 designs the wiring pattern of the printed circuit board, and if it fails, it is modeled again and automatically divided by looking at the CRT display. Do it while doing it. When creating a wiring pattern for a printed circuit board in the design section 5, if there is great difficulty in manufacturing the printed circuit board or if the electrical characteristics cannot satisfy the desired values, the analysis section 2
This feedback is fed back to the model, the model is modified, simulations are performed, and the process is repeated until the optimal layout is possible. The finally obtained wiring pattern data is transferred to the printed wiring board manufacturing section 14 and the processing section 6 of the component mounting machine, and the overall analysis is completed. According to this embodiment, it is possible to arrange electronic components that satisfy the required specifications on the printed wiring board, so that a highly reliable product can be obtained. Furthermore, since the simulation part is inline, there is no need to make a prototype of the product, so the period from development to manufacturing can be shortened, and the development costs associated with prototyping can be reduced.
次に、本発明における第2の実施例を第5図を用いて説
明する。同図は蓄積データ部1と解析部2での設計手順
のフロー図を示している。同図により蓄積データ部1は
過去の設計事例をデータ・ベースとして有しており、対
象とした電子部品とプリント配線基板の寸法6種類、パ
ターン等の各゛ 12゛
諸元データを各事例毎に登録している。実装対象とする
電子部品と配線基板に関するデータが入力されると、蓄
積データ部1に登録されているデータ・ベースの検索と
マツチングが行われ最も類似した設計事例をCRT上に
出力する。設計者はCRT上で不足の電子部品を追加し
たり過剰の電子部品を削除して所望の設計対象を作成し
、解析部2にデータ転送する。解析部2ではモデル化を
行った後以下第1の実施例と同様の設計手順で、所望の
プリント配線基板を設計・製造し電子部品の実装を行う
。本実施例によれば、蓄積データ部に提供するデータの
入力作業が大幅に省力化され、また解析部の計算繰返し
回数が軽減され設計期間を短縮することができる。Next, a second embodiment of the present invention will be described using FIG. 5. This figure shows a flowchart of the design procedure in the stored data section 1 and the analysis section 2. As shown in the figure, the accumulated data section 1 has past design cases as a database, and data on each of the 12 dimensions of the target electronic components and printed wiring boards, including six types of dimensions and patterns, is stored for each case. is registered with. When data regarding electronic components and wiring boards to be mounted are input, a search and matching is performed in the database registered in the stored data section 1, and the most similar design example is output on the CRT. The designer creates a desired design object by adding missing electronic components or deleting excess electronic components on the CRT, and transfers the data to the analysis section 2. After modeling, the analysis section 2 designs and manufactures a desired printed wiring board and mounts electronic components using the same design procedure as in the first embodiment. According to this embodiment, the work of inputting data to be provided to the stored data section can be greatly reduced, and the number of calculation repetitions of the analysis section can be reduced, so that the design period can be shortened.
次に、本発明における第3の実施例を第6図を用いて説
明する。同図(a、)はプリント配線基板」二に各種電
子部品を搭載した場合のレイアウト図を、また(b)は
その一部を取り出したものを示している。蓄積データ部
1において、電子部品とプリント配線基板の寸法7種類
、パターン等の各諸元とともに各電子部品に要求される
信頼度がランク分けしてデータ・ベース化されている。Next, a third embodiment of the present invention will be described using FIG. 6. 2(a) shows a layout diagram when various electronic components are mounted on a printed wiring board, and FIG. 2(b) shows a portion thereof. In the stored data section 1, the reliability required for each electronic component is classified into ranks and compiled into a data base along with specifications such as seven types of dimensions and patterns of electronic components and printed wiring boards.
設計者が実装対象とする電子部品と配線基板に関するデ
ータを入力すると、CRT上には第6図(a)に示すよ
うに入力した電子部品の要求信頼度がラング分けして表
示される。When the designer inputs data regarding the electronic component and wiring board to be mounted, the required reliability of the input electronic component is displayed on the CRT, divided into ranks, as shown in FIG. 6(a).
ここで、要求信頼度を各条件別にまとめて表1に記載し
た。Here, the required reliability is summarized for each condition in Table 1.
表1 要求信頼度
ここで、信頼度は、表1に示すようにA>B>Cの順で
ある。設計者は必要に応じて同図(b)のように、最も
信頼度の要求が高い電子部品周辺から順次取り出して解
析部2にデータ転送する。更に配線基準等により最適配
置が困難な場合には信頼度ランクを順次繰り下げて解析
部2にデータ転送する。解析部2ではモデル化を行った
後以下第1の実施例と同様の設計手順で、所望のプリン
ト配線基板を設計・製造し電子部品の実装を行う。Table 1 Required Reliability Here, as shown in Table 1, the reliability is in the order of A>B>C. As needed, the designer sequentially extracts electronic components from around electronic components that require the highest reliability and transfers the data to the analysis unit 2, as shown in FIG. 2(b). Furthermore, if optimum placement is difficult due to wiring standards, etc., the reliability rank is sequentially lowered and the data is transferred to the analysis unit 2. After modeling, the analysis section 2 designs and manufactures a desired printed wiring board and mounts electronic components using the same design procedure as in the first embodiment.
本実施例によれば、解析部に提供するデータ量が大幅に
減少し、解析部の計算負荷が軽減され設計期間を短縮す
ることができる。According to this embodiment, the amount of data provided to the analysis section is significantly reduced, the calculation load on the analysis section is reduced, and the design period can be shortened.
本発明は、以上説明したように構成されているので、以
下に記載されるような効果を奏する。先ず、製造工程を
構成する各制御部分をオンラインで接続し電子部品及び
プリント配線基板の各諸元や配置データを転送している
ので、データの再入力に伴うミスや労力を減らし、高精
度の設計を行うことができる。またシミュレーションの
部分がインライン化されており、製品の試作が不要とな
るので、開発から製造期間までを従来の172以下に短
縮することができる。さらにプリン[・配線基板上に電
子部品を仮装置する工程は、すべてCRT上で行うので
部材を必要とせず試作回数が172以下となリコストの
低減となる。またシミュレーションにより使用環境下で
のプリント配線基板上の電子部品及びその接続部のスト
レスが許容値以下になるような配置に設計されるので高
信頼度の製品を得ることができる。Since the present invention is configured as described above, it produces the effects described below. First, each control part that makes up the manufacturing process is connected online and the specifications and layout data of electronic components and printed wiring boards are transferred, reducing errors and labor associated with re-entering data, and achieving high precision. Design can be done. In addition, the simulation part is done inline, eliminating the need for product prototypes, so the period from development to manufacturing can be shortened to less than 172 seconds compared to conventional products. Furthermore, since the process of temporarily mounting electronic components on a print/wiring board is all performed on a CRT, no parts are required and the number of prototypes is less than 172, reducing re-costs. Further, by simulation, the layout is designed so that the stress of the electronic components on the printed wiring board and their connections under the usage environment is below the allowable value, so a highly reliable product can be obtained.
第1図は本発明の一実施例の電子部品実装工程設計支援
システムの基本構成図である。第2図は電子部品を仮想
配置したプリント配線基板の熱解析のモデル図である。
第3図は発熱量の多い半導体素子が集中してプリント配
線基板上に仮想配置された場合の熱解析とその結果に基
づいた熱応力解析例を示すモデル図である。第4図は本
発明の第1の実施例に基づいた電子部品実装工程の解析
手順の流れ図である。第5図は蓄積データ部と解析部で
の解析手順の流れ図である。第6図は部品の信頼度を併
せて表示した場合のプリント配線基板上の各種電子部品
のレイアウト図である。
〔符号の説明〕
■・・・蓄積データ部 2・・・解析部3・・・CR
T 4・・・メモリ5・・・設計部
6・・・部品搭載機用処理部8・・・電子部品搭載用
アーム
9・・・プリント配線基板用ステージ
10・・・画像処理装置 1]・・・電子部品用ステ
ージ12・・・電子部品用吸着装置
14・・・製造部 21・・・プリント配線基
板22及び26・・・各種記憶素子
23・・・コンデンサ
24及び27・・・各種論理回路素子
25・・・抵抗
28・・・論理回路素子の移動可能領域線圭 3 口
(tQ)
〔払前柑のη針ψ図〕
(b)
第 4 図
旨
畢
ム
■FIG. 1 is a basic configuration diagram of an electronic component mounting process design support system according to an embodiment of the present invention. FIG. 2 is a model diagram for thermal analysis of a printed wiring board on which electronic components are virtually arranged. FIG. 3 is a model diagram showing a thermal analysis in the case where semiconductor elements that generate a large amount of heat are virtually arranged in a concentrated manner on a printed wiring board, and an example of a thermal stress analysis based on the results. FIG. 4 is a flowchart of an analysis procedure for an electronic component mounting process based on the first embodiment of the present invention. FIG. 5 is a flowchart of the analysis procedure in the stored data section and the analysis section. FIG. 6 is a layout diagram of various electronic components on a printed wiring board when the reliability of the components is also displayed. [Explanation of symbols] ■...Accumulated data section 2...Analysis section 3...CR
T 4...Memory 5...Design Department
6... Processing section for component mounting machine 8... Arm for electronic component mounting 9... Stage 10 for printed wiring board... Image processing device 1]... Stage 12 for electronic components... Electronic component Adsorption device 14... Manufacturing department 21... Printed wiring boards 22 and 26... Various memory elements 23... Capacitors 24 and 27... Various logic circuit elements 25... Resistor 28... Logic Movable area of circuit element Kei 3 mouth
(tQ) [Figure of η needle ψ of Kazenkan] (b) 4th figure title■
Claims (3)
る組立製造工程までの一連の工程において、電子部品及
びプリント配線基板の諸元に関する蓄積データ部,数値
計算を行う解析部,プリント配線基板の配線作成を行う
設計部,実際のプリント配線基板を造る製造部,及び実
際に部品をプリント配線基板に搭載する処理部とで構成
し、蓄積データ部からの諸元と仮配置データに基づき、
前記解析部において電子部品を仮想配置したプリント配
線基板を対象に、熱,応力,振動,流れ及び熱と応力,
熱と流れの連成問題等をシミュレーシヨンし、各種電子
部品に加わるストレスを小さくし基板全体の放熱効率を
高めるよう電子部品の再配置を行った後、前記設計部に
より電気的な結線を行うためプリント配線基板の配線作
成を行い、前記製造部で実際に得られたプリント配線基
板に前記設計部で生成された電子部品の搭載位置データ
に基づき前記処理部により各種電子部品の搭載を行うこ
とを特徴とする電子部品実装工程設計支援システム。1. In a series of processes from the wiring design of printed wiring boards to the assembly and manufacturing process in which electronic components are mounted, we have an accumulated data department related to the specifications of electronic components and printed wiring boards, an analysis department that performs numerical calculations, and a wiring creation process for printed wiring boards. The production department consists of a design department, a manufacturing department that makes the actual printed wiring boards, and a processing department that actually mounts the parts on the printed wiring boards.Based on specifications and temporary placement data from the accumulated data department,
The analysis section analyzes heat, stress, vibration, flow, and heat and stress on a printed wiring board on which electronic components are virtually arranged.
After simulating the coupling problem of heat and flow, etc., and rearranging the electronic components to reduce the stress applied to various electronic components and increase the heat dissipation efficiency of the entire board, electrical connections are made by the design department. to prepare the wiring for the printed wiring board, and the processing section mounts various electronic components on the printed wiring board actually obtained by the manufacturing section based on the electronic component mounting position data generated by the design section. An electronic component mounting process design support system featuring:
づく電子部品の配置データ及びプリント配線基板の配線
パターンデータを知識データ・ベースとして登録し、前
記解析部に仮配置データとして提供することを特徴とす
る請求項1記載の電子部品実装工程設計支援システム。2. A claim characterized in that electronic component placement data and printed wiring board wiring pattern data based on past similar analysis cases are registered in the accumulated data section as a knowledge database and provided to the analysis section as temporary placement data. The electronic component mounting process design support system according to item 1.
を要求される信頼度にランク分けし、最上位ランクから
順次電子部品周辺の基板を取り出して解析部に提供し、
各種シミュレーシヨンを行うことを特徴とする請求項1
記載の電子部品実装工程設計支援システム。3. In the accumulated data section, electronic components to be designed are ranked according to required reliability, and boards around the electronic components are sequentially taken out from the highest rank and provided to the analysis section;
Claim 1 characterized in that various simulations are performed.
The electronic component mounting process design support system described.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2141427A JPH0436872A (en) | 1990-06-01 | 1990-06-01 | Design backup system for electronic parts mounting process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2141427A JPH0436872A (en) | 1990-06-01 | 1990-06-01 | Design backup system for electronic parts mounting process |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0436872A true JPH0436872A (en) | 1992-02-06 |
Family
ID=15291731
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2141427A Pending JPH0436872A (en) | 1990-06-01 | 1990-06-01 | Design backup system for electronic parts mounting process |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0436872A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05327296A (en) * | 1992-05-14 | 1993-12-10 | Nec Corp | Component placement processor |
WO2001050356A1 (en) * | 2000-01-04 | 2001-07-12 | Fujitsu Limited | Method and apparatus for designing printed-circuit board |
JP2002117082A (en) * | 2000-10-11 | 2002-04-19 | Zuken:Kk | Method and system for simulating mounting of flexible substrate |
US7114132B2 (en) | 2001-04-20 | 2006-09-26 | Nec Corporation | Device, system, server, client, and method for supporting component layout design on circuit board, and program for implementing the device |
JP2009529173A (en) * | 2006-03-08 | 2009-08-13 | エキスパート ダイナミックス リミテッド | Reliability simulation method and system |
-
1990
- 1990-06-01 JP JP2141427A patent/JPH0436872A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05327296A (en) * | 1992-05-14 | 1993-12-10 | Nec Corp | Component placement processor |
WO2001050356A1 (en) * | 2000-01-04 | 2001-07-12 | Fujitsu Limited | Method and apparatus for designing printed-circuit board |
US6662345B2 (en) | 2000-01-04 | 2003-12-09 | Fujitsu Limited | Method and apparatus for designing printed-circuit board |
JP2002117082A (en) * | 2000-10-11 | 2002-04-19 | Zuken:Kk | Method and system for simulating mounting of flexible substrate |
JP4672127B2 (en) * | 2000-10-11 | 2011-04-20 | 株式会社図研 | Mounting simulation method and apparatus for flexible substrate |
US7114132B2 (en) | 2001-04-20 | 2006-09-26 | Nec Corporation | Device, system, server, client, and method for supporting component layout design on circuit board, and program for implementing the device |
JP2009529173A (en) * | 2006-03-08 | 2009-08-13 | エキスパート ダイナミックス リミテッド | Reliability simulation method and system |
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