JPH043671B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an insulated gate field effect transistor,
In particular, the present invention relates to an insulated gate field effect transistor having a built-in protection diode for preventing electrical breakdown of the gate. Due to the structure of an insulated gate field effect transistor, when a high voltage is applied to the gate, the gate insulating film may be destroyed. This dielectric breakdown phenomenon occurs not only when a high voltage is intentionally applied to the gate, but also when static electricity is charged. Therefore, some devices have a built-in protection diode to prevent dielectric breakdown. FIG. 1 is a cross-sectional structural diagram showing a conventional insulated gate field effect transistor incorporating a protection diode.
In FIG. 1, 1 is a P-type semiconductor substrate, which is an example of a so-called n-channel MOSFET. Gate electrode 1
0 is connected to the ohmic electrode 14 of the protection diode through the ohmic metal 12 and wiring metal. The protection diode junction is formed by 4 in the P ⁺ region and 5 in the N ⁺ region. The breakdown voltage of this P ⁺ n ⁺ junction is meaningless unless it is below the dielectric breakdown voltage of the gate, and it cannot operate as a transistor unless it is within the voltage range normally applied to the gate, for example 0 to 20 V or higher. The breakdown voltage of a P ⁺ n ⁺ junction is related to the impurity concentration or the junction depth.
The impurity concentration of the conventional P ⁺ region 4 can be controlled, or the spacing between regions 4 and 5 can be selected so that the impurity concentration is optimal when the P ⁺ and n ⁺ regions extend laterally and collide with each other due to diffusion. The breakdown voltage was controlled using the following method. As mentioned above, the conventional insulated gate field effect transistor as shown in FIG. 1 has the following drawbacks.

(1) It is necessary to form the P ⁺ region 4, which increases the number of steps.

(2) Since it is necessary to control the impurity concentration of the P ⁺ region 4 and requires advanced technology, it becomes expensive and also reduces the yield.

(3) Since the gate dielectric breakdown voltage depends on the thickness of the gate insulating film 6, it is necessary to change the conditions for forming the region 4 for each model with a different film thickness.

The present invention provides a novel structure of an insulated gate field effect transistor that solves the above-mentioned drawbacks of the conventional type, and provides an inexpensive and highly reliable insulated gate field effect transistor that can simplify the structure and manufacturing process. can be obtained.

The present invention will be explained in detail below using the drawings.

Example 1 FIG. 2 is a cross-sectional structural diagram showing an example of the present invention, and FIGS. 3 a to 3 d schematically show the manufacturing process thereof. Figure 3a shows well-known methods such as thermal oxidation.
This shows a state in which an oxide film is selectively formed in the peripheral area by photo-etching. b shows a gate oxide film formed by a well-known method on a portion where no oxide film was formed. 1. In c, a second gate electrode 16 is formed by laminating an electrically conductive film via an insulating film on the gate electrode 10 and a protective diode region, which is a feature of the present invention.

In this example, polysilicon was formed on the entire surface by a conventional CVD method, and then by conventional photo processing and etching. Using this polysilicon as a mask, the gate oxide film is removed by etching, and then a drain 2, a source 3, and an n ⁺ region 5 of a protective diode are formed by a conventional method, for example, a vapor phase diffusion method using POCl ₃ . At this time, phosphorus is also diffused into the polysilicon, and the resistance value of the polysilicon falls to a resistance value sufficient for use as an electrically conductive film for a gate. After that, an ohmic electrode metal such as Al is formed by a conventional method, and the result is as shown in FIG. Gate electrode 12
Although not particularly shown, and the electrode 14 of the protection diode are preferably connected to each other on the surface by Al wiring. The source electrode 13 is the second gate electrode 16
It is necessary to electrically couple the

In this example, the thickness of the insulating film 6 (gate oxide film) was 100 nm, and a voltage was applied between the source and the protection diode with the source short-circuited to the substrate 1, and the breakdown voltage of the protection diode was investigated. Approximately 35V
It was hot. It has been separately confirmed that the withstand voltage of the gate insulating film 6 is 50 V or more, and the gate applied voltage of this type of field effect transistor is in the range of 0 to 20 V, which is optimal as the breakdown voltage of the protective diode. was confirmed. Furthermore, when the gate oxide film thickness is 80 nm and 200 nm, the dielectric breakdown voltage is 40 V or more and 100 V or more, respectively, whereas the breakdown voltage of the protective diode is approximately
It was confirmed that the voltage automatically changed to 32V and 40V. Furthermore, the breakdown voltage in each case is independent of the impurity concentration of the P-type substrate 1 and is independent of the impurity concentration of the second gate electrode 16.
It was confirmed that this is related only to the thickness of the underlying insulating film 6'. For example, the thickness of the insulating film 6′ (oxide film) is 120 nm.
The impurity concentration of the P-type substrate 1 is approximately 5×10 ¹⁵
When the voltage was varied from cm ^-3 to 2×10 ¹⁴ cm ^-3 in experiments, the breakdown voltage remained constant at about 36V. The reason why the above-mentioned phenomenon occurs regarding the breakdown voltage is presumed to be as follows. In order to explain this, FIG. 4 is an enlarged view of the protective diode portion of FIG. 2. When a voltage is applied between the source and the gate, the protective diode is reverse biased and a depletion layer shown at 17 is formed. The width of the depletion layer is narrower near the surface due to the planar junction, but on the side A where the second gate electrode 16 is located, the width of the depletion layer is 16
Since it is used as a source, it becomes a ground potential and suppresses the expansion of the depletion layer. Therefore, the depletion layer becomes much narrower than in case B without the second gate electrode 16, and breakdown occurs at a lower voltage. The effect of this second gate electrode on suppressing the expansion of the depletion layer is that
It is determined not by the impurity concentration but by the thickness of the insulating film, that is, the oxide film, similar to the channel formation by the MOSFET gate electrode. It is believed that the phenomenon of the present invention is based on the above reasons. The second gate electrode 16 may cover the entire exposed surface of the PN junction of the protection diode, but if the PN junction has even one weak spot, breakdown will occur from that spot. Therefore, the second gate electrode 16 only needs to be formed in a portion.

Example 2 An example of application to a vertical MOSFET (hereinafter abbreviated as VDMOS) is shown in FIG. In the VDMOS, a portion corresponding to the base region 1 of Example 1 is formed of a diffusion layer,
It consists of a low concentration base region 1 necessary for channel formation and a high concentration and deep diffusion region 18 for increasing the breakdown voltage and improving the ohmic properties. When a protection diode is formed using the conventional method, the breakdown voltage of the diode is too low (usually 5 to 8 V) if the n ⁺ region for the diode is formed within the high concentration region 18, and the low concentration P-type region 1
If only the voltage is formed inside the capacitor, the breakdown voltage will become too high to be useful (usually 50 to 100 V). In the present invention, by forming the n ⁺ region 5 in the lightly doped P-type region 1 and providing the second gate electrode 16, it was possible to obtain the optimum breakdown voltage as in Example 1.

Although the explanation has been given above regarding the n-channel type using the P-type substrate region 1, it is natural that the present invention is also applied to the P-channel type using the n-type substrate. That is, in either case, equivalent conductivity type conversion is included within the scope of the present invention.

As described above, the insulated gate field effect transistor of the present invention has a built-in protective diode to effectively prevent electrical breakdown of the gate.
The structure and manufacturing process are simplified, and a product with high reliability can be provided at low cost, which is extremely effective in industry.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structural diagram of a conventional insulated gate field effect transistor, FIGS. 2 and 5 are cross-sectional structural diagrams of an embodiment of the present invention, and FIG. 3 is a manufacturing process diagram for the embodiment of FIG. 2. , FIG. 4 is an enlarged structural diagram of the protective diode portion of FIG. 2. 1 is a semiconductor substrate;
2 is a drain region, 3 is a source region, 4 is a region of the same conductivity type as the substrate of the protection diode, 5 is a region of opposite conductivity type to the substrate of the protection diode, 6 is a main gate insulating film, and 6' is a second gate insulator. Membranes, 7, 8 and 9
10 is a passivation insulating film, 10 is a main gate electrode, 11, 12, 13, 14 and 15 are ohmic metals, 16 is a second gate electrode, 17 is a depletion layer, and 18 is a high concentration region.

Claims (1)

[Claims] 1. A source, a drain, and a protective diode region of the same conductivity type are formed on one surface of a semiconductor substrate, and at least a part of the portion of the protective diode region where the PN junction is exposed on the one surface is covered with an insulating film. 1. An insulated gate field effect transistor comprising: a second gate electrode made of an electrically conductive film laminated on the substrate; and the second gate electrode is electrically connected to the source region.