JPH04367184A - Picture encoder - Google Patents

Abstract

PURPOSE:To uniformize a quantization distortion of a screen by equalizing an average minuteness of a processing unit with approximately that of an entire screen. CONSTITUTION:A memory 51 stores a picture data. An adder 53 adds a horizontal high frequency component of the picture data extracted by HPE 52h and 52v to a vertical one. A sorting circuit 55 sorts a block into four groups based upon the high frequency component. A memory 51 stores a block number for each group. A control circuit 57 divides the picture data stored in the memory 51 into blocks, where nXn pieces in spatial allocation are taken as one block, and controls so that a block ratio constituting a processing unit comes to be proportional to the number of blocks of each group when the picture data is read out of each processing unit consisting of the specified number of blocks. A DCT circuit 13 processes the picture data read out of each processing unit by a discrete cosine conversion to calculate a conversion coefficient. A quantization circuit 73 quantizes the conversion coefficient for outputting.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image encoding apparatus, and more particularly to an image encoding apparatus that encodes image data with high efficiency using discrete cosine transform.

0002

2. Description of the Related Art When transmitting image data or recording it on a recording medium such as a magnetic tape, various encoding methods are used to compress image information. For example, so-called predictive coding, transform coding, vector quantization, etc. are known.

[0003] By the way, the above-mentioned transform encoding utilizes the correlation that image signals have, transforms sample values (hereinafter referred to as image data) into mutually orthogonal axes, and decorrelates the correlation between image data. The so-called basis vectors are orthogonal to each other, the sum of the average signal power before conversion is equal to the sum of the average power of the so-called transformation coefficients obtained by orthogonal transformation, and the degree of power concentration in low frequency components is reduced. Excellent orthogonal transformations have been adopted, such as the so-called Hadamard transform, Haar transform, Kärnen-Louvé (K-L) transform, and discrete cosine transform (hereinafter referred to as DCT).
Discrete Sine Transform (hereinafter referred to as DST), Discrete Sine Transform (hereinafter referred to as DST)
rm), slant transformation, etc. are known.

[0004] Here, the above-mentioned DCT will be briefly explained. DCT divides an image into image blocks each consisting of n pixels (n×n) in both the horizontal and vertical directions in a spatial arrangement, and orthogonally transforms the image data within the image block using a cosine function. This DCT has come to be widely used for transmitting and recording image data due to the existence of a high-speed calculation algorithm and the realization of a one-chip so-called LSI that enables real-time conversion of image data. In addition, DCT has almost the same characteristics as the above-mentioned K-L transform, which is an optimal transform in terms of the degree of power concentration in low frequency components, which directly affects efficiency, in terms of encoding efficiency. Therefore, by encoding only the components in which power is concentrated in the transform coefficients obtained by DCT, it is possible to significantly reduce the amount of information as a whole.

Specifically, transform coefficients obtained by DCT of image data are expressed as, for example, Cij (i=0 to n-1, j=0
˜n−1), the transform coefficient C00 corresponds to a DC component representing the average brightness value within the image block, and its power is typically considerably larger than the other components. Therefore, when this DC component is coarsely quantized, so-called block distortion, which is noise peculiar to orthogonal transform coding, which is visually felt as a large deterioration in image quality, occurs. For example, the visual characteristic that the visual spatial frequency decreases at high frequencies is used for the conversion coefficients Cij (excluding C00) of other components other than the DC component (hereinafter referred to as AC components). The higher the frequency component, the lower the number of bits allocated to it for quantization.

In the transmission and recording of image data, after the transform coefficients obtained by DCT of the image data are quantized as described above, so-called Huffman coding and run-length coding are used for further compression. Variable length coding such as run length coding is applied, and a synchronization signal, parity, etc. are added to the resulting coded data for transmission or recording.

Furthermore, for example, in a digital video tape recorder (hereinafter simply referred to as a VTR) that records a video signal as a digital signal on a magnetic tape, the amount of data per frame or field is constant (fixed length) when editing, variable speed playback, etc. are taken into consideration. ), and considering the circuit scale, it is also desirable that the processing unit, which collects encoded data for a predetermined number of image blocks, has a fixed length. Therefore, in a VTR, multiple quantizers with different quantization widths are prepared, and under the condition that one quantizer is used for all image blocks within a processing unit, the amount of data per processing unit is is less than a predetermined value and the quantizer with the smallest quantization width is selected to perform quantization. this is,
If quantization is performed by switching and selecting a quantizer for each image block within a processing unit, the information of the quantizer used must be transmitted for each image block, which increases the amount of data (overhead). So this is to avoid that.

[0008]

[Problem to be solved by the invention] By the way, the conversion coefficient C
When the amount of quantized data obtained by quantizing ij is constant, the quantization width is a monotonous pattern, that is, the so-called fineness (Cij2, i, j≠0) defined by the power of the AC component (Cij2, i, j≠0). In an image block with a low activity (hereinafter referred to as "activity"), the conversion coefficient Cij has a high degree of concentration in low frequency components, and therefore becomes small. Therefore, if the same quantizer is used for each image block of one processing unit as described above, and the data amount of the processing unit is quantized to be constant, many image blocks with monotonous patterns will be included. The processing unit has a small quantization width, that is, it is finely quantized,
On the other hand, in a processing unit that includes many image blocks with complex patterns, the quantization will be coarse.

That is, depending on the picture, the activity of each processing unit may be biased, and the so-called quantization distortion may vary greatly depending on the processing unit (locally on the screen), giving a sense of discomfort.

The present invention has been made in view of the above circumstances, and uses the same quantizer for each block of a processing unit consisting of a predetermined number of blocks, and also uses a method in which the amount of data in the processing unit is constant. An object of the present invention is to provide an image encoding device capable of equalizing the quantization distortion of the screen by making the average definition of the entire screen approximately equal to the average definition of the processing unit when quantizing the image so that That is.

[0011]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides storage means for storing input image data, and image data stored in the storage means in a spatial arrangement of n×n pieces. A control means that divides the input image data into one block and reads out each processing unit consisting of a predetermined number of blocks; a high-pass filter that extracts high-frequency components of the input image data; and a control means that extracts the high-frequency components of the input image data from the high-pass filter. a classification means for classifying each block into a plurality of groups based on the size and controlling the control means so that the ratio of blocks constituting a processing unit is proportional to the number of blocks in each group; and processing from the storage means. discrete cosine transform means for orthogonally transforming the image data of each block read out in units using a cosine function to calculate transform coefficients;
It is characterized by comprising a quantization means for quantizing and outputting the transform coefficients from the discrete cosine transform means.

0012

[Operation] The image encoding device according to the present invention stores input image data, divides the stored image data into blocks each having n×n blocks in a spatial arrangement, and processes a predetermined number of blocks. When reading out each unit, each block is classified into multiple groups based on the size of the high-frequency component of the input image data, and the ratio of blocks constituting a processing unit is proportional to the number of blocks in each group. do. Then, the image data of each block read out for each processing unit is orthogonally transformed using a cosine function to calculate transformation coefficients, and the transformation coefficients are quantized and output.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of an image encoding apparatus according to the present invention will be described with reference to the drawings. FIG. 1 shows the circuit configuration of an image encoding device to which the present invention is applied, and FIG.
3 shows the circuit configuration of the recording system of a digital video tape recorder (hereinafter simply referred to as VTR) to which this image encoding device is applied, and FIG. 3 shows the circuit configuration of the reproduction system of the VTR.

First, this VTR will be explained. As shown in FIG. 2, this VTR converts an analog video signal into a digital signal, performs data processing such as so-called conversion encoding on the resulting image data, and compresses the data. A recording system for recording on the magnetic tape 1 and a magnetic head 31 from the magnetic tape 1 as shown in FIG.
and a reproduction system that binarizes the reproduced signal reproduced by the system, performs data processing such as decoding, converts it into an analog signal, and reproduces the analog video signal.

The above recording system, as shown in FIG.
An analog/digital converter (hereinafter referred to as an A/D converter) 11 samples a video signal and converts it into a digital signal to form image data, and the image data from the A/D converter 11 is The image is divided into image blocks Gh (h=0 to H, where H depends on the number of pixels in one frame or one field and the number of pixels in one image block n2), and a predetermined number of image blocks. A blocking circuit 1 that forms a processing unit that is, for example, one unit of data processing or transmission, consisting of Gh.
2, and the image data from the blocking circuit 12 is subjected to orthogonal transformation (hereinafter referred to as DCT) using a cosine function.
Cosine Transform) and transform coefficients Cij (i=0 to n-1,
A discrete cosine variable circuit (hereinafter referred to as DC
T circuit) 13, a quantization circuit 14 that quantizes the transform coefficient Cij from the DCT circuit 13 for each processing unit to form quantized data, and the quantized data from the quantization circuit 14, for example, The coded data VLCij (i=0 to n-1, j=0 to n-1) is encoded using a variable length code.
), a parity addition circuit 17 that adds parity for each processing unit, for example, for error detection or error correction, to the encoded data VLCij from the encoding circuit 15, and the parity addition circuit. Synchronization signal insertion in which an identification bit (hereinafter referred to as ID) for identifying the synchronization signal and the number h of the image block Gh, etc. is added to the encoded data VLCij to which parity has been added from No. 17 for each processing unit to form transmission data. A circuit 18, a parallel/serial (hereinafter referred to as P/S) converter 19 that converts transmission data sent as parallel data from the synchronization signal insertion circuit 18 into serial data, and a For example, so-called scramble or NRZI
A recording signal is generated by performing modulation processing, and the magnetic head 2
1 and a channel encoder (hereinafter referred to as ENC) 20.

[0016] After converting the video signal supplied as an analog signal through the terminal 2 into image data, this recording system divides, for example, one frame or one field worth of image data into image blocks Gh. DCT the image data of the image block Gh to calculate the transform coefficient Cij, quantize the transform coefficient Cij for each processing unit to form quantized data, and encode the quantized data using a variable length code. Data VLCij is formed. In addition, this recording system adds a synchronization signal etc. to encoded data VLCij for each processing unit to form transmission data, and then performs modulation suitable for recording on this transmission data, such as scrambling or NRZI modulation processing, and then performs magnetic Recording is performed on the magnetic tape 1 by the head 21.

[0017] Thus, the image encoding device according to the present invention,
That is, the main part of the VTR configured as described above is composed of the blocking circuit 12 to the quantizing circuit 14, and specifically, the configuration is as follows.

As shown in FIG. 1, for example, the blocking circuit 12 has a storage capacity for one frame or one field, and includes a memory 51 for storing image data, and a memory 51 for storing high-frequency components of the image data in the horizontal direction. a high-pass filter (hereinafter referred to as HPF) 52h that extracts vertical high-frequency components of image data;
an adder 53 that adds the output of the PF 52h and the output of the HPF 52v to calculate the so-called fineness (hereinafter referred to as activity) Ah (h=0 to H) of each image block Gh;
Comparators 54a, 54b, 54c that compare the activity Ah from the adder 53 with predetermined thresholds TH1, TH2, TH3, respectively; and the comparators 54a, 54b.
, 54c, and a classification circuit 55 that classifies each image block Gh into a plurality of groups based on the outputs of
When reading out the image data from the memory 56 which stores the numbers h of the image blocks Gh classified for each group and the memory 51 into image blocks Gh each having n×n blocks in the spatial arrangement, Memory 5 above
A control circuit that controls the memory 51 based on the number h of the image blocks Gh that are stored and classified into groups in 6, so that the ratio of the image blocks Gh constituting the processing unit is proportional to the number of image blocks in each group. It consists of 57.

The blocking circuit 12 sequentially stores the image data supplied through the terminal 4 in the memory 51, and extracts high frequency components in the horizontal and vertical directions of the image data to form each image block. An activity Ah of Gh is calculated, and each image block Gh is classified into a plurality of groups based on this activity Ah. When the image data is divided and read out from the memory 51 into image blocks Gh in which n×n pieces in the spatial arrangement constitute one block, the images constituting the processing unit are determined based on the number h of the classified image blocks Gh. Block Gh
The image data of the read image block Gh is supplied to the DCT circuit 13.

Specifically, HPF52h, HPF52v
extracts, for example, a horizontal high-frequency component and a vertical high-frequency component of the luminance signal Y of the image data supplied as the so-called luminance signal Y and color difference signals U and V via the terminal 4, respectively, and sends them to the adder 53. supply to.

The adder 53 calculates the activity Ah of each image block Gh by adding the horizontal high frequency component and the vertical high frequency component, and calculates the activity Ah of each image block Gh.
h to comparators 54a-54c.

Comparators 54a to 54c have threshold values TH1, TH2, TH3 (TH1
>TH2 >TH3) and the activity Ah from the adder 53, and the comparison result is sent to the classification circuit 5.
Supply to 5.

The classification circuit 55 classifies each image block Gh into four groups, for example, based on the comparison results of the comparators 54a to 54c.
The number h of the image block Gh included in each group #1 to #4 is divided into three groups #1, #2, #3, and #4 (the group with the lower number has the highest activity Ah).
are stored in the memory 56 for each group.

The control circuit 57 stores the image data recorded in the memory 51 in a spatial arrangement of, for example, 8×8 pieces.
When dividing into image blocks Gh and reading out each processing unit, groups #1 to Gh are stored in the memory 56.
Based on the number h of the image block Gh classified and stored as #4, the image block G constituting the processing unit is
The image data of the read image block Gh is read out so that the ratio of h is proportional to the number of image blocks in each group #1 to #4, and the image data of the read image block Gh is supplied to the DCT circuit 13. For example, the number of image blocks of each group #1 to #4 stored in the memory 56 is set to 100, 300, and 500, respectively.
, 1000, and these image blocks Gh are 1
00 processing units, each processing unit is 1 (=
100÷100) pieces, 3 pieces, 5 pieces, and 10 pieces. Further, the control circuit 57 is configured to output the number h of the image block Gh constituting the processing unit via the terminal 58.

The DCT circuit 13 is, for example, a so-called DSP.
(Digital Signal Processor
), etc., and the image data supplied from the blocking circuit 12 for each processing unit is orthogonally transformed using the cosine function as described above to calculate the transformation coefficient Cij, and this transformation coefficient Cij is sent to the quantization circuit. 14.

The quantization circuit 14 has different quantization widths, as shown in FIG. It is composed of quantizers Qm (m=1 to M) that each form quantized data of a data amount, and forms quantized data of a different amount of data for the same processing unit for each processing unit. The encoded data is supplied to the encoding circuit 15.

Specifically, the quantizer Qm converts the transform coefficients Cij of the image block Gh, as shown in FIG.
For example, the quantizer Q1 performs quantization with a predetermined quantization width q in the three regions 81, 82, and 83, and the quantizer Q2 performs quantization with a predetermined quantization width q. , quantization is performed with a quantization width q in regions 81 and 82, and quantization is performed with a quantization width 2q in the region 83. For example, the quantizer Q3 performs quantization with a quantization width q in the region 81, and , quantization is performed with a quantization width of 2q in the regions 82 and 83, for example, the quantizer Q4
has a quantization width of 2 in the three regions 81, 82, and 83.
Quantization is performed using q, and quantization data with different amounts of data are formed for the same processing unit.

As shown in FIG. 1, the encoding circuit 15 uses, for example, a so-called Huffman code (
Huffman code) and run-length code (R
un Length code), etc.
an encoder CODm (m=1 to M) that encodes the quantized data from each of the quantizers Qm using a variable length code to respectively form encoded data VLCij;
A buffer memory BUFm (m=1 to M) which stores encoded data VLCij from each encoder CODm in each processing unit and has a predetermined storage capacity, and codes read from each buffer memory BUFm. It is comprised of a selector 61 that selects one of the quantized data VLCij, and a control circuit 62 that controls the selector 61 using a quantizer selection signal, which will be described later, obtained by detecting the overflow of each of the buffer memories Bm.

The encoding circuit 15 encodes different amounts of quantized data from each quantizer Qm using a Huffman code and a run-length code, and encodes different amounts of data for the same processing unit. encoded data VLCij are respectively stored in buffer memories BUFm, and these encoded data VLCij are respectively stored in buffer memories BUFm.
A quantizer selection signal for detecting an overflow of m and selecting a quantizer Qm that does not cause an overflow and has the maximum amount of data, that is, a quantizer Qm
The coded data VLCij selected by the selector 61 is outputted to the parity addition circuit 17 shown in FIG. 2 through the terminal 5. Further, this encoding circuit 15 includes a selector 61
The number m of the quantizer Qm selected in is supplied to the parity addition circuit 17 via the terminal 63.

As a result, the selector 61 outputs encoded data V that has been quantized with the minimum quantization width so that the amount of data per processing unit falls within a predetermined amount and the amount of data is maximized.
LCij is output. At this time, the ratio of image blocks Gh constituting the processing unit is set for each group #1
~ #4 The ratio of the number of image blocks, that is, the ratio of the image blocks Gh of the entire screen classified by the size of the activity Ah, so one processing unit includes an image block Gh with a low activity Ah or an image block with a high activity Ah. It is possible to avoid bias in the activities Ah, where more Gh than others are included, and it is possible to equalize the quantization distortion of the screen. In other words, a processing unit consisting of a predetermined number of image blocks Gh has a fixed length, and can be quantized to the finest extent within the amount of data allowed for the processing unit, and the average activity Ah of the entire screen and the average activity of the processing unit can be Ah can be made almost equal, and the quantization distortion of the screen can be made uniform, eliminating the discomfort caused by the large difference in quantization distortion for each processing unit (locally on the screen) seen in conventional devices. It can be eliminated.

The parity addition circuit 17 and synchronization signal insertion circuit 18 shown in FIG.
The number h of the image block Gh constituting the processing unit from
The encoded data VLCij from the encoding circuit 15 and the number m of the selected quantizer Qm are time-division multiplexed, and
Parity and synchronization signals are added to form transmission data. As a result, for example, one processing unit includes a synchronization signal, an ID, a number h of an image block Gh constituting the processing unit, a number m of a quantizer Qm employed in the processing unit, a predetermined number of image blocks Gh encoded data VLCij,
Transmission data consisting of parity is output.

As described above, this image encoding device temporarily stores the image data supplied through the terminal 4 in the memory 51, and stores the stored image data in a spatial arrangement of n×
After dividing the image into image blocks Gh with n blocks as one block, reading out each processing unit consisting of a predetermined number of blocks, and performing DCT on the image data of each image block Gh,
The obtained transform coefficient Cij is quantized using a quantizer Qm whose processing unit has a fixed length and whose quantization width is the minimum within the data amount allowed for the processing unit, and this quantized data is converted into a variable length code. and the resulting encoded data VLCij
When outputting through terminal 5, the high-frequency components of the image data are extracted and the activity Ah of each image block Gh is calculated.
, each block is classified into multiple groups based on the size of the activity Ah, and the ratio of image blocks Gh constituting a processing unit is proportional to the number of image blocks in each group. There is no bias in the activity Ah in processing units, the quantization distortion of the screen can be made uniform, and a video signal of good image quality that does not give an unnatural feeling during playback can be obtained.

Next, the reproduction system of this VTR will be explained. As shown in FIG. 3 above, this reproduction system includes a channel decoder (hereinafter simply referred to as DEC) that performs signal processing such as NRZI demodulation on the reproduction signal reproduced from the magnetic tape 1 by the magnetic head 31 to reproduce transmitted data. 32
and a serial/parallel (hereinafter referred to as S/P) converter 33 that converts the transmission data sent as serial data from the DEC 32 into parallel data, and the synchronization of the transmission data from the S/P converter 33. In addition, a synchronization signal detection circuit 34 that reproduces the encoded data VLCij
and a time axis correction circuit (hereinafter referred to as TBC: Ti
base corrector) 35, an error correction circuit 36 that performs error correction on the encoded data VLCij from the TBC 35, and sets an error flag EF for the encoded data VLCij for which error correction could not be made; Encoded data VLCij that has been variable length encoded during recording from the circuit 36
a decoding circuit 37 that decodes the quantized data to reproduce the quantized data, and an inverse quantization circuit 38 that performs signal processing such as inverse quantization on the quantized data from the decoding circuit 37 to reproduce the transform coefficient Cij. an inverse discrete cosine transform circuit (hereinafter referred to as IDCT circuit) 39 that orthogonally transforms the transform coefficient Cij from the inverse quantization circuit 38 to reproduce image data; and the IDCT circuit 3
a deblocking circuit 40 that forms image data for one frame or one field from the image data supplied for each image block Gh from 9; and the error correction circuit 3.
an error correction circuit 41 that performs error correction on the image data from the deblocking circuit 40 based on the error flag EF from 6, and a digital/digital converter that converts the image data from the error correction circuit 41 into an analog signal and outputs it It is composed of an analog converter (hereinafter referred to as a D/A converter) 42.

Next, the operation of the reproduction system configured as described above will be explained. The DEC 32 binarizes the reproduction signal reproduced from the magnetic tape 1 by the magnetic head 31, performs NRZI demodulation, performs descramble processing to reproduce the transmission data, and converts this transmission data into S/
It is supplied to the synchronization signal detection circuit 34 via the P converter 33.

The synchronizing signal detection circuit 34 is connected to the S/P converter 3.
A synchronization signal is detected from the transmission data converted to parallel data in step 3, synchronization is pulled in, and the encoded data VL
Cij and convert this encoded data VLCij to TBC.
35.

The TBC 35 performs time axis correction on the encoded data VLCij, absorbs fluctuations in the time axis that occur during reproduction, and supplies the time axis corrected encoded data VLCij to the error correction circuit 36.

The error correction circuit 36 converts the encoded data VL
Cij error correction is performed using the parity added during recording, and an error flag EF is set for encoded data VLCij that has an error exceeding the error correction capability.
and the error-corrected encoded data VLCij
is supplied to the decoding circuit 37.

[0038] The decoding circuit 37 decodes the encoded data VLCij encoded by the Huffman code and run-length code during recording and reproduces the quantized data.
This quantized data is supplied to an inverse quantization circuit 38.

The inverse quantization circuit 38 converts the encoded data VLC
Based on the number m of the quantizer Qm of each processing unit reproduced together with ij and the number h of the image block Gh constituting each processing unit, the quantizer Qm of each processing unit used during recording and each Recognize the image block Gh of the processing unit, inversely quantize the quantized data of each processing unit with the quantization width corresponding to these quantizers Qm, reproduce the transform coefficient Cij, and apply the transform coefficient Cij to the IDCT circuit. 3
Supply to 9.

The IDCT circuit 39 calculates the transformation coefficients Cij using a transposed matrix corresponding to the transformation matrix used during recording.
is orthogonally transformed to reproduce the image data for each image block Gh, and this image data is supplied to the deblocking circuit 40.

The deblocking circuit 40 converts the image block G
One frame or one field of image data is formed from the image data reproduced every h and is supplied to the error correction circuit 41.

The error correction circuit 41 performs an interpolation process using, for example, error-free image data adjacent to the image data for which the error cannot be corrected in the error correction circuit 36, so that the error cannot be corrected for the image data. The error is corrected, and the image data with this error corrected is supplied to the D/A converter 42.

The D/A converter 42 converts the error-corrected image data into an analog signal, and outputs the analog video signal from the terminal 3 as, for example, a luminance signal Y and color difference signals U and V.

As described above, at the time of recording, the activity Ah is set so that the average activity Ah of the processing unit is approximately equal to the average activity Ah of the entire screen based on the activity Ah of the image block Gh of the processing unit. By mixing image blocks Gh and image blocks Gh with low activity Ah, and recording the number h of the image blocks Gh constituting each processing unit and the number m of the quantizer Qm used in each processing unit. By performing the above-described reproduction using these pieces of information during reproduction, it is possible to reproduce a video signal of good image quality with uniform quantization distortion.

[0045]

Effects of the Invention As is clear from the above description, in the present invention, input image data is temporarily stored, and the stored image data is divided into blocks each having n×n pieces in the spatial arrangement. The image data of each read block is orthogonally transformed using a cosine function to calculate the transform coefficients, and when the transform coefficients are quantized and output, the input image data is By extracting high-frequency components, classifying each block into multiple groups based on the size of this high-frequency component, and controlling the ratio of blocks constituting a processing unit in proportion to the number of blocks in each group, The definition of each processing unit is not biased and can be made approximately equal to the average definition of the entire screen, and the quantization distortion of the screen can be made uniform, so that good image quality without any discomfort can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a circuit configuration of an image encoding device to which the present invention is applied.

FIG. 2 is a block diagram showing a circuit configuration of a recording system of a digital video tape recorder to which the above image encoding device is applied.

FIG. 3 is a block diagram showing a circuit configuration of a reproduction system of a digital video tape recorder to which the above image encoding device is applied.

FIG. 4 is a diagram showing a region of transform coefficients for explaining the quantization width of a quantizer constituting the image encoding device.

[Explanation of symbols]

12...Blocking circuit 52h, 52v...High pass filter 55...Classification circuit 57...Control circuit 13...DCT circuit 14...Quantization circuit Qm...Quantizer

Claims (1)

[Claims] 1. Storage means for storing input image data, and processing for dividing the image data stored in the storage means into blocks in which one block is n×n in a spatial arrangement and consisting of a predetermined number of blocks. a control means for reading out each unit; a high-pass filter for extracting high-frequency components of input image data; and classifying each block into a plurality of groups based on the magnitude of the high-frequency components of the input image data from the high-pass filter; a classification means for controlling the control means so that the ratio of blocks constituting a processing unit is proportional to the number of blocks in each group; Discrete cosine transform means for calculating transform coefficients by orthogonal transform using
and quantization means for quantizing and outputting transform coefficients from the discrete cosine transform means.