JPH04365290A - Color separation circuit - Google Patents

Abstract

PURPOSE:To obtain the suitable color separation circuit by digitizing. CONSTITUTION:A scan line dot sequentially containing a sum signal C1 of Mg and Ye components and a sum signal C2 of Gr and Cy components and a scan line dot sequentially containing a sum signal C3 of Mg and Cy components and a sum signal C4 of Gr and Ye components are inputted from an imaging device. The inputted signals are synchronized by a IH delay line 2 and a switch 3 as a signal containing only the C1 and C2 and a signal containing only the C3 and C4. One of the synchronized signals is converted into an R signal by sample/hold circuits 4 and 5, multiplier circuit 6 and adder circuit 7, and the other signal is converted into a B signal by S/H circuits 8 and 9, multiplier circuit 10 and adder circuit 11. The output of the imaging device and the output of the 1H delay line 2 are added by an adder circuit 12, synchronized and converted into a G signal by S/H circuits 13 and 14, multiplier circuit 15 and adder circuit 16. The number of adder/subtracting circuits and multiplier circuits can be reduced in comparison with the conventional circuit.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to a color separation circuit used in an imaging device such as a color video camera.
In particular, the present invention relates to a color separation circuit suitable for digitizing imaging devices.

0002

2. Description of the Related Art FIG. 8 is a block diagram of a video camera using an imaging device such as a CCD. Referring to FIG. 8, this video camera includes an optical system 32 for condensing incident light from a subject to form an image of the subject on a predetermined image forming plane, and an optical system 32 for forming an image of the subject on a predetermined imaging plane, and an optical system 32 for converting the image of the subject into an image by photoelectric conversion. An image sensor 1 for converting into a signal and outputting it, an LPF (low pass filter) 33 for extracting a luminance signal Y component from an image signal output from the image sensor 1, and a γ for the luminance signal Y output from the LPF 33. A γ correction circuit 34 for performing correction and a γ correction circuit 34 that processes the image signal output from the image sensor 1 to produce color difference signals R-Y, B.
-Y, and an encoder 35 to encode the luminance signal Y, color difference signals RY, BY, and output them as a composite video signal.

Details of the color signal processing circuit 35 will be described later. FIG. 9 is a schematic block diagram of the image sensor 1. As shown in FIG. Referring to FIG. 9, the image sensor 1 is arranged in a matrix in the horizontal and vertical directions, and one of cyan (Cy), magenta (Mg), yellow (Ye), and green (Gr) color filters is arranged on the image sensor 1. a photosensor 43 formed on the top of the photosensor 43 for generating and accumulating a charge corresponding to a predetermined color component of incident light according to the spectral characteristics of each color filter; A vertical shift register CCD44 for reading out the accumulated charges and sequentially transferring them in a predetermined direction, and a vertical shift register C
The ends of the CDs 44 in the charge transfer direction are connected to each vertical shift register CCD 44, and the vertical shift register C
A horizontal shift register CCD45 is connected to the output of the horizontal shift register CCD45 for transferring the number of horizontal pixels of the charges transferred by the CD44 in a predetermined direction within a horizontal scanning period (1H: 64 μsec). and an output section 46 for sequentially outputting a potential Vout according to the amount of charge. Each vertical shift register CC
D44 is externally supplied with vertical register transfer clocks Vφ1 to Vφ4 for driving each shift register CCD44 to transfer charges in a predetermined direction. The horizontal shift register CCD45 has horizontal register transfer clocks Hφ1 and Hφ2 for transferring the charges in the horizontal shift register CCD45 toward the output section 46 within 1H, and the output section 4.
Horizontal shift register CCD for transferring charge to 6
A horizontal final stage transfer clock LHφ1 supplied to the horizontal final stage of 45 is supplied from the outside. The output section 46 includes a charge detection capacitor (not shown), and this capacitor is initialized by an externally applied reset gate clock RG. The potential Vout output from the output section 46 is obtained by amplifying the potential output from the charge detection capacitor described above by an output amplifier (not shown).

Referring to FIG. 10, the color filters formed on the photosensor are arranged in a mosaic shape as shown in FIG. That is, rows in which photosensors in which Mg color filters are formed and photosensors in which Gr color filters are formed are arranged alternately in the horizontal scanning direction, and photosensors in which Ye color filters are formed, There are rows in which photosensors on which Cy color filters are formed are arranged alternately, and these two types of rows are arranged alternately in the vertical direction. The arrays of Ye and Cy are alternated depending on the row.

Charge reading is performed in the following format. As is well known, in the current NTSC system image signal processing, so-called "interlaced scanning" is performed. For example, a field consisting only of odd-numbered horizontal scanning lines (hereinafter referred to as "A field") and a field consisting only of even-numbered horizontal scanning lines (hereinafter referred to as "B field") are alternately processed. In the image sensor 1, charges are read out in the following manner according to such a system.

In field A, as shown at the right end of FIG. 10, the n-th horizontal scanning line is a photosensor formed with Mg and Ye, Gr and Cy color filters arranged in two adjacent rows. The accumulated charges are read out and mixed together. The signal of the n+1th horizontal scanning line is Mg, Cy, and Gr from the array of the following two photosensors.
Similarly, the charges accumulated in the photosensors of and Ye are mixed and read out. On the other hand, in the B field, the arrangement of the photosensors to be mixed is shifted by one stage from that in the A field. That is, as shown at the left end of FIG. 10, one of the two arrays outputs the signal of the n-th horizontal scanning line of the A field, and the signal of the n+1-th horizontal scanning line is output. One of the two arrays is combined, and the accumulated charges of adjacent photosensors between each array are read out, mixed, and transferred. That is,
In the B field, the image signal output from the image sensor 1 is Y
A horizontal scanning line is formed by dot-sequentially arranging a signal in which the e and Mg color components are mixed and a signal in which the Cy and Gr color components are mixed, and each color component of Cy, Mg, Ye and Gr is The mixed signal and the horizontal scanning line formed by arranging the mixed signals in dot-sequential manner are arranged in line-sequential manner. therefore,
In order to create a color video signal, the problem is how to create color difference signals RY and BY from these color components.

Referring again to FIG. 8, the color signal processing circuit 35
is for processing the image signal output from the image sensor 1 and outputting color difference signals R-Y, B-Y, and converts the image signal output from the image sensor 1 into three primary color signals R, B, G.
A color separation circuit 31 for outputting signals R and R, respectively.
R amplification circuit 36 for amplifying B and G at a predetermined amplification factor
, B amplifier circuit 37, G amplifier circuit 38, and γ correction circuits 39 and 4 for performing γ correction on signals output from R amplifier circuit 36, B amplifier circuit 37, and G amplifier circuit 38, respectively.
0, 41, and the signals R, B, and G given from the γ correction circuits 39, 40, and 41, a color difference matrix circuit 4 that performs predetermined calculations and outputs color difference signals R-Y, B-Y.
2. Among these circuits, the color separation circuit 31 is the circuit targeted by the present invention.

As shown in FIG. 10, in the A field, the n-th horizontal scanning line is a sum signal of Ye and Mg and a sum signal of Cy and Gr arranged dot-sequentially. Further, the (n+1)th horizontal scanning line signal of the A field is a signal in which a sum signal of Cy and Mg and a sum signal of Ye and Gr are arranged dot-sequentially. On the other hand, the n-th horizontal scanning line of the B field is a sum signal of Mg and Ye, and a G
The sum signal of r and Cy is arranged point-sequentially. The n+1st horizontal scanning line of the B field is Mg and C.
The sum signal of Gr and Ye and the sum signal of Gr and Ye are arranged point-sequentially. These dot-sequentially arranged signals can be separated from each other by sampling at timings determined by two sample-and-hold pulses SHP1 and SHP2 shown at the bottom of FIG.

Referring to FIG. 11, a conventional color separation circuit 31
are connected to the image sensor 1, and sample and hold the image signal given from the image sensor 1 with pulses SHP1 and SHP1, respectively.
A first sample hold circuit 21 and a second sample hold circuit 22 for sampling according to SHP2, a subtraction circuit 23 for subtracting the signal output from the sample hold circuit 22 from the output of the sample hold circuit 21, and a subtraction circuit. A 1H delay line 24 for delaying the signal output by 23 by 1H is connected to the output of the subtraction circuit 23 and the output of the 1H delay line 24, and the output of the subtraction circuit 23 and the output of the 1H delay line 24 are connected every 1H. By alternately selecting and outputting two color difference signals Ery and E
A switch 25 for outputting by and an adding circuit 27 for adding the outputs of the sample and hold circuits 21 and 22.
and a 1H delay line 28 for delaying the output of the adder circuit 27 by 1H, and the output of the adder circuit 27 and the output of the adder circuit 27 delayed by 1H by the 1H delay line 28 are added together and output as a luminance signal Y. By performing a predetermined calculation on the two color difference signals Ery and Eby outputted from the switch 25 and the luminance signal Y given from the addition circuit 29, the three primary color signals RBG are output. matrix circuit 26.

Referring to FIG. 12, the matrix circuit 26 applies a predetermined coefficient K3 to the color difference signals Ery and Eby, respectively.
, K4 and outputs the multiplication circuits 68 and 69.
and the signal K3 Ery output from the multiplier circuits 68 and 69,
An addition circuit 70 for adding K4 Eby, a subtraction circuit 71 for subtracting the output of the addition circuit 70 from the luminance signal Y and outputting the signal G, and multiplying the luminance signal Y by predetermined coefficients K1 and K2, respectively. multiplication circuits 65 and 67 for outputting the signal R, and an addition circuit 64 for adding the output of the multiplication circuit 65 to the color difference signal Ery and outputting the result as a signal R.
and an addition circuit 66 for adding the output of the multiplication circuit 67 to the color difference signal Eby and outputting the result as a signal B.

First, the principle of color separation performed in this circuit will be explained. From the image sensor 1 to the sample hold circuit 21
, 22 is expressed as follows.

0012

[Math 1]

As shown in FIG. 13(a), the output of the image sensor 1 is a dot-sequential signal of C1 and CC2 on the n-th line;
The (n+1)th line is a point sequential signal of C3 and C4. 1st
The sample and hold circuit 21 samples and holds the input signal according to the sample and hold pulse SHP1 shown in FIG. Therefore, the sample-and-hold circuit 21 samples and holds C1 on the n-th line and C3 on the (n+1)-th line, and outputs them. Sample hold circuit 21
The output of is shown in FIG. 13(b).

The sample and hold circuit 22 samples and holds the input signal according to the sample and hold pulse SHP2 shown in FIG. Therefore, sample and hold circuit 2
2 samples and holds the C2 signal on the n-th line and the C4 signal on the (n+1)-th line, and outputs the sample-and-hold signal. This state is shown in Figure 13(c).
is shown.

The output of the subtraction circuit 23 is as follows.

[0016]

[Math 2]

The above signal is shown in FIG. 13(d). The output of the adder circuit 27 is as follows.

[0018]

[Math 3]

The output signal of the adder circuit 27 is shown in FIG. 13(h). The three primary colors of light are r (red), g (green), and b (
(blue), Mg, Ye, Gr, and Cy are expressed as follows.

[0020]

[Math 4]

By substituting equations (9) to (12) into equations (5) to (8), the following equations (13) to (16) are obtained.

[0022]

[Math 5]

On the other hand, the luminance signal Y(
R-Y) color difference signal Ery and (B-Y) color difference signal Eb
It is common practice to approximate y as shown in the following equation.

[0024]

[Math 6]

By referring to equations (5), (6), (17), and (18), the color difference signal E is output from the subtraction circuit 23.
It can be seen that ry and Eby are obtained as line sequential signals. On the other hand, by referring to equations (7), (8), and equation (19), it can be seen that a Y signal is obtained at the output of the adder circuit 27.

The switch 25 forms a pre-interpolation circuit together with the 1H delay line 24, and the two switches 48 and 49
including. One of the inputs of the switch 48 is connected to the arithmetic circuit 23,
The other end is connected to the 1H delay line 24. switch 49
The two inputs of are similarly connected to the output of the subtraction circuit 23 and the output of the 1H delay line 24. Switches 48, 49
are constructed so that their operations are complementary. That is, when the switch 48 selects the output of the subtraction circuit 23, the switch 49 selects the output of the 1H delay line 24. When the switch 48 selects the output of the 1H delay line 24, the switch 49 selects the output of the subtraction circuit 23.

As mentioned above, the 1H delay line 24 and the switch 25
form a pre-interpolation circuit, and converts the Ery/Eby line sequential signal given as the output of the subtraction circuit 23 into successive Ery and Eb signals by switches 48 and 49, respectively.
This is for outputting as a y signal. 1H delay line 2
4 delays the output of the subtraction circuit 23 by 1H, and as shown in FIG.
) and is applied to the switch 25. The switch 48 selects only the C1-C2 signal from among the outputs of the subtraction circuit 23 and the 1H delay line 24. Therefore switch 4
A continuous Ery signal (C1-C2) is obtained as the output of 8. This signal is shown in FIG. 13(f). On the other hand, the switch 49 selects only the C3-C4 signal from the output of the subtraction circuit 23 and the output of the 1H delay line 24. As a result, the output of the switch 49 is a continuous Eby signal (C
3-C4) is obtained. This signal is shown in FIG. 13(g).

As described above, in order to obtain color difference signals, interpolation is performed on the line sequential signals output from the image pickup device. Therefore, the vertical resolution of the color difference signal is degraded compared to the luminance signal Y if left as is. Therefore, it is necessary to match the resolution of the Y signal to the resolution of the color difference signal. The 1H delay line 28 and adder circuit 29 form a vertical filter for this purpose. That is, addition circuit 2
The Y signal output from 7 is
It is delayed by H and added to the Y signal again by the adder circuit 29. Thereby, the resolution of the Y signal is matched to the resolution of the color difference signal. The output of the adder circuit 27 is shown in FIG. 13(i). Therefore, the output of the adder circuit 29 is as shown in FIG.
3(j), it is expressed by the following formula.

[0029]

[Math 7]

The color difference signal Ery obtained as above
, the color difference signal Eby, and the luminance signal Y are the matrix circuit 2.
6 and is converted into three primary color signals R, G, and B.

Referring to FIG. 12, matrix circuit 26 operates as follows. The three primary color signals are R, G,
It is well known that the following relationships hold between R, G, B and Ery, Eby, and Y.

[0032]

[Math. 8]

By transforming equations (21) to (23), the following equations (24) to (26) are obtained.

[0034]

[Math. 9]

Y, E obtained from formulas (17) to (19)
By substituting ry and Eby into equations (24) to (26), three primary color signals R, G, and B signals can be obtained. However, due to the characteristics of the image sensor, it is actually difficult to obtain values according to the above theory, so the relative levels of the signals Y, Ery, and Eby obtained according to equations (17) to (19) are It is different from Y, Ery, and Eby in formulas (21) to (23). Therefore, usually the following equations (27) to (29)
R, B, and G are separated using the coefficients K1, K2, K3, and K4 as described above.

[0036]

[Math. 10]

The above-mentioned coefficients K1 to K4 are coefficients determined by the image pickup device. Matrix circuit 2 shown in FIG. 12 realizes equations (27) to (29) using a circuit.
It is 6. Referring to FIG. 12, matrix circuit 26 operates as follows. The output signal Ery of the switch 25,
Eby and the Y signal output from the adder circuit 29 (both shown in Figure 1
1) are the adder circuit 64 and the multiplier circuit 6, respectively.
8, is applied to an adder circuit 66, a multiplier circuit 69, and a subtracter circuit 71. The signal Ery is multiplied by the coefficient K by the multiplier circuit 68.
3 is multiplied by 3 and provided to the adder circuit 70 as K3 Ery. The signal Eby is multiplied by the coefficient K4 by the multiplication circuit 69.
is multiplied by K4 Eby and provided to the adder circuit 70. The adder circuit 70 adds the two input signals and provides the result to the subtracter circuit 71 as (K3.Ery+K4.Eby). The subtraction circuit 71 subtracts the output of the addition circuit 70 from the Y signal, thereby outputting a signal G shown by equation (29).

On the other hand, the Y signal is multiplied by a coefficient K1 by a multiplier circuit 65 and is provided as K1Y to an adder circuit 64. The adder circuit 64 adds K1 Y to the signal Ery and outputs the signal R shown in equation (27). The Y signal is also multiplied by a coefficient K2 by the multiplication circuit 67, and the Y signal is
2 Y to the adder circuit 66. Addition circuit 66
adds the signal Eby and the output of the multiplier circuit 67, and formula (
28).

As described above, the R, G, and B signals are separated from the signal output from the image sensor 1.

[0040]

However, when the above-mentioned conventional color separation circuit is digitized, there is a problem in that the circuit becomes extremely large in scale. For example, Figure 1
Including the matrix circuit 26 shown in FIG. 12, the color separation circuit 1 has two sample and hold circuits and a 1H
Two delay lines, seven adder or subtractor circuits, and four multiplier circuits are required. Of these, apart from sample and hold circuits and 1H delay lines, multiplication circuits, addition circuits, subtraction circuits, etc. are relatively small in analog signal processing due to variable resistors, mixing circuits with resistors, inverting amplifiers, and addition circuits. This can be realized with a large-scale circuit.

For example, referring to FIG. 14, the adder circuit is realized by resistors 50 and 51 having resistance values R1 and R2, respectively. The signal A is input to one end of the resistor 50,
It is assumed that a signal B is input to one end of the resistor 51. The other ends of each of the resistors 50 and 51 are connected to each other,
connected to the output terminal. In the circuit of Fig. 14,
A signal C defined by the following equation is obtained at the output terminal.

[0042]

[Math. 11]

In other words, in the analog circuit, as shown in FIG.
Addition processing can be performed with an extremely simple circuit as shown in .

However, if an attempt is made to implement the adder circuit using a digital circuit, the circuit will become extremely large-scale. For example, FIG. 15 shows an example of a carry-ahead 4-bit adder. The 4-bit adder shown in FIG. 15 consists of two 4-bit numbers a1a2a3a4, b1b2b3
b4 and a carry signal c0 from the lower multiplier, and outputs the result of addition of two numbers x1x2x3x4 and a carry signal c4 to the upper adder. Referring to FIG. 15, this carry look-ahead 4-bit adder includes an inverter 101 to which a carry signal c0 is input;
NOR circuit 102 and NOR circuit 102 to which signals a1 and b1 are input, respectively
An AND circuit 103, a NOR circuit 104 and a NAND circuit 105 to which signals a2 and b2 are respectively input, and a signal a2 and a
3 and b3, and a NOR circuit 108 and a NAND circuit 109 to which signals a4 and b4 are input, respectively.

The adder shown in FIG. 15 further has an NA input to one input to obtain the least significant bit x1 of the addition result.
The output of the ND circuit 103 is the input of the NOR circuit 102.
AND gate 111 to which the inverted output of
, an inverter 110 whose input is connected to the output of the inverter 101, and an AND gate 11 whose two inputs are connected to the output of the inverter 101, respectively.
1 and an EXOR circuit 133 connected to the output of the inverter 110. The least significant bit x1 is obtained at the output of the EXOR circuit 133. In order to similarly obtain each bit x2-x4 and carry signal c4, each circuit 112-136 is included in this adder as shown in FIG. 15. Since this structure is well known, its details will be omitted here. The same applies to its operation.

As can be readily seen with reference to FIG. 15, this 4-bit adder requires a significant amount of logic circuitry. Furthermore, the circuit for carry calculation is also large-scale. Moreover, in the circuit shown in FIG.
It can only perform 4-bit operations. Since it is usually necessary to perform calculations on approximately 8-bit data in digital equipment, it is necessary to prepare two 4-bit adders shown in FIG. 15. That is, when compared with the analog circuit shown in FIG. 4, the circuit becomes extremely large-scale when digitized. Therefore, the conventional color separation circuit has a problem in that it is not suitable for digitalization.

It is therefore an object of the invention to provide a color separation circuit that is more suitable for digitization than previous devices.

[0048]

A color separation circuit according to claim 1 includes a first sum signal including a sum of first and second color components and a sum of third and fourth color components. a first image signal including a second sum signal point-sequentially; a third sum signal including a sum of the first and fourth color components; and a fourth image signal including a sum of the second and third color components. A color separation circuit for separating predetermined three primary color signals from a line-sequential image signal of an imaging means that outputs a second image signal including a sum signal and a second image signal dot-sequentially for each horizontal scanning line. first and second synchronizing means for synchronizing the first image signal and the second image signal and outputting the first and second synchronized image signals, respectively; and the first synchronizing means. By performing a predetermined operation between the first sum signal and the second sum signal, which are connected to
a first calculation means for outputting a signal of the first of the three primary colors by mixing the sum signal of The third sum signal and the fourth sum signal are mixed at a predetermined ratio by performing a predetermined operation between the third sum signal and the fourth sum signal included in the signal point-sequentially. , a second calculation means for outputting a signal of a second primary color among the three primary colors, and adding first and second image signals of a plurality of continuous predetermined horizontal scanning lines given from the imaging means. 1st and 3rd by
a third synchronized image signal including a sum signal of the sum signal and a sum signal of the second and fourth sum signals in point sequence; is connected to the synchronization means of the third synchronized image signal, and there is a predetermined difference between the sum signal of the first and third sum signals and the sum signal of the second and fourth sum signals included point-sequentially in the third synchronized image signal. By performing the calculation, the sum signal of the first and third sum signals and the sum signal of the second and fourth sum signals are mixed at a predetermined ratio, and the third of the three primary colors is mixed.
and third calculation means for outputting primary color signals.

[0049]

In the color separation circuit according to the first aspect of the present invention, addition processing is required only at four locations: the first, second, and third arithmetic means and the third simultaneous processing means. Similarly, multiplication processing is required at three locations: the first, second, and third calculation means. No subtraction process is required. When digitizing, addition processing, multiplication processing, and subtraction processing that require especially large-scale circuits can be reduced compared to conventional methods.

[0050]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a color separation circuit 31A according to an embodiment of the present invention. The color separation circuit 31A is shown in FIG.
A color signal processing circuit 35 is used instead of the color separation circuit 31 shown in FIG.
can be incorporated into

Before explaining the color separation circuit 31A shown in FIG. 1, the basic principle of the color separation circuit of the present invention will be explained. By substituting equations (17) and (19) into equation (27), the following equation is obtained.

[0052]

[Math. 12]

In addition, equations (18) and (19) can be transformed into equation (28)
By substituting , we obtain the following equation.

[0054]

[Math. 13]

Further, by substituting equations (17), (18), and (20) into equation (29), the following equation is obtained.

[0056]

[Math. 14]

As described above, the coefficients K3 and K4 are determined by the image pickup device used. However, by adjusting the spectral characteristics of the image sensor as described below,
It is possible to set K3≈K4. In that case, equation (33) can be rewritten as follows.

[0058]

[Math. 15]

In equations (31), (32), and (34), constants n1, n2, and n3 are constants representing gains, respectively. Therefore, if these are ignored as adjustments to be made in the amplification process after the color separation circuit, color separation can be achieved in accordance with the following three equations (35) to (37).

[0060]

[Math. 16]

The present invention realizes a color separation circuit according to equations (35) to (37). Referring to FIG. 1, a color separation circuit 31A according to the present invention includes a timing signal generation circuit 17 for outputting a switching pulse SWP shown in FIG. 2 and two sample and hold pulses SHP1 and SHP2 shown in FIG. , a 1H delay line 2 for delaying the image signal output from the image sensor 1 by 1H, and a switching pulse SWP connected to the output of the image sensor 1 and the output of the 1H delay line 2 and given from the timing signal generation circuit 17. and a switch 3 for outputting two synchronized image signals by synchronizing the outputs from the image sensor 1 in response to the image sensor 1 . The switch 3 has one input connected to the output of the image sensor 1 and the other input connected to the 1H delay line 2.
, and includes switches 18 and 19 for complementary switching and outputting input signals in response to the switching pulse SWP.

The color separation circuit 31A further includes a switch 18.
are connected to the outputs of the sample and hold pulses S, respectively.
It is connected to sample-hold circuits 4 and 5 for sample-holding and outputting the image signals synchronized at the timing defined by HP1 and SHP2, and to the output of the sample-hold circuit 5, as shown in equation (35). A multiplier circuit 6 for multiplying the output of the sample hold circuit 5 by a predetermined coefficient m1 and outputting the result, and an adder circuit for adding the output of the sample hold circuit 4 and the output of the multiplier circuit 6 and outputting the result as a signal R. 7 and switch 19 respectively.
are connected to the outputs of the sample and hold pulses S, respectively.
Sample and hold circuits 8 and 9 for sample-holding and outputting the output of the switch 32 at the timing specified by HP1 and SHP2, and a predetermined circuit connected to the output of the sample-and-hold circuit 9 and shown in equation (36). A multiplier circuit 10 for multiplying the output of the sample and hold circuit 9 by a coefficient m2 and outputting the result is connected to the outputs of the sample and hold circuit 8 and the multiplier circuit 10, and is connected to the output of the sample and hold circuit 8 and the output of the multiplier circuit 10. and an adder circuit 11 for adding and outputting as signal B.

In order to realize equation (37), the color separation circuit 31A is further connected to the output of the image sensor 1 and the output of the 1H delay line 2, and has an addition circuit 12 for adding these outputs, respectively. Sample and hold circuits 13 and 14 are connected to the output of the addition circuit 12 and are configured to sample and hold the output of the addition circuit 12 and output the sample and hold output at the timing specified by the sample and hold pulses SHP2 and SHP1.
is connected to the output of the sample and hold circuit 14, and the formula (
37), a multiplication circuit 15 for multiplying the output of the sample and hold circuit 14 by a predetermined coefficient m3 and outputting the result, and a sample and hold circuit 13 and a multiplication circuit 15.
By adding the output of the sample hold circuit 13 and the output of the multiplication circuit 15, the signal G
and an adder circuit 16 for outputting.

Of the above circuits, the 1H delay line 2 and switch 18 form a first synchronization means, and the 1H delay line 2 and switch 19 form a second synchronization means. Further, the 1H delay line 2 and the adder circuit 12 form a third synchronization means. Circuits 4 to 7 serve as first computing means, circuits 8 to 11 serve as second computing means, and circuits 13 to 16 serve as first computing means.
correspond to the third calculation means, respectively.

The signal (a) input from the image sensor 1 to the color separation circuit 31A has a configuration as shown in FIG. 2(a). In other words, the nth line of this signal is expressed by the formula (1
), signals C1 and C2 shown in (2) are included point-sequentially. Also, on the n+1th line, equation (3), (
Signals C3 and C4 shown in 4) are included in point sequence. This signal is applied to one input terminal of the switches 18 and 19, one input of the adder circuit 12, and the input of the 1H delay line 2, respectively.

The signal (b) output from the 1H delay line 2 is the signal shown in FIG. 2(a) delayed by 1H, as shown in FIG. 2(b). Therefore, on the n-th line, the signals C3 and C expressed by equations (3) and (4) are
4 is included in dot sequence, and the n+1th line contains equations (1) and (
Signals C1 and C2 shown in 2) are included point-sequentially. This signal is transmitted to the switches 18, 19 and the adder circuit 12.
The output of the image sensor 1 is given to the unconnected input.

The switch 18 is a switching pulse SW.
When P is at a high level, the output of the image sensor 1 is selected, and when it is at a low level, the output of the 1H delay line 2 is selected,
It is output as a synchronized signal (c). That is, the switch 18 always changes the connection so as to output the dot sequential signals of C1 and C2. The output (c) of the switch 18 is shown in FIG. 3(c).
will be shown.

On the other hand, the switch 19 is switched to select the output of the 1H delay line 2 when the switching pulse SWP is at a high level, and to select the output of the image pickup element 1 when the switching pulse SWP is at a low level. Therefore, the output signal (d) of the switch 19 is always a synchronized signal including the point sequential signals of C3 and C4, as shown in FIG. 3(d).

Therefore, sample and hold circuits 4 and 5
The signals shown in FIG. 3(c) are input to both the sample and hold circuits 8 and 9, and the signals shown in FIG. 3(d) are input to both the sample and hold circuits 8 and 9, respectively. The sample and hold circuits 4 and 8 receive the sample and hold pulse SHP1 in FIG.
The input signal is sampled and held at the timing defined by and applied to adder circuits 7 and 11, respectively. Therefore, the signal (e
) includes only C1 as shown in FIG. 4(e). Similarly, the signal output from the sample and hold circuit 8 includes only C3, as shown in FIG. 4(g).

The sample and hold circuits 5 and 9 sample and hold their respective input signals at the timing defined by the sample and hold pulse SHP2 shown in FIG. 3, and output them to the multiplication circuits 6 and 10. Therefore, the output signal (f) of the sample and hold circuit 5 includes only C2, as shown in FIG. 4(f). Similarly, the output (h) of the sample hold circuit 9 is C
Contains only 4.

The multiplier circuit 6 multiplies the signal C2 provided from the sample and hold circuit 5 by a predetermined coefficient m1, and provides the multiplier as m1 C2 to the adder circuit 7. Addition circuit 7
is C1 output from the sample hold circuit 4 and the multiplication circuit 6
m1 and C2 outputted by are added, and C1+m1 C2 is output. This signal corresponds to R of the three primary colors, as shown in equation (35).

The multiplication circuit 10 includes a sample hold circuit 9
C4 given by is multiplied by a predetermined coefficient m2 and is given to the adder circuit 11 as m2 C4. The adder circuit 11 adds C3 from the sample hold circuit 8 and m2 C4 from the multiplier circuit 10, and outputs the result as C3+m2 C4. As shown in equation (36), this value is
It corresponds to B of the three primary colors.

The adder circuit 12 adds the signal shown in FIG. 2(a) and the signal delayed by 1H shown in FIG. 2(b). Therefore, the output (i) of the adder circuit 12 is as shown in FIG.
As shown in i), the signal becomes a signal containing C1+C3 and C2+C4 dot-sequentially. This signal is applied to sample and hold circuits 13 and 14.

The sample-and-hold circuit 13 samples and holds the input signal at the timing defined by the sample-and-hold pulse SHP2 shown in FIG. 5, and outputs the sample-and-hold signal. Therefore, the output signal (j) of the sample and hold circuit 13 becomes a signal containing only C2+C4, as shown in FIG. 6(j).

On the other hand, the sample hold circuit 14 is shown in FIG.
The input signal is sampled and held at the timing defined by the sample and hold pulse SHP1 shown in and output. Therefore, the output signal (k) of the sample and hold circuit 14 is C1+C3 as shown in FIG. 6(k).
The signal contains only This signal is applied to multiplication circuit 15.

The multiplication circuit 15 is the sample hold circuit 1
A predetermined coefficient m is added to C1+C3 given from 4.
3, and adder circuit 16 as m3 (C1+C3).
give to

The adder circuit 16 includes the sample and hold circuit 1
By adding C2+C4 given from 3 and m3 (C1+C3) output from the multiplier circuit 15, (C2+C4)+m3
Output as (C1+C3). This output is expressed by the formula (3
It is none other than the remaining G of the three primary colors shown in 7).

The gains of the R, B, and G primary color signals obtained as described above must be adjusted as described above. However, this adjustment is performed by the R amplifier circuit 36 shown in FIG.
, B amplifier circuit 37, and G amplifier circuit 38.

As described above, by using the color separation circuit 31A shown in FIG.
) can be obtained. As can be readily seen with reference to FIG. 1, color separation circuit 31A
The number of circuits required is 6 sample and hold circuits,
There is one 1H delay line, a total of four addition/subtraction circuits, and a total of three multiplication circuits. Compared to the conventional color separation circuit shown in FIGS. 11 and 12, the sample and hold circuit has four
However, the number of 1H delay lines and multiplication circuits has decreased by one each, and the number of addition/subtraction circuits has decreased by three. In the case of digital signal processing, the sample and hold circuit can be easily realized using a D flip-flop.
An increase in the number of sample and hold circuits is not a problem at all. Since the number of processes that require large-scale circuits, such as addition/subtraction circuits and multiplication circuits, is reduced, it is possible to provide a color separation circuit that is more advantageous when digitized.

Note that, as mentioned above, in order to realize this color separation circuit, K3 is added to the coefficients K3 and K4 of the image sensor.
It is necessary that the relationship ≒K4 exists. Each filter Mg
, Ye, G, and Cy, those having a spectral response as shown in FIG. 7, for example, are known. If the spectral characteristics of each filter are changed, the corresponding output of the photosensor will change, and therefore the values of C1 to C4 shown in equations (1) to (4) will change. Accordingly, the values of coefficients K3 and K4 in equation (29) also change. As an assumption to obtain the above equation (34), K3 ≒K
4, but there is no known general method for making K3 and K4 completely coincident. However, it is known that when a combination of color filters having the spectral characteristics shown in FIG. 7 is used, K3≈K4. Therefore, the present invention can be practiced by using a combination of color filters having at least the spectral characteristics shown in FIG.

One embodiment of the present invention has been described above with reference to the drawings. However, it goes without saying that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications.

[0082]

As described above, in the color separation circuit according to the first aspect, addition/subtraction processing and multiplication processing which require particularly large-scale circuits in the case of digitization can be reduced compared to the conventional method. Therefore, when digitized, the circuit scale can be made smaller than that of a conventional color separation circuit, making it easier to digitize the device.

As a result, a color separation circuit more suitable for digitalization can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of a color separation circuit according to an embodiment of the present invention.

FIG. 2 is a schematic waveform diagram showing the operation of the color separation circuit.

FIG. 3 is a schematic waveform diagram showing the operation of the color separation circuit.

FIG. 4 is a schematic waveform diagram showing the operation of the color separation circuit.

FIG. 5 is a schematic waveform diagram showing the operation of the color separation circuit.

FIG. 6 is a schematic waveform diagram showing the operation of the color separation circuit.

FIG. 7 is a diagram showing a spectral response of a spectral filter of an image sensor.

FIG. 8 is a block diagram of a video camera with a color separation circuit.

FIG. 9 is a schematic block diagram of an image sensor.

FIG. 10 is a schematic diagram showing an arrangement of color filters and a waveform of a sample-and-hold pulse.

FIG. 11 is a block diagram of a conventional color separation circuit.

FIG. 12 is a block diagram of a matrix circuit of a conventional color separation circuit.

FIG. 13 is a schematic waveform diagram showing the operation of a conventional color separation circuit.

FIG. 14 is a schematic circuit diagram of an adder circuit in an analog circuit.

FIG. 15 is a block diagram of an example of a carry-ahead 4-bit adder.

[Explanation of symbols]

1 Image sensor 2 1H delay line 3 Switches 4, 5, 8, 9, 13, 14 Sample and hold circuits 6, 10, 15 Multiplication circuits 7, 11, 12, 16 Addition circuit 17 Timing signal generation circuit 31A Color separation circuit

Claims (1)

[Claims] Claim 1: A first sum signal including a predetermined sum of first and second color components and a second sum signal including a predetermined sum of third and fourth color components in a dot-sequential manner. a first image signal including a first image signal, a third sum signal including the sum of the first and fourth color components, and a fourth sum signal including the sum of the second and third color components, point-sequentially. A color separation circuit for separating predetermined three primary color signals from a line-sequential image signal of an imaging means that outputs a second image signal including a second image signal line-sequentially for each horizontal scanning line, the color separation circuit comprising: first and second synchronization means for synchronizing the image signal and the second image signal and outputting first and second synchronized image signals;
The first sum signal and the second sum signal are connected to the first synchronization means and included in the first synchronized image signal point-sequentially.
By performing a predetermined operation on the sum signal of the first sum signal and the second sum signal, the first sum signal and the second sum signal are mixed in a predetermined ratio and a signal of the first primary color of the three primary colors is output. and a first calculation means connected to the second synchronization means to calculate the sum signal of the third color component and the fourth sum signal, which are connected to the second synchronization means and included in the second synchronization image signal point-sequentially. By performing a predetermined operation between the third sum signal and the fourth sum signal,
a second calculation means for outputting a signal of a second primary color of the three primary colors by mixing the sum signal of the three primary colors at a predetermined ratio; and a plurality of consecutive predetermined horizontal scanning lines provided from the imaging means. A synchronized image signal including a sum signal of the first and third sum signals and a sum signal of the second and fourth sum signals in point-sequential manner by adding the first and second image signals of a third synchronizing means for outputting a third synchronized image signal;
By performing a predetermined operation between the sum signal of the first and third sum signals and the sum signal of the second and fourth sum signals included point-sequentially in the simultaneous image signal of 1
and a third signal for mixing the sum signal of the third sum signal and the sum signal of the second and fourth sum signals at a predetermined ratio to output a signal of a third primary color among the three primary colors. and a color separation circuit.