JPH04361557A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04361557A JPH04361557A JP3138023A JP13802391A JPH04361557A JP H04361557 A JPH04361557 A JP H04361557A JP 3138023 A JP3138023 A JP 3138023A JP 13802391 A JP13802391 A JP 13802391A JP H04361557 A JPH04361557 A JP H04361557A
- Authority
- JP
- Japan
- Prior art keywords
- output
- cells
- chip
- cell
- basic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 13
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は設計変更に対し有効な半
導体装置に関する。従来、アセンブリされた半導体装置
において、出力リードに複数の異なる出力駆動能力が要
求されているような場合、多数のＩ／Ｏ（入力、出力、
入出力回路）セルを定義しライブラリに登録する必要が
生じた。設計変更に対し極めて不便であったから、簡易
な手段で設計変更が処理できる技術を開発することが要
望された。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device that is effective against design changes. Conventionally, in assembled semiconductor devices, when output leads are required to have multiple different output drive capabilities, a large number of I/Os (inputs, outputs,
It became necessary to define cells (input/output circuit) and register them in the library. Since it was extremely inconvenient to deal with design changes, there was a demand for the development of technology that could handle design changes using simple means.
【０００２】0002
【従来の技術】通常の半導体集積回路チップの周辺パッ
ドとパッケージ外方へ突出しているリード線（リードフ
レーム）とはボンディングワイヤで結合されている。最
近の周辺パッドはＩ／Ｏセル（入出力セル）と呼ばれる
出力駆動トランジスタを含み構成されるようになった。
即ち、図５に示すように、セル構成の入出力部であって
、図６にその回路構成図を示す。図５・図６において、
１はＩ／Ｏセルを全体的に示すもの、２はＣ−ＭＯＳ出
力駆動トランジスタ、３はＰ型ＦＥＴ、４はＮ型ＦＥＴ
、５は両ＦＥＴの接続点Ｉ、６は接続点５と接続される
両ＦＥＴの出力端子Ｏでボンディングパッドを示す。各
ＦＥＴに対する端子Ｐ，Ｎに対し内部モジュール（即ち
ＩＣチップ）からの信号が印加されると、トランジスタ
２が動作し出力端子６に通常の出力信号が得られ、外部
へのリード線に駆動用出力信号を送出する。2. Description of the Related Art The peripheral pads of a typical semiconductor integrated circuit chip and lead wires (lead frames) protruding outward from the package are connected by bonding wires. Recent peripheral pads have come to include output drive transistors called I/O cells (input/output cells). That is, as shown in FIG. 5, the input/output section has a cell configuration, and FIG. 6 shows a circuit configuration diagram thereof. In Figures 5 and 6,
1 shows the overall I/O cell, 2 shows the C-MOS output drive transistor, 3 shows the P-type FET, and 4 shows the N-type FET.
, 5 indicates a connection point I between both FETs, and 6 indicates a bonding pad at an output terminal O of both FETs connected to connection point 5. When a signal from the internal module (i.e. IC chip) is applied to the terminals P and N for each FET, the transistor 2 operates and a normal output signal is obtained at the output terminal 6, and the drive wire is connected to the external lead wire. Send an output signal.
【０００３】図示しないリード線は出力ピン，入力ピン
，及び入出力ピンのように種々の状態となっていて、例
えば出力ピンの状態として出力信号出力が例えば１単位
の場合、２単位の場合など種々の状態となる必要がある
。Lead wires (not shown) are in various states such as output pins, input pins, and input/output pins. For example, the state of the output pin is such that the output signal output is 1 unit, 2 units, etc. It is necessary to be in various states.
【０００４】一般に集積回路チップを設計するとき、機
能設計から開始し、論理設計に進んで行く。最近では論
理設計のとき、基本ゲートのほかに複合ゲートや機能セ
ルを含んだ論理セルライブラリを利用する。このときＩ
／Ｏセルについて、出力・入力・入出力の種別毎に、ま
た出力について駆動能力毎に多数のＩ／Ｏセルを定義し
、それぞれをセルライブラリに登録している。設計が終
了し製造工程に入ったとき、パッケージにアセンブリす
るため１本のピンのリードフレーム端子に対し一つのＩ
／Ｏセルをボンディングしていた。そのためリードフレ
ーム端子とＩ／Ｏセルとチップの信号端子とについて、
その対応は、１対１対１であった。[0004] Generally, when designing an integrated circuit chip, one starts with functional design and proceeds to logical design. Recently, when designing logic, we use logic cell libraries that include not only basic gates but also composite gates and functional cells. At this time I
A large number of I/O cells are defined for each type of output, input, and input/output, and for each output driving capacity, and each is registered in a cell library. When the design is complete and the manufacturing process begins, one I/O per pin lead frame terminal is required for assembly into the package.
/O cell was bonded. Therefore, regarding lead frame terminals, I/O cells, and chip signal terminals,
The correspondence was one-on-one.
【０００５】[0005]
【発明が解決しようとする課題】前述のような設計手順
により開発した集積回路パッケージに対し、下記のよう
な問題点が生じている。開発後の製品に対し外部端子の
出力駆動能力の変更や、また外部リードフレーム端子の
本数を増やすなどの最上位レベルでの論理変更を行う場
合、そのチップのＩ／Ｏセルの種類或いは個数を変更す
る必要があるため、マスク・ウェーハプロセスとも全層
を作り直すこととなる。Problems to be Solved by the Invention The following problems have arisen with integrated circuit packages developed using the above-described design procedure. When making top-level logic changes to a product after development, such as changing the output drive capacity of external pins or increasing the number of external lead frame pins, it is necessary to change the type or number of I/O cells on the chip. Since it is necessary to make changes, all layers in both the mask and wafer processes will have to be remade.
【０００６】更にＩ／Ｏセルを新規に定義する場合、そ
の度に充分に評価を行う必要がある。また駆動能力ごと
にＩ／Ｏセルを定義する必要があるためセルライブラリ
の膨大化につながる欠点があった。Furthermore, when defining a new I/O cell, it is necessary to thoroughly evaluate it each time. Furthermore, since it is necessary to define I/O cells for each drive capacity, there is a drawback that the cell library becomes enormous.
【０００７】本発明の目的は前述の欠点を改善し、一定
の設計手順により開発した集積回路パッケージに対し設
計変更の必要が生じたときなど、柔軟で、且つ容易な対
応を可能にした半導体装置を得ることにある。An object of the present invention is to provide a semiconductor device which improves the above-mentioned drawbacks and makes it possible to flexibly and easily respond to the need for design changes to an integrated circuit package developed according to a certain design procedure. It's about getting.
【０００８】[0008]
【課題を解決するための手段】図１は本発明の原理構成
を示す図である。図１において、２１−１，２１−２
〜は複数の基本出力セル、３−１，３−２〜は基本出力
セルへの入力端子、６−１，６−２ 〜は基本出力セル
のボンディングパッドで出力端子、７はＩＣ内部素子の
出力端子、８は半導体装置パッケージのリードフレーム
（出力ピン）、９−１，９−２ 〜はボンディングワイ
ヤ、１０は半導体装置チップ内結線、１１はＩＣチップ
を示し、１２はパッケージ部分を示す矢印である。[Means for Solving the Problems] FIG. 1 is a diagram showing the basic configuration of the present invention. In FIG. 1, 21-1, 21-2
~ are multiple basic output cells, 3-1, 3-2 ~ are input terminals to the basic output cells, 6-1, 6-2 ~ are bonding pads and output terminals of the basic output cells, 7 is an IC internal element Output terminal, 8 is a lead frame (output pin) of the semiconductor device package, 9-1, 9-2 ~ are bonding wires, 10 is a connection inside the semiconductor device chip, 11 is an IC chip, 12 is an arrow indicating the package part It is.
【０００９】チップ上にボンディングパッド６と駆動ト
ランジスタ２とを有する基本出力セルが複数２１−１，
２１−２ 〜設けられ、パッケージ１２側のボンディン
グパッド（１６）１個に対して、複数の前記基本出力セ
ル２１−１，２１−２ 〜のボンディングパッド６−１
，６−２ 〜がワイヤ９−１，９−２ 〜で接続されて
いることで構成する。A plurality of basic output cells 21-1 each having a bonding pad 6 and a driving transistor 2 are provided on the chip.
21-2 ~ is provided, and for each bonding pad (16) on the package 12 side, a plurality of bonding pads 6-1 of the basic output cells 21-1, 21-2 ~ are provided.
, 6-2 are connected by wires 9-1, 9-2.
【００１０】0010
【作用】図１における基本出力セル２１−１，２１−２
〜は単位駆動能力の基本出力セルであって、従来のＩ
／Ｏセルに対し代表的・汎用的なものを共通的に使用す
る。各基本出力セル２１−１，２１−２ 〜は駆動トラ
ンジスタを内蔵していて、半導体装置チップからの信号
が印加されたとき、増幅動作を行うことは同様であるが
、増幅動作の程度を１単位のものとする。半導体装置チ
ップについて、一旦設計製作の後出力駆動能力を変更す
る必要が生じたとき、装置としてはボンディング処理を
変更して能力に対応する複数の基本出力セル２１−１，
２１−２ 〜から単数のリードフレーム８・ボンディン
グパッド１６に対し、各ボンディングワイヤ９−１，９
−２ 〜を接続する。各基本出力セルの入力端子３−１
，３−２ 〜側はＩＣチップの出力端子７とチップ内結
線１０を介して各々並列接続する。そのためリードフレ
ーム端子と基本出力セルとチップの信号端子とについて
、その対応は、本発明によると
１ 対 多数 対 １
となる。[Operation] Basic output cells 21-1, 21-2 in FIG.
〜 is a basic output cell of unit driving capacity, and is a conventional I
/Use representative and general-purpose cells in common for O cells. Each basic output cell 21-1, 21-2 ~ has a built-in drive transistor, and when a signal from a semiconductor device chip is applied, performs an amplification operation in the same way, but the degree of amplification operation is reduced to 1. It shall be a unit. When it becomes necessary to change the output drive capacity of a semiconductor device chip after it has been designed and manufactured, the device changes the bonding process and creates a plurality of basic output cells 21-1 corresponding to the capacity.
21-2 Each bonding wire 9-1, 9 is connected to a single lead frame 8/bonding pad 16 from ~.
-2 Connect ~. Input terminal 3-1 of each basic output cell
, 3-2 ~ are connected in parallel to the output terminal 7 of the IC chip via the intra-chip connection 10. Therefore, according to the present invention, the correspondence between lead frame terminals, basic output cells, and chip signal terminals is one to many to one.
【００１１】図２は本発明の実施例として半導体装置の
一部を示す上面図である。図２において、１−１，１−
２ 〜は単位Ｉ／Ｏセルであって、ＩＣチップ１１の周
辺部に隙間なく配列されている。ここで単位Ｉ／Ｏセル
は基本出力セルについて、入力セルとして動作するため
の端子も具備する。７−１，７−２〜はＩＣチップから
外部への信号出力端子、１７−１，１７−２ 〜は同信
号入力端子、８−１，８−２ 〜はリードフレーム、９
−１，９−２ 〜はボンディングワイヤを示す。図２の
Ｉ／Ｏセル内に記入したＰ，Ｎは、それぞれＰ型ＦＥＴ
，Ｎ型ＦＥＴの各制御電極、Ｉは両ＦＥＴの接続点から
の接続線を示す。図２における単位Ｉ／Ｏセル１−１，
１−２ 〜はチップの周辺部に隙間なく配列され、図２
においてはＩ／Ｏセル１−７ が未使用で、図示する他
のセルは全て使用する。そして単一のＩＣチップの信号
端子７−１ からの信号が印加されるＩ／Ｏセル１−１
は単位駆動能力のもの単独で、リードフレーム８−１
と対応して動作する。次にＩＣチップの信号端子７−
２ からの信号が並列印加されるＩ／Ｏセル１−２，１
−３ は、単一のリードフレーム８−２ を共同駆動す
る。同様に信号端子７−３ からの信号はＩ／Ｏセル１
−４，１−５，１−６ により並列印加され、リードフ
レーム８−３ を共同駆動する。したがってリードフレ
ーム８−１，８−２，８−３ は出力専用である。リー
ドフレーム８−４ はそれに対し入力専用であって、Ｉ
／Ｏセル１−８ を介してＩＣチップの入力端子１７−
１に信号を入力させる。またＩ／Ｏセル１−９ は入出
力セルであって、リードフレーム８−５ を入力信号用
として使用するとき、及び出力駆動用とする場合を区別
して動作させる。入力信号用のときはＩ／Ｏセル１−９
を読出信号用として外部からの信号をＩＣチップ入力
端子１７−２に入力させる。次にＩ／Ｏセル１−９ を
出力駆動用とするときはＩ／Ｏセル１−１０と共にリー
ドフレーム８−５ を共同駆動する。この場合、リード
フレーム８−２，８−３ に対応するＩ／Ｏセルは大型
のＩ／Ｏセルを設計使用する必要がない。なお、未使用
Ｉ／Ｏセルは、任意に配置できるが、リードフレームに
複数接続されるＩ／Ｏセルからなる機能回路（出力、入
力、入出力回路）間に必ず設けることや、設計変更の生
じやすい回路に近接して設けておくことも出来る。FIG. 2 is a top view showing a part of a semiconductor device as an embodiment of the present invention. In Figure 2, 1-1, 1-
2 to 2 are unit I/O cells, which are arranged around the periphery of the IC chip 11 without gaps. Here, the unit I/O cell also has a terminal for operating as an input cell for the basic output cell. 7-1, 7-2 ~ are signal output terminals from the IC chip to the outside, 17-1, 17-2 ~ are the same signal input terminals, 8-1, 8-2 ~ are lead frames, 9
-1,9-2 ~ indicate bonding wires. P and N written in the I/O cell in Figure 2 are P-type FETs, respectively.
, each control electrode of the N-type FET, and I indicates a connection line from the connection point of both FETs. Unit I/O cell 1-1 in FIG.
1-2 ~ are arranged without any gaps around the periphery of the chip, as shown in Figure 2.
In the figure, I/O cells 1-7 are unused, and all other cells shown are used. And an I/O cell 1-1 to which a signal from a signal terminal 7-1 of a single IC chip is applied.
is the unit drive capacity alone, lead frame 8-1
It operates correspondingly. Next, the signal terminal 7- of the IC chip
I/O cells 1-2, 1 to which signals from 2 are applied in parallel
-3 jointly drive a single lead frame 8-2. Similarly, the signal from signal terminal 7-3 is I/O cell 1
-4, 1-5, and 1-6 are applied in parallel to jointly drive the lead frame 8-3. Therefore, lead frames 8-1, 8-2, and 8-3 are used only for output. Lead frame 8-4, on the other hand, is for input only, and is for input only.
/O cell 1-8 to IC chip input terminal 17-
Input a signal to 1. Further, the I/O cell 1-9 is an input/output cell, and is operated separately when the lead frame 8-5 is used for input signals and when it is used for output driving. I/O cells 1-9 for input signals
An external signal is input to the IC chip input terminal 17-2 as a read signal. Next, when the I/O cell 1-9 is used for output driving, the lead frame 8-5 is jointly driven together with the I/O cell 1-10. In this case, it is not necessary to design and use large I/O cells for the I/O cells corresponding to the lead frames 8-2 and 8-3. Note that unused I/O cells can be placed arbitrarily, but they must be placed between functional circuits (output, input, input/output circuits) consisting of multiple I/O cells connected to a lead frame, and should be It is also possible to provide it close to a circuit where it is likely to occur.
【００１２】図３は本発明の他の実施例として開発後の
製品に対し最上位レベルでの設計変更を行った場合を示
す図である。図３Ａは既製品、図３Ｂは変更後の状況を
示す図である。図３において１−１１，１−１２ 〜は
Ｉ／Ｏセル、７−５，７−６ はＩＣチップの出力端子
、１７−３，１７−４ はＩＣチップへの入力端子、８
−１１，８−１２ 〜はリードフレームを示す。リード
フレーム８−１１は単独のＩ／Ｏセル１−１１と対応し
ていて、入力専用または出力専用の何れかとなる。Ｉ／
Ｏセル１−１３，１−１４ は単一のリードフレーム８
−１２を共同駆動していたが、３つのＩ／Ｏセルにより
共同駆動するように設計変更するとき、本発明によれば
、隙間なく配列されていたＩ／Ｏセルの列のうち１−１
２が偶然に未使用であったから、これを１−１３と並列
接続すれば、３ 倍駆動出力用リードフレーム８−１２
がボンディングワイヤ９−１２の新設のみで得られる。
次にリードフレーム８−１３は２倍駆動出力用であった
が、そのリードフレームを入力専用８−２３と変更する
ときは、ボンディングワイヤを未使用のＩ／Ｏセル１−
１６と接続し、それを介して入力端子１７−３と接続す
れば良い。リードフレーム８−１４は単独の出力専用型
であったが、リードフレーム８−２４として２倍駆動出
力用・兼入力用に変更されている。リードフレームの使
用方法を変更すれば、装置の設計変更に対し極めて有効
に対処できる。FIG. 3 is a diagram showing another embodiment of the present invention in which a design change is made at the top level of a developed product. FIG. 3A is a diagram showing a ready-made product, and FIG. 3B is a diagram showing a state after modification. In FIG. 3, 1-11, 1-12 ~ are I/O cells, 7-5, 7-6 are output terminals of the IC chip, 17-3, 17-4 are input terminals to the IC chip, and 8
-11, 8-12 ~ indicate lead frames. The lead frame 8-11 corresponds to a single I/O cell 1-11, and is either input-only or output-only. I/
O cells 1-13, 1-14 are a single lead frame 8
-12 were jointly driven, but when changing the design to jointly drive with three I/O cells, according to the present invention, 1-1 of the I/O cell rows that were arranged without gaps
2 happened to be unused, so by connecting it in parallel with 1-13, the lead frame 8-12 for triple drive output
can be obtained only by newly installing the bonding wire 9-12. Next, the lead frame 8-13 was for double drive output, but when changing the lead frame to input-only 8-23, connect the bonding wire to the unused I/O cell 1-23.
16 and then to the input terminal 17-3 through it. The lead frame 8-14 was a single output-only type, but it has been changed to a lead frame 8-24 for double drive output and dual input. By changing the way the lead frame is used, changes in device design can be dealt with very effectively.
【００１３】図４は本発明の実施例としてセルライブラ
リの記述とチップ上レイアウトの対応を示す図である。
図４Ａは論理設計変更の段階で、Ｉ／Ｏセルとして３倍
出力駆動能力があり、双方向Ｉ／Ｏセルという条件が定
まったことを示す。図４Ｂはセルライブラリの記述内容
を示す。即ち、単位駆動能力のＩ／Ｏセル３個を並列接
続し、入・出力端子を附して構成することを記述する。
図４Ｃはチップ上のレイアウトを示す図である。即ち、
入出力型Ｉ／Ｏセル１−３１、出力型Ｉ／Ｏセル１−３
２は、例えば隣接したものを使用し、出力型Ｉ／Ｏセル
１−３６をセル１−３１，１−３２ と並列接続すると
き、隣接せずに離れているセル１−３６について接続す
る。ＩＣチップとの入・出力配線を図のように行えば良
い。このようにして一旦、開発・製造した後に設計変更
するとき、ウェ−ハプロセスの全層を変更する必要がな
くなり、マスク・ウェーハプロセス共に配線層の変更と
、アセンブリ工程のボンディング変更のみで対処できる
。FIG. 4 is a diagram showing the correspondence between the cell library description and the on-chip layout as an embodiment of the present invention. FIG. 4A shows that at the stage of changing the logic design, the conditions for the I/O cell to have three times the output drive capability and to be a bidirectional I/O cell were determined. FIG. 4B shows the description contents of the cell library. That is, it is described that three I/O cells of unit driving capacity are connected in parallel and configured by attaching input/output terminals. FIG. 4C is a diagram showing the layout on the chip. That is,
Input/output type I/O cell 1-31, output type I/O cell 1-3
For example, when the output type I/O cells 1-36 are connected in parallel with the cells 1-31 and 1-32, the cells 1-36 which are not adjacent to each other but are separated are connected. The input/output wiring with the IC chip can be done as shown in the figure. In this way, when a design is changed once it has been developed and manufactured, there is no need to change all layers in the wafer process, and it can be handled by changing only the wiring layer and bonding in the assembly process for both mask and wafer processes. .
【００１４】[0014]
【発明の効果】このようにして本発明によると、単位駆
動能力の出力セルを基本的なものとしてＩ／Ｏセルライ
ブラリ体系を構築できるため、セルライブラリ自体が簡
略化され、ＩＣチップの最上位レベルでの論理変更に対
し柔軟で容易な対応が可能となる。したがってその設計
方法に基づき製造した半導体装置が安価に短時間に得ら
れる効果を有する。As described above, according to the present invention, it is possible to construct an I/O cell library system based on output cells of unit driving capacity, so that the cell library itself is simplified and the topmost layer of the IC chip is It becomes possible to respond flexibly and easily to logical changes at the level. Therefore, a semiconductor device manufactured based on the design method can be obtained at low cost and in a short time.
【図１】本発明の原理構成を示す図である。FIG. 1 is a diagram showing the principle configuration of the present invention.
【図２】本発明の実施例の構成を示す図である。FIG. 2 is a diagram showing the configuration of an embodiment of the present invention.
【図３】本発明の実施例の構成を示す図である。FIG. 3 is a diagram showing the configuration of an embodiment of the present invention.
【図４】本発明の他の実施例の構成を示す図である。FIG. 4 is a diagram showing the configuration of another embodiment of the present invention.
【図５】Ｉ／Ｏセルの構成を示す図である。FIG. 5 is a diagram showing the configuration of an I/O cell.
【図６】図５の回路構成図である。FIG. 6 is a circuit configuration diagram of FIG. 5;
２ 駆動トランジスタ ３−１，３−２ 〜 接続線 ６ チップ上のボンディングパッド ７ 内部素子出力端子 ８ リードフレーム ９−１，９−２ 〜 接続線 2 Drive transistor 3-1, 3-2 ~ Connection line 6 Bonding pad on chip 7 Internal element output terminal 8 Lead frame 9-1, 9-2 ~ Connection line
Claims (2)
と駆動トランジスタ（２） とを有する基本出力セル
が複数（２１−１）（２１−２）〜設けられ、パッケー
ジ（１２）側のボンディングパッド（１６）１個に対し
て、複数の前記基本出力セル（２１−１）（２１−２）
〜のボンディングパッド（６−１）（６−２）〜が接続
線（９−１）（９−２）〜で接続されていることを特徴
とする半導体装置。[Claim 1] Bonding pad (6) on the chip
A plurality of basic output cells (21-1), (21-2), and a drive transistor (2) are provided, and a plurality of basic output cells are provided for one bonding pad (16) on the package (12) side. Cell (21-1) (21-2)
A semiconductor device characterized in that bonding pads (6-1), (6-2), and so on are connected by connection lines (9-1), (9-2), and so on.
は、半導体装置のチップ周辺部に互いに隙間なく配列し
たことを特徴とする半導体装置。2. A semiconductor device according to claim 1, wherein the plurality of basic output cells are arranged around a chip of the semiconductor device without any gaps between them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3138023A JPH04361557A (en) | 1991-06-10 | 1991-06-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3138023A JPH04361557A (en) | 1991-06-10 | 1991-06-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04361557A true JPH04361557A (en) | 1992-12-15 |
Family
ID=15212250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3138023A Withdrawn JPH04361557A (en) | 1991-06-10 | 1991-06-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04361557A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6292024B1 (en) | 1999-12-14 | 2001-09-18 | Philips Electronics North America Corporation | Integrated circuit with a serpentine conductor track for circuit selection |
-
1991
- 1991-06-10 JP JP3138023A patent/JPH04361557A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6292024B1 (en) | 1999-12-14 | 2001-09-18 | Philips Electronics North America Corporation | Integrated circuit with a serpentine conductor track for circuit selection |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
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Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980903 |