JPH04361296A - Method and device for compressing waveform data and reproducing device - Google Patents

Abstract

PURPOSE:To promote the compression of waveform data and freely control the compression. CONSTITUTION:The data compression is promoted more by performing not only a specific data compressing process for the waveform data, but also an arithmetic process for decreasing the value of the waveform data according to a weight coefficient before or after the data compressing process. The system of the specific data compressing processing itself is not altered and easily and freely controlled so that the compressibility can be varied or no compression is performed extremely easily only by varying the weight coefficient. This device and method are advantageous when the data compression is further promoted in some section of the waveform or when the data compression is performed to different extents according to sections of the waveform.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for compressing waveform data and a reproducing apparatus that can be used in electronic musical instruments, other musical tone generators, sound signal processing apparatuses, and the like.

0002

[Prior Art] One method for creating a sound source waveform for an electronic musical instrument is to sample and store sounds actually acoustically produced by a natural instrument, etc. 54-161313, JP-A-62-89093, JP-A-62-94896, etc.). These external sound sampling method sound sources have the advantage of being able to obtain musical sound waveforms of the same high quality as natural instrument sounds, but on the other hand, the amount of waveform data is enormous, so the waveform data storage device must have a large capacity. was demanding.

Compression of waveform data has been considered in order to simplify the configuration of storage devices and related circuits and devices. For example, Japanese Patent Laid-Open No. 62-242993 discloses storing tone waveform data in a data representation format compressed by the linear prediction method (LPC method). Further, Japanese Patent Publication No. 1-45078 discloses that waveform sample data is expressed by being decomposed into a floating point representation consisting of a mantissa part and an exponent part, and then stored. In addition, the data encoding method is not limited to PCM, but also DPC.
Adopts various methods such as M, ADPCM, and delta modulation,
It is also known to perform data compression.

0004

However, in the conventional waveform data compression technique, waveform data was simply compressed according to a predetermined data compression process, and therefore only uniform data compression could be performed. Therefore, it is easy to handle cases where you want to further advance data compression, particularly in some sections of a waveform, or when you want to compress data to different degrees depending on sections of the waveform. could not. For example, normal data compression is performed in areas where waveform accuracy is desired, such as the attack section where the waveform changes in a complex manner, and data compression is further promoted in areas where it is acceptable to reduce waveform accuracy to some extent. Although it is sometimes desirable to use them differently, it has not been possible to meet such a request in the past. This invention was made in view of the above points,
It is an object of the present invention to provide a waveform data compression method and apparatus that can facilitate data compression with a simple configuration and that can be freely controlled. Furthermore, it is an object of the present invention to provide a waveform data reproducing device for reproducing waveform data compressed according to such a data compression method.

[0005]

[Means for Solving the Problems] A waveform data compression method according to the present invention includes a first step of providing waveform data to be compressed, and a second step of performing predetermined data compression processing on the waveform data. A waveform data compression method comprising: a third step of further reducing the value of the waveform data according to an arbitrary weighting coefficient at any stage before or after the data compression process. This is a characteristic feature. One aspect of a waveform data compression device capable of implementing the waveform data compression method according to the present invention is a reduction method that inputs waveform data to be compressed and performs an operation to reduce the value of the waveform data according to an arbitrary weighting coefficient. a calculation means; a compression filter means for inputting the waveform data output from the reduction calculation means and performing data compression filter processing on the waveform data; and creating filter coefficients to be used in the compression filter means by a linear prediction method. death,
and coefficient generating means for supplying the compression filter means. Another aspect of the above waveform data compression device is
Compression filter means that inputs waveform data to be compressed and performs data compression filter processing on the waveform data, and reduction that performs an operation to reduce the value of the waveform data output from the compression filter means according to an arbitrary weighting coefficient. The apparatus includes a calculation means, and a coefficient generation means for creating filter coefficients to be used in the compression filter means by a linear prediction method and supplying the generated filter coefficients to the compression filter means. The waveform data reproducing device according to the present invention includes a waveform storage means that stores waveform data that has been subjected to predetermined data compression processing and data value reduction processing according to a weighting coefficient, a coefficient providing means for providing a coefficient and the weighting coefficient; a compressed data demodulating means for performing compressed data demodulation processing on the waveform data read from the waveform storage means according to the coefficient for demodulation; and the weighting factor. and calculation means for performing an operation on the waveform data read from the waveform storage means to restore the data value reduced according to the coefficient to its original size.

[0006]

[Operation] According to the waveform data compression method of the present invention, the second
In the step, predetermined data compression processing is performed on the waveform data. The predetermined data compression processing performed here is
Any other compression method may be used, such as linear prediction. The present invention is characterized by the provision of a third step, in which the value of the waveform data is further reduced according to an arbitrary weighting coefficient at any stage before or after the data compression processing. This data value reduction processing allows the values of the waveform data compressed by the data compression processing to be further reduced, so that data compression can be further promoted. Moreover, you can change the reduction rate by changing the weighting factor, or not reduce it at all.
This control can be performed easily and freely. Therefore, if you want to further compress data in some sections of the waveform, or compress data to different degrees depending on sections of the waveform, you may want to change the method of data compression processing in the second step. This can be handled extremely easily by simply changing the weighting coefficient in the third step. The third step is an extremely simple process of reducing the value of the waveform data according to an arbitrary weighting coefficient (this process can be performed by appropriate coefficient operations such as data shifting, division, or multiplication). Therefore, the configuration is simple.

[0007] As an example, data compression processing is performed using a compression filter according to a linear prediction method. According to one aspect of the waveform data compression device according to the present invention, reduction calculation means is provided at a stage before the compression filter means. The reduction calculation means receives waveform data to be compressed and performs calculation to reduce the value of the waveform data according to an arbitrary weighting coefficient. The compression filter means inputs the waveform data output from the reduction calculation means and performs data compression filter processing on the waveform data. The filter coefficients used by the compression filter means are created by the coefficient generation means by a linear prediction method. Discontinuity in data values that may occur due to reduction processing by the reduction calculation means (for example, data values may become discontinuous at the boundary when the weighting coefficient changes) is absorbed by the subsequent compression filter means. be able to.

According to another aspect of the waveform data compression device according to the present invention, reduction calculation means is provided at a stage subsequent to the compression filter means. In that case, in order to absorb discontinuities and errors in data values that may occur due to reduction processing by the reduction calculation means, the output signal of the reduction calculation means is inputted to the compression filter means, and the output waveform of the reduction calculation means is It is preferable to include calculation means for expanding and restoring data values inversely according to the weighting coefficients, and to perform calculations of compression filter coefficients on the restored data.

According to the waveform data reproducing device according to the present invention, the waveform storage means stores waveform data that has been subjected to a predetermined data compression process and a data value reduction process according to a weighting coefficient. , compressed data demodulation means performs compressed data demodulation processing on the waveform data read out from the waveform storage means, as well as an operation to return the data value reduced according to the weighting coefficient to the original size. It is provided with arithmetic means for performing calculation on the waveform data read out from the storage means. Thereby, it is possible to reliably demodulate and reproduce waveform data that has been subjected to data compression processing and data value reduction processing according to the weighting coefficient.

Some embodiments of the waveform data compression method according to the present invention are listed below. a) The third step is executed before the second step, and the second step uses a data compression filter to perform data compression processing. This allows discontinuities and noise components that may occur due to data reduction operations to be absorbed by the subsequent compression filter. b) The third step is executed after the second step, and the second step uses a data compression filter to perform data compression processing. c) In the third step, continuous waveform data is divided into a plurality of sections, and reduction processing is performed independently for each section according to a weighting coefficient independently set for each section. As a result, if you want to vary the degree of waveform compression in any section of the entire sound generation period (for example, if you want to apply different compression to the attack section and the sustain section), you can change the specified data compression processing method itself. This is simple and advantageous because it can be dealt with simply by changing the weighting coefficient. d) A limit bit number is set to limit the number of bits of one sample data for each section, and the data after the data compression processing and reduction processing for each section is equal to the limit bit number corresponding to the section. The weighting coefficients are set for each section so that the weighting coefficients are within the range. This makes it easy to control the number of bits of waveform data to the desired number for each section of the entire sound generation period, which is advantageous for creating and managing waveform data, and also makes waveform memory effective. It can be used for. Furthermore, it is advantageous because the weighting coefficient for each section can be automatically set. e) In the third step, reduction processing is performed by data shifting. This is advantageous because the weighting coefficients can be calculated by simple data shifting. f) The second step performs data compression processing using a two-stage compression filter, and includes a step of creating filter coefficients to be used in the compression filter by a linear prediction method, and this coefficient creation step includes: , multiply the waveform data input to the first-stage compression filter by a Hamming window function, calculate a first linear prediction coefficient based on the autocorrelation function of the multiplication result, and apply the first linear prediction coefficient to the first-stage compression filter. a step of providing the first linear prediction coefficient as a filter coefficient of a compression filter; and a step of compressing the waveform data with the first-stage compression filter using the first linear prediction coefficient as a filter coefficient of the first-stage compression filter. Then, the output waveform data of the first-stage compression filter is multiplied by a Hamming window function, a second linear prediction coefficient is calculated based on the autocorrelation function of the multiplication result, and the second linear prediction coefficient is divided into two stages. and providing the filter coefficients as filter coefficients of the second compression filter. By calculating the Hamming window function in two stages, accurate compression filter coefficients can be created. g) a fourth step of storing the waveform data that has been subjected to data compression processing and reduction processing in a storage device, and when the data compression processing and reduction processing for a continuous series of waveform data is completed, storing the data of the series in the storage device; The present invention further comprises a fifth step of generating and storing data indicating the storage location of the waveform data. The storage location of a series of waveform data can be indicated by specifying the start address, the total address size, or the end address. As a result, the overall size (capacity) of a series of waveform data becomes unpredictable due to data compression and reduction processing, but in preparation for this, this size is automatically adjusted by generating and storing such storage location indication data. (capacity) is known, which is advantageous for later read/playback processing. Some embodiments of the waveform data compression apparatus according to the present invention are listed below. h) The continuous waveform data is divided into a plurality of sections, and the compression filter means performs data compression processing for each section according to a filter coefficient independently set for each section, and the data compression processing for one section is performed. storage means for temporarily storing the data held in the delay section in the compression filter when the data compression process is completed; The method further comprises a control means that is set in a delay section in the compression filter to enable redoing. This allows the compression process to be repeated many times to achieve optimal data compression. Further, in this case, since the signal state of the delay section in the compression filter regarding the immediately previous section can be reproduced, accurate compression filter calculation can be performed no matter how many times the calculation is repeated. i) The continuous waveform data is divided into a plurality of sections, and the reduction calculation means performs reduction processing independently for each section according to a weighting coefficient independently set for each section, and the compression processing and reduction processing The present invention further comprises a storage means for storing the waveform data for each section subjected to the processing and for storing the weighting coefficient for each section. This is advantageous because when restoring the reduced data to its original state, the weighting coefficient for each section can be read out from the storage means and used for the restoration calculation. j) In the storage means, the weighting coefficient for each interval is determined by the interval before the relevant interval, and the weighting coefficient for the next interval is read out at the time of reading the waveform data of the preceding interval during the restoration calculation. This can be used immediately as a restoration weighting coefficient for the next section when reading the waveform data of the next section, so the control is simple and reliable.
There is an advantage. k) The compression filter means performs data compression processing independently for each section according to filter coefficients independently set for each section, and the storage means stores the filter coefficients for each section from the corresponding section. The waveform data of the previous section is also stored in a part of the storage area that stores the waveform data of the previous section. As a result, when demodulating compressed data, it is possible to read the compression filter coefficient of the next section when reading the waveform data of the preceding section, and use this when reading the waveform data of the next section. Since it can be immediately used as a demodulation coefficient for compressed data, it has the advantage that control is simple and reliable. l) a setting means for arbitrarily setting a limit number of bits that limits the number of bits of one sample data; and a setting means for setting the weighting coefficient so that the data after the data compression processing and reduction processing falls within the set limit number of bits. and a control means for automatically setting. This allows you to easily control the number of bits of waveform data to the desired number.
This is advantageous for creating and managing waveform data, and the waveform memory can be used effectively. It is also advantageous that the weighting factors can be set automatically. m) The control means initially sets the weighting coefficient to a predetermined value to perform the data compression processing and reduction processing, and if the data after the data compression processing and reduction processing does not fit within the limit bit number, For example, the weighting coefficients are automatically switched and the data compression processing and reduction processing are re-performed. This is advantageous because the optimal weighting coefficients can be automatically set. One embodiment of the waveform data reproducing apparatus according to the present invention is as follows. n) Coefficients and weighting coefficients for the compressed data demodulation are stored together with the waveform data in the waveform storage means, and the coefficient providing means extracts the coefficients and weighting coefficients for the compressed data demodulation from the readout output of the waveform storage means. It must be able to extract the coefficients and weighting coefficients separately. This allows the waveform memory to be used effectively without waste, which is advantageous in terms of memory savings.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. --Overall flow of waveform data compression/reproduction processing--First, the overall flow of waveform data compression/reproduction processing in an embodiment of the present invention will be briefly explained with reference to FIG. First, prepare the waveform to be compressed. An example of how to prepare this is by sampling and storing an original waveform produced by a natural instrument, or by importing a desired original waveform already stored in an external memory, etc. You may do so.

The sampled original waveform may not be used as it is as a waveform to be compressed, but may be subjected to necessary processing before being compressed. Examples of such processing include, for example, processing to extract the amplitude envelope of the original waveform, processing to remove the amplitude envelope from the original waveform and normalize its amplitude level to a uniform level, and conversely, adding an arbitrary amplitude envelope. There are various types of processing, such as processing, processing for applying appropriate filtering, processing for matching the phases of waveforms, and processing for extracting noise components, and one or more of them may be performed. Further, instead of storing the entire processed original waveform in the memory, a predetermined section may be cut out and stored. In this case, processing is also performed to set the start address of the original waveform to be stored in the memory, and if there is a section to be read out repeatedly, to set the address of the section to be repeatedly read out. Also, in order to ensure that repeated reading is performed smoothly,
Necessary waveform processing or the like may be performed.

Next, the waveform data is compressed and written into memory. First, let's start with various "data settings"
I do. One of these "data settings" is a read address setting and a write address setting. The read address setting is to set the address range from which the original waveform that has been subjected to the necessary processing as described above, that is, the waveform to be compressed, is to be read from the memory stored therein. That is, the read start address and read end address of the original waveform memory, or the address for setting the repeat read range, etc. are set. The write address setting is a process of setting an address that specifies in which address range of the memory the waveform data after data compression processing should be written. As described later, in the following examples, the number of bits of one sample of waveform data after data compression processing (
In other words, the data length (data length) does not necessarily match the number of bits at one address in memory, and is variable bit length, and one sample is not stored one-to-one at one address, but is packed and written. It looks like this. Therefore, even if the amount of data (number of samples) of the original waveform is known, it is not possible to know how many storage addresses the waveform data will have after data compression processing until the compression processing is completed. Therefore, in this write address setting, the start address to which the first data should be written can be set, but the write end address cannot be set. As will be explained later, the write end address is automatically stored when the data compression process and write process are completed, so as to facilitate later reproduction process.

Another example of the "data setting" performed here is setting the limit number of bits. This is because the waveform to be compressed, which consists of multiple continuous cycles, is divided into multiple sections (simply referred to as blocks or block sections), and the number of bits of one sample data after data reduction and compression processing is limited for each section. The second method is to arbitrarily set the limit number of bits for each section. In the entire section of the waveform from the start to the end of the sound, there are parts such as the attack part that require fine reproducibility, and there are parts such as the decay part that do not require very fine reproducibility. Therefore, it is efficient to vary the number of bits after data reduction and compression processing depending on the precision required for reproduction, since this also contributes to reducing the number of data bits. For this purpose, the waveform is divided into multiple sections, and the limit number of bits can be arbitrarily set for each section.

Another example of the "data setting" performed here is the setting of weighting coefficients (shift data). In the waveform compression process, while performing a predetermined data compression process, a reduction process is performed to reduce the value of the waveform data according to an arbitrary weighting coefficient either before, during, or after the predetermined data compression process. This is one of the features of this embodiment. Set the weighting coefficient for that purpose. In the example below, since the weighting calculation is performed by data shifting, the weighting coefficients are also referred to as shift data. In the following embodiments, weighting coefficients (shift data) can be set for each block section, and data reduction processing is performed in accordance with independent weighting coefficients for each block section. In addition, here
The method of ``data setting'' is not limited to manual setting using a setting switch or the like, and it is also possible to import already set data from an external source. Also, the weighting coefficient (shift data) may be set manually or by external input at this data setting stage.
The limit bit number may be automatically set and changed in accordance with the above-mentioned limit number of bits during execution of data compression processing.

Next, "data compression and reduction processing" is performed. Here, a "predetermined data compression process" according to a predetermined data compression technique such as a linear prediction method, and a "data reduction process" according to the weighting coefficient (shift data) are performed. The "predetermined data compression process" is a so-called main data compression process that follows a predetermined data compression technique such as a linear prediction method. On the other hand, "data reduction processing" is a process in which the value of waveform data is further reduced according to the weighting coefficient (shift data) at any stage before or after this "predetermined data compression processing", This is, so to speak, a sub-data compression process. Details of this "data compression and reduction processing" will be described later.

Next, the waveform sample data after the "data compression and reduction processing" is processed into variable bit length data. Here, one block section is further divided into multiple sections (these are simply called frames or frame sections), the bit length of the waveform sample data is determined for each frame section, and each waveform sample is arranged so that it fits within that bit length. Trim the number of bits of data. For example, for each frame section, the maximum value of the number of effective bits of waveform sample data is detected, and this is determined as the common bit length of the waveform sample data in that frame section. For example, if there are 5 consecutive "0" bits starting from the most significant bit in the waveform sample data shown in the 16-bit standard, the upper 5 bits of "0" correspond to the actual value. is a negligible bit that does not
The lower 11 bits are valid bits. The maximum value of the number of effective bits within the frame is a bit length that can cover all the effective bits of the waveform sample data within the frame. Therefore, with the bit length determined in this way,
Even if the number of bits of all waveform sample data in that frame is rounded down, all valid bits can be retained. In this way, the waveform sample data is processed so that it becomes variable bit length data for each frame section. This variable bit length processing can be performed automatically based on detection of the maximum value of the number of effective bits, without manual intervention. Of course, it is also possible to manually set and input the data variable bit length for each frame section.

Next, the waveform sample data processed into a variable bit length and subjected to "data compression and reduction processing" is written into the memory. As mentioned above, when storing variable bit length waveform sample data in memory, it is not stored one-to-one at each address, but is packed and stored, so one waveform sample data
Write control is performed in a part of the bit area of one address or across multiple addresses. In addition, various control data such as the compression coefficient used for data compression, the weighting coefficient used for data reduction, and data indicating the number of bits of waveform sample data are hidden so that they can be used during subsequent playback processing. Controls writing by mixing it with waveform sample data as bit data. Details of such write processing will be described later.

In the reproduction process, first, as is generally known, various parameters for musical tone generation (envelope setting parameters, effect setting parameters, timbre control parameters, etc.) are set. Then, a pitch designation operation or a sound production designation operation is performed using a sound generation designation means such as a keyboard, and waveform sample data are sequentially read out from the memory according to the designated pitch. Along with this reading, since the read waveform sample data is data with variable bit length as described above, matching processing is performed to convert it into a predetermined uniform bit length. At the same time, hidden bit data, that is, various control data mixed in the waveform sample data is extracted from the memory read data and separated from the waveform sample data. Details of such bit length matching processing and hidden bit separation processing will be described later. Next, the compressed waveform sample data is converted into a predetermined encoding form (for example, PCM form).
A demodulation process is performed to demodulate the waveform sample data, and an arithmetic process is performed to restore the waveform sample data, which has been reduced by arbitrary weighting, to a uniform weight. At that time, the compression coefficient and weighting coefficient contained in the hidden bit data, that is, the control data, separated as described above are used, and demodulation processing is performed according to the compression coefficient, and weight restoration calculation processing is performed according to the weighting coefficient. . Detailed examples of these processes will be described later. Thus, the final result is a normal data form (e.g. PCM with uniform weights).
The waveform sample data restored to form data) is D/A converted and acoustically produced.

--Explanation of Hardware Configuration Example--Next, FIG. This is explained by: The electronic musical instrument shown in FIG. 2 performs various processes and controls using a microcomputer, and a CPU (central processing unit) 1
0, ROM11 that stores programs and various data,
It includes RAM 12 for working and data storage. The analog signal external input section 13 is for inputting an analog audio signal from the outside, and includes, for example, a microphone. The sampling device 14 samples the analog audio signal input from the analog signal external input section 13 and converts it into PCM-encoded digital waveform sample data.

The waveform memory 15 is a readable and writable memory for storing waveform data, and is composed of, for example, a RAM, and may be made non-volatile by battery backup or other means as necessary. The waveform memory interface 16 controls reading and writing of the waveform memory 15. The disk memory device 17 consists of a large capacity memory for storing waveform data and its driver,
It can be of any type, such as a built-in hard disk or a removable floppy disk. The disk interface 18 is an interface for reading and writing data to the disk memory device 17. The DMA controller 19 performs DM reading and writing of the disk memory device 17.
It is controlled by method A, and the disk memory device 1
It is used when transferring waveform data between 7 and the waveform memory 15.

Waveform data compression processing is performed on waveform sample data obtained by PCM encoding an analog acoustic waveform signal inputted from the analog signal external input section 13. The original waveform data sampled from the outside and to be compressed may be stored in the waveform memory 15 or may be temporarily stored in the disk memory device 17. The aforementioned necessary processing of the original waveform data (e.g., envelope removal, extraction or creation of attack parts and repeat parts) may be performed using the microcomputer of this electronic musical instrument, or may be performed in the disk memory device 17. It is also possible to temporarily store the information, set it in a separate waveform processor or waveform processing computer, and perform the processing there. In the former case, a predetermined area of the RAM 12 or waveform memory 15 may be used as a buffer memory during the processing process, and the final waveform data to be compressed for multiple cycles consisting of a large number of processed sample points is is stored in the waveform memory 15. In the latter case, a plurality of cycles of waveform data to be compressed consisting of a large number of processed sample points are taken into the electronic musical instrument from the disk memory device 17 and stored in the waveform memory 15. Of course, the original waveform data sampled by a separate appropriate sampling system may be stored in a floppy disk or the like, and then imported into this electronic musical instrument from the disk memory device 17 and stored in the waveform memory 15.

Predetermined data compression processing and reduction processing are performed on the waveform to be compressed prepared in the waveform memory 15 as described above. In this embodiment, data compression processing and reduction processing are executed under the control of a microcomputer. The operator section 20 includes various switches for tone selection/setting/control that are normally provided in the operation panel section of an electronic musical instrument, as well as switches and displays for selecting/setting/controlling musical tone elements and various effects. In addition, it may also include switches, displays, etc. used to set the various data mentioned above during waveform processing, data compression, and reduction processing, but the details thereof will be omitted. The waveform buffer memory 21 is a buffer that temporarily stores waveform data that is being processed or has been processed while data compression processing and reduction processing are being executed. The waveform data that has been subjected to data compression and reduction processing stored in the buffer memory 21 is read out, and the processed waveform data is written to the waveform memory 15 while performing the above-mentioned stuffing processing and hidden bit insertion processing.

As is generally known, the keyboard section 22 is equipped with a plurality of keys for specifying the pitch of musical tones to be generated. When reproducing musical tones, various parameters for generating musical tones are set to desired states using the operator section 20, as is generally known. Then, a desired key is pressed on the keyboard section 22. The sound source section 23 reads waveform data from the waveform memory 15 in accordance with various parameter setting states in the operator section 20 and key press information on the keyboard section 22, and generates musical tone signals based on this. In this sound source section 23,
In addition to performing the data bit length matching processing and hidden bit separation processing described above, it also performs demodulation processing of compressed waveform sample data and weight restoration calculation processing. The digital waveform sample signal generated from the sound source section 23 is converted into an analog signal by the D/A converter 24, and is applied to the sound system 25, where it is acoustically produced.

--Description of Blocks and Frames-- The waveform to be compressed stored in the waveform memory 15 is PCM encoded data with a constant bit length (for example, 1 sample is 16 bits), and consists of many sample points. It will come true. When compressing this data, it is handled separately into a block section and a frame section as described above. As an example, one block consists of 1024 samples, and a series of waveforms to be compressed corresponding to one note usually consists of a larger number of samples as a whole. Therefore, the block interval may also be divided into multiple blocks. can. One block consists of 64 frame sections, and therefore one frame section consists of 16 sample points. When compressing and reducing waveform data, processing is performed according to compression coefficients and weighting coefficients unique to each block section. In other words, the compression coefficient and weighting coefficient are common within one block section. In variable bit length processing of waveform data, a unique variable bit length is set for each frame section. In other words, the bit length of the waveform sample data is common within one frame section.

--Outline of Compression and Writing-- FIG. 3 is a flowchart showing an overview of the entire process from compression of waveform data to writing to memory, which is executed under the control of a microcomputer. It is something that First, in step 30, the various data set in the above-mentioned "data setting" are received, and a state is made in which data compression processing can be started. For example, the reading start address of the waveform to be compressed in the waveform memory 15, the limit bit number data for each block, etc. are set according to the operator's wishes as described above, and are received. In the next step 31, a block counter that counts a block number for identifying a block section under compression processing;
The contents of a sample counter that counts sample numbers for identifying sample points within the block are reset to an initial value of 0. Also, the contents of various registers are set to predetermined initial values, respectively. For example, limit bit number data set for each block is set in a register that stores the limit bit number.

In the next step 32, the waveform data of the first block section of the waveform to be compressed is stored in the waveform memory 1 based on the read start address set as described above.
Read from 5. Then, predetermined data compression processing and reduction processing are performed on the waveform data of this first one block section. Specific examples of this data compression processing and reduction processing will be explained later. In the next step 33,
The waveform start address table WST stores data indicating the start address of a memory area in which waveform data to be compressed is to be stored. When writing compressed waveform data into the waveform memory 15, the start address stored in this waveform start address table WST is referred to, and writing of the compressed waveform data is started from that start address. When reading the compressed waveform data, the start address stored in the waveform start address table WST is referred to and reading is started from the start address. In the next step 34, head data of the compressed waveform data is written in the header section of the area for storing the compressed waveform data.

An example of the format of the storage area of compressed waveform data in the waveform memory 15 is shown in FIG. Waveform numbers 1 to n correspond to n types of sounds or tones, and waveform data corresponding to n types of tones or tones can be stored in the waveform memory 15. The number n may be fixed or variable. The waveform start address table WST stores start address data for each waveform number 1 to n. The data area is an area for storing waveform data for each waveform number 1 to n, and has a header section and a waveform sample data storage section corresponding to each waveform number 1 to n. In step 32, start address data is written into the waveform start address table WST corresponding to the waveform number assigned to the waveform to be compressed. This start address data specifies the start address of the waveform data storage area regarding the waveform number in the data area.

Examples of head data stored in the header section include waveform name data, compression flag data, envelope identification data, initial playback control data, and address size data (or end address data). The waveform name data is data indicating a waveform name (for example, a timbre name). The compression presence/absence flag data is a flag indicating whether or not this waveform has been subjected to compression processing. Although this embodiment is described on the assumption that compression processing will be performed, it is also possible to choose not to perform compression processing, so such a flag is provided. Envelope identification data refers to whether this waveform data has a volume envelope attached to it as a whole from the start to the end of the sound, or has an envelope attached only to the attack section, or whether the waveform data has an envelope attached only to the attack section, or No fluctuating volume envelope is attached (
In other words, it is data that identifies the state of applying a volume envelope, such as whether the volume has been standardized to a certain level.

[0029] Initial reproduction control data refers to various types of control data necessary for reproducing waveform data in the first block section and frame section, and is necessary for demodulating compressed waveform sample data. compression coefficient data, weight coefficient data necessary for weight restoration calculation processing,
It consists of the bit number data necessary to match the data bit length, etc. Data compression and weighted reduction processing are 1
Since the variable data bit length is common within a block and the variable data bit length is common within one frame, the initial reproduction control data includes compression coefficient and weighting coefficient data regarding the first block, and bit number data regarding the first frame of the first block. It consists of. Note that the compression coefficient and weighting coefficient data for each block after the second block are written mixed with the waveform sample data as hidden bit data in the storage area for the waveform sample data of the block immediately before the block. . In addition, the bit number data regarding each frame after the second frame of the first block is written as hidden bit data mixed with the waveform sample data in the storage area of the waveform sample data of the frame immediately before the current frame. do. The compression coefficient and weighting coefficient data regarding the first block and the bit number data regarding the first frame of the first block are stored in the header part as initial playback control data since the previous block or frame does not exist. It is.

Address size data (or end address data) is data indicating the total number of addresses (address size) that store waveform data related to this waveform number. This may be data indicating the address where the last waveform sample data related to this waveform number is stored, that is, the end address. As mentioned above, the number of bits of one sample of waveform data after data compression processing (that is, data length) does not necessarily match the number of bits of one address in memory, and the bit length is variable. Since the waveform data is not stored one-to-one in one address, but is written in a packed manner, the total number of storage addresses for the waveform data after data compression processing is determined only after the compression processing is completed. You won't know until you see it. Therefore, the address size data or end address data that becomes clear when data compression processing and writing processing are completed is written in this header section to facilitate later reproduction processing. Therefore, at step 34, address size data or end address data is not written to the header section.

Note that the head data stored in the header section is not limited to the above example, and may be any data as required. For example, if a partial section of the waveform is to be repeatedly read out, loop address data for specifying the section to be repeatedly read out may be stored. Furthermore, when data is selectively compressed according to one of a plurality of data compression methods, data indicating the selected data compression method is stored in the header section to facilitate demodulation. Alternatively, data indicating the name of the original waveform may be stored in the header section, read out and displayed as appropriate, and provided for reference by the performer.

Returning to FIG. 3, in step 35, the waveform data of the next one block section of the waveform to be compressed is read out from the waveform memory 15, and predetermined data is stored in the waveform data of the read one block section. Perform compression processing and reduction processing. The waveform data of the first block subjected to data compression processing and reduction processing in step 33 is temporarily stored in the waveform buffer memory 21 (FIG. 2). The waveform data of the second block that has been subjected to data compression processing and reduction processing through the processing of step 35 is also temporarily stored in the waveform buffer memory 21. In this way, the waveform buffer memory 21 temporarily stores compressed and reduced waveform data of two adjacent blocks (the preceding block and the next block).

In the next step 36, the waveform data of the preceding block of the waveform data temporarily stored in the waveform buffer memory 21 is processed into variable bit length data and written into the waveform memory 15. conduct. Here, when writing the waveform data of the preceding block,
A process is performed in which the compression coefficient and weighting coefficient data regarding the next block whose compression process has been completed in the previous step 35 are mixed with the waveform data and written. Specific examples of this variable bit length processing and writing processing will be described in detail later. Note that in this step 36, bit length processing and writing processing are initially performed on the waveform data of the first block;
In that case, the start address for writing is indicated by the start address table WST.

In the next step 37, it is determined whether all waveform data has been compressed. If the process has not yet been completed, the process goes to step 38 to instruct the next block. Then, the process returns to step 35, and the waveform data for the designated next block is compressed and reduced, and the process of step 36 is performed. In this way, the blocks are sequentially switched and the processing of steps 35 and 36 is repeated. Then, when all waveform data has been compressed, step 3
7 becomes YES, and the process goes to step 39. Step 39
Now, in the header section regarding the waveform number currently being processed,
Write the address size data or end address data regarding the waveform data. Although it will not be explained in detail, when writing compressed waveform data to the waveform memory 15, the address pointer appropriately specifies the write address, so when all waveform data has been compressed, the address pointer will point to the end address. are doing. Therefore, in step 39, the address size data or end address data regarding the waveform data is automatically determined and is written.

--Compression and reduction processing (first embodiment)
-- The waveform data compression and reduction processing performed in steps 32 and 35 is performed under the control of a microcomputer. FIG. 5 shows an example of waveform data compression and reduction processing performed under the control of a microcomputer (the first
FIG. This waveform data compression and reduction processing will be explained according to the functional block diagram shown in the figure, and presentation of the flowchart will be omitted. Of course, it goes without saying that the waveform data compression and reduction processing can be performed not only by control by a microcomputer but also by a hardware circuit according to the functional block diagram shown in the figure. In this first embodiment, the waveform data reduction process according to the weighting coefficient is
This is done before the data compression process using filters. In FIG. 5, the waveform memory reading unit 40
is for reading the waveform data to be compressed from the waveform memory 15, and is given a read address signal under the control of the control section 41. The control section 41 is for overall control and provides control signals to each section. The block counter 42 counts the block number currently being processed. The sample counter 43 counts the number of samples currently being processed.

As described above, in the initial state (at step 31 in FIG. 3), the block counter 42 and sample counter 43 are set to the initial value 0 under the control of the control section 41.
Reset to . Then, each time the waveform data for one sample is compressed and reduced, the sample counter 43 is incremented by one.
Count up. Furthermore, the block counter 42 is incremented by one each time one block is processed. Further, the sample counter 43 is reset to 0 when starting processing for one block. Also, the read start address that specifies the range of the waveform to be compressed is set to the control unit 4.
1, and the read address of the waveform memory 15 is determined by adding the count value of the sample counter 43 to this start address, and adding the count value of the block counter 42 with a predetermined weight (1024 times the weight). , specified. This read address data is
It is given to the waveform reading unit 40 and specifies the address of sample data to be read from the waveform memory 15. Further, since one frame section is made up of 16 samples, the bits from the fifth bit onward of the sample counter 43 are also used as data indicating the frame number.

The limit bit number register 44 stores data indicating the limit bit number set in advance for each block section, as described above, and the limit bit number register 44 stores data indicating the limit bit number set in advance for each block section. Each limit bit number instruction data is taken into the register 44. In accordance with the output of the block counter 42, that is, the block number data, limit bit number instruction data set corresponding to the block currently being processed is read from the register 44. The shift data generation unit 45 generates shift data, that is, weighting coefficients, and generates appropriate shift data, that is, weights, taking into account the limit bit number instruction data and other data regarding the block given from the limit bit number register 44. Generate coefficients. This shift data generating section 4
The shift data generated from 5 is registered in the shift data register 46. The shift data, that is, the weighting coefficient, registered in the shift data register 46 is given to a shift circuit 47 (that is, a weight calculation circuit).

The shift circuit 47 inputs the waveform sample data read out from the waveform memory 15 via the waveform reading section 40, and shifts the value of this sample data downward by the number of bits corresponding to the shift data. , performs a reduction operation on the value of the sample data. For example, if waveform sample data with an effective bit count of 10 bits is shifted to the lower order by 2 bits, the effective bit count of the waveform sample data will be reduced to 8 bits. The waveform sample data output from the shift circuit 47 is input to the compression filter section 48. The compression filter section 48 performs data compression processing using a filter. The filter coefficients of the compression filter section 48, that is, the compression coefficients, are calculated for each block section based on the waveform sample data for each block section according to the linear prediction method. For this purpose, a Hamming window multiplier 49, a Hamming buffer 50,
A coefficient generation calculation section 51 and a coefficient register 52 are provided. A detailed example of this will be explained later. The calculated compression coefficient is stored in the coefficient register 52 and input to the compression filter section 48.

The waveform sample data output from the compression filter section 48 is temporarily stored in the block buffer 55 via the block buffer write control section 53. The data stored in the block buffer 55 is appropriately read-controlled by the block buffer read control section 54 and input to the compression filter section 48 . This is because a one-stage filter circuit is used as the compression filter section 48, and a two-stage compression filter is constructed by circulating data there. Therefore, to be more precise, the waveform sample data output from the compression filter section 48 in the second round is data that has been compressed. The bit number detection section 56 detects the effective number of bits of the compressed waveform sample data output from the compression filter section 48. For example, in compressed waveform sample data that is output according to the 16-bit standard, the upper "0" bits are excluded, and the number of bits from the most significant bit that is "1" to the lower bit is calculated. Detected as the number of effective bits. The bit number detection unit 56 detects the maximum value of the effective bit number for each frame section and outputs it as frame-by-frame bit number data FBN. This frame-by-frame bit number data FBN is
The data is temporarily stored in the block buffer 55 via the block buffer write control unit 53, and used during variable bit length processing for each frame. Further, the bit number detection unit 56 compares this frame-by-frame bit number data FBN with the bit number data stored in the bit number register 57, and if the frame-by-frame bit number data FBN found this time is larger, then this is stored in the bit number register 57.

In this way, when processing for one block is completed, the bit number data finally stored in the bit number register 57 is the maximum value of the effective number of bits in that block, and this is referred to as the maximum bit number data. It is given to the shift data generating section 45 as MBN. When the shift data generating unit 45 finishes processing one block, it compares the limit bit number data of the block given from the limit bit number register 44 with the maximum bit number data MBN, and selects the maximum bit number data MBN. If is large, then
Since the compressed waveform data exceeds the limit bit number set for the block, the control unit 41 is ordered to redo the compression and reduction processing for the block, and the shift data given to the shift data register 46 is Increase the value of . In this way, the shift data, that is, the value of the weighting coefficient, is initially set to an appropriate predetermined value (a constant value or a value arbitrarily set for each block),
Judging from the relationship with the limit bit number set for the block, this shift data, that is, the value of the weighting coefficient, is automatically switched, and the compression and reduction processing for the block is re-performed, and finally, The shift data, that is, the weighting coefficient, is automatically controlled so that the data after data compression and reduction processing falls within the limit number of bits set corresponding to the block. The finally determined shift data, that is, the weighting coefficient regarding the block is temporarily stored in the block buffer 55 via the block buffer write control section 53, and later written to the waveform memory 15 together with the waveform sample data. Of course, instead of adopting such an automatic method of determining shift data, that is, weighting coefficients, manual setting may be performed for each block.

When the shift data generating section 45 finishes processing one block, it compares the limit bit number data of the block given from the limit bit number register 44 with the maximum bit number data MBN, and calculates the maximum bit number data. M
If the BN is smaller, the compressed waveform data is within the bit limit set for the block, so the block is A count-up instruction signal is given to the block counter 42 and the control section 41. As a result, the block counter 42 is incremented by one, giving an instruction to process the next block. The block buffer 55 is a buffer memory included in the waveform buffer memory 21 of FIG. 2, and its memory format is illustrated in FIG. 6. This block buffer 55 includes waveform data buffers BW(A) and BW(B).
Each block of waveform sample data can be temporarily stored, and a total of two blocks of waveform sample data can be temporarily stored. Which buffers BW(A), BW(B
) is alternately switched depending on whether the block count value is even or odd. The reason for having the waveform data buffers BW(A) and BW(B) for two blocks is that when writing the waveform data of a certain block to the waveform memory 15, the compression coefficient and This is to control the shift data (weighting coefficient) to be written together as hidden bit data. Note that the two adjacent blocks temporarily stored in the block buffer 55 are referred to as block A and block B for convenience.

Parameter buffer BP(A), BP(B
) is for temporarily storing control data to be written mixed with waveform sample data as hidden bit data, and contains the compression coefficient and shift data (weighting coefficient) of the block A or B, and the control data of the block A or B. Bit number data for each frame (frame-specific bit number data FBN) is stored. The header buffer is a buffer for temporarily storing head data to be stored in the header portion of the waveform memory 15. The filter delay buffer is for temporarily storing the signal data held at the end of the compression process regarding the previous block in the delay circuit unit for performing unit delay of the signal in the compression filter unit 48. As mentioned above, this is in preparation for redoing the compression and reduction processing for one block of data if the number of bits of the waveform sample data after compression and reduction processing does not fall within the bit limit. be. That is, in order to enable such a redo, the contents of the signal data in the delay circuit section in the compression filter section 48 must be reproduced to the contents immediately after the compression processing for the previous block is completed. To this end, the signal data held at the end of the compression processing for the previous block in the delay circuit section in the compression filter section 48 is temporarily stored in the filter delay buffer, and is requested to be redone in the compression processing for the next block. At this time, the data stored in the filter delay buffer is set in the delay circuit section in the compression filter section 48 to reproduce the initial state for performing compression processing on the block.

Returning to FIG. 5, the variable bit length processing and writing processing section 58 reads out one block of compressed data stored in the block buffer 55, and divides this data bit number into the maximum bit number for each frame section. In addition to performing "variable bit length processing" to trim to the bit size of the numerical data FBN, the next block's compression coefficient and shift data (weighting coefficient) are mixed and written in the waveform sample data, and the next frame's variable bits are This process performs a process of writing data indicating a number FBN mixed with waveform sample data. A detailed example will be explained later.

--Description of Compression Filter Section (First Embodiment)-- FIG. 7 conceptually shows an example of the basic configuration of the shift circuit section 47 and the compression filter section. 48A and 48B are connected in cascade in two stages. The first stage filter 48A transfers the reduced waveform sample data output from the shift circuit section 47 to the delay section DA0.
and multiplier M0 for the output of this delay section DA0.
Multiply by the coefficient a0. Also, the output of delay section DA0 is set to 2
The output signal is input to the second delay section DA1, and the output of this delay section DA1 is multiplied by a coefficient a1 in a multiplier M1. thus,
An adder ADD adds the product of data from one sample before and data from two samples before multiplied by a coefficient, and the sum (convolution sum) is subtracted from the data at the current sample point by a subtractor SUB. The output of the subtracter SUB is input to the second stage filter 48B. The second-stage filter 48B has the same configuration as the first-stage filter 48A, but has different coefficients b0 and b1. Adopting the configuration in which the secondary filters 48A and 48B are connected in two stages in this manner has the advantage that data compression processing can be performed efficiently and that setting of compression coefficients is also facilitated. Furthermore, since a hardware circuit for one stage of secondary filter is prepared as the compression filter section 48 and used in a time-division manner, the hardware configuration becomes simple.

FIG. 8 shows an example of the hardware circuit of the compression filter unit 48 consisting of one stage of secondary filter, and includes a subtracter 59 for subtracting the convolution sum from the input waveform sample data at the current sample point. The output is output through a limiter 60. Further, by adding the convolution sum to the output of the limiter 60 in an adder 61, the input waveform sample data at the current sample point is reproduced, and this is sent to the delay unit 63 via the limiter 62.
, 64. In the multipliers 65 and 66, each delay unit 63
, 64 are multiplied by compression coefficients c0 and c1, and an adder 67 calculates the convolution sum. Compression coefficient c0,
The values of c1 are a0 and a1 when this compression filter section 48 is used as the first stage filter 48A, and b0 and b1 when used as the second stage filter 48B. Note that when performing the above-mentioned redo process, the delay units 63 and 6
4. Contents of the filter delay buffer (signal data held at the end of compression processing regarding the previous block)
Set.

--Generation of compression coefficient-- Next, the Hamming window multiplier 49 and the Hamming buffer 5
An example of a compression filter coefficient generation operation procedure according to the linear prediction method using the coefficient generation operation unit 51 and the coefficient register 52 will be described with reference to FIG. First, one block (1024 samples) of waveform sample data is sequentially read from the waveform memory 15, input to the Hamming window multiplier 49, and multiplied by the Hamming window function. In this case, the Hamming window function also consists of 1024 samples, and each sample value of the Hamming window function is multiplied by one block (1024 samples) of waveform sample data. Then, the product Sn (where n=0, 1, 2, 3,...
1023) is stored in the humming buffer 50. Next, the coefficient generation calculation unit 51 calculates autocorrelation functions Ri for i=0, 1, and 2, respectively, according to the following equations based on the waveform sample data Sn weighted by the Hamming window. Ri=ΣSnSn+i (However, the cumulative range of Σ is from n=0 to 1023) Next, based on the autocorrelation function Ri obtained as above,
Compression coefficients c0 and c1 are determined according to the following equations. c0=(R1・R0-R1・R2)/(R0・R0-R
1・R1)c1=(R2・R0−R1・R1)/(R0
・R0-R1・R1) When calculating the first stage compression filter coefficients, the above c0, c1 correspond to a0, a1, and when calculating the second stage compression filter coefficients, the above c0, c1 correspond to a0, a1. c1 corresponds to b0 and b1.

Next, the compression filter coefficients c0,c just found
Check whether 1 is the first stage, and if so, use the compression filter coefficients c0, c1 that you just found, that is, a0, a1.
is stored in the coefficient register 52, and the waveform sample data regarding the block currently being processed is sequentially read out from the waveform memory 15 and input to the compression filter unit 48, and the compression filter coefficients c0, Compression processing according to c1, that is, a0 and a1 is performed. In this way, the output of the first stage filter 48A is obtained, inputted to the Hamming window multiplier 49, and multiplied by the Hamming window function. Then, the same process as described above is repeated, the product Sn is stored in the Hamming buffer 50, the autocorrelation function Ri is determined, and the compression coefficients c0 and c1 are determined. This time, the obtained compression coefficients c0, c1 correspond to the second-stage compression filter coefficients b0, b1, and are stored in the coefficient register 52, and the process ends. Although the explanation has been mixed, after calculating the compression filter coefficients a0, a1, b0, b1 for the block in this way, the compression processing of the waveform sample data of the block is performed using the compression filter section 48 as described above. It is done to.

--Explanation of variable bit length and hidden bits--
- One block of compressed data stored in the block buffer 55 is written to the waveform memory 15 through processing by the variable bit length processing and writing processing unit 58. FIG. 10 is a functional block diagram for explaining the processing operation of the variable bit length processing and writing processing section 58. Further, FIG. 11 schematically shows the procedure of variable bit length processing and writing processing executed by the variable bit length processing and writing processing section 58. In other words, FIG. 11 is step 3 of FIG.
6 is shown in some detail, and FIG. 10 is a functional block diagram that performs processing equivalent to the procedure performed in FIG. 11. First, the outline of the specifications of the variable bit length processing and writing processing of waveform sample data and the writing processing of hidden bit data performed by the variable bit length processing and writing processing section 58 is as follows. In addition, Figure 1
2 shows an example of the format of variable bit length processed waveform sample data and hidden bit data.

1) The number of bits of variable bit length waveform sample data is common within one frame, and is variable for each frame. Specifically, based on the frame-by-frame bit number data FBN, which is the maximum value of the effective bit number in the frame,
Each sample data in the frame is extracted from the lower bits by the number of bits of the FBN. Thereby, the number of bits of each sample data in the frame can be reduced by ensuring valid bits. Figure 1
In example 2, the size or bit length of the waveform data in frame 0 is 11 bits, and in frame 1 it is 10 bits.
bit, frame 2 is 12 bits.

2) Hidden bits a) Bit number instruction data for each frame The data that indicates the number of bits of the waveform sample data processed into a variable bit length for each frame as described above is the waveform sample of the previous frame. Mix it with the data and write it as hidden bit data. This bit number instruction data is 4-bit data, which is separated one bit at a time.
They are respectively positioned on the lower side of the least significant bit LSB of the first four samples of waveform data of the previous frame. In the example of FIG. 12, each bit of the hidden bit data corresponding to the bit number instruction data is set to HB0, HB1, HB2, HB3.
It is shown in The binary coding weight of each hidden bit is such that HB3 is the highest, followed by HB2, HB1, and HB0. In the example of FIG. 12, the hidden bit HB3 of frame 0
The contents of ~HB0 are "1010" and indicate the data length of the next frame 1 = 10 bits. Further, the contents of hidden bits HB3 to HB0 of frame 1 are "1100", indicating that the data length of the next frame 2 is 12 bits. At sample points having these hidden bits HB0 to HB3, the data length is substantially 1 bit longer than other sample points within the same frame. However, if such hidden bits HB0 to HB3 are not present, that is, the actual size of the waveform data is constant within the same frame. Note that regarding the first frame 0 of the first block, since there is no preceding frame, the number of bits indicating data is written in the header section as described above. Note that the reason why the bit number instruction data of the next frame is mixed and written with the waveform data of the previous frame is so that the bit number instruction data can be read out in advance during playback processing. It's for a reason.

b) Shift data (weighting coefficient) Shift data (weighting coefficient) for each block is mixed with the waveform sample data of the previous block and written as hidden bit data. This shift data (weighting coefficient) is 4-bit data, which is separated one bit at a time and is divided into 4 bits from the 5th to the 8th frame of the first frame 0 of the previous block.
They are respectively positioned on the lower side of the least significant bit LSB of the sample's worth of waveform data. In the example of FIG. 12, each bit of hidden bit data corresponding to shift data (weighting coefficient) is indicated by HS0, HS1, HS2, and HS3.

c) Compression coefficients Four compression coefficients a0, a1, b0, for each block
b1 is mixed with the waveform sample data of the previous block and written as hidden bit data. Each compression coefficient is 8-bit data, separated by 1 bit, and for coefficient b1, the first frame 0-9 of the previous block
The coefficient b0 is located at the lower side of the least significant bit LSB of the 8 samples of waveform data from the 1st to the 16th, and the coefficient b0 is located at the lower side of the least significant bit LSB of the 8 samples of waveform data from the 1st to the 16th. are respectively positioned on the lower side of the least significant bit LSB of the waveform data,
3rd frame 2 of previous block for coefficient a1
The coefficient a0 is located on the lower side of the least significant bit LSB of the 8 samples of waveform data from the 9th to the 16th of They are respectively positioned on the lower side of the least significant bit LSB of the waveform data. In the example of FIG. 12, each bit of hidden bit data corresponding to one compression coefficient is indicated by HC0 to HC7.

3) Packing Storage FIG. 13 shows an example of a memory format when variable bit length data having the format shown in FIG. 12 is actually packed into the waveform memory 15 and stored. In the case of FIG. 13, the size of the storage address of the waveform memory 15, that is, the data length, is fixed at 16 bits per address, and each address is accessed by an address signal. Data of one sample point is not stored per address, but data of variable bit length is stored as appropriate. For example, the least significant bit of address A0 is a hidden bit HB0 accompanying the waveform data of sample point 0.
is stored, the waveform data of sample point 0 is stored in the upper 11 bits, the hidden bit HB1 accompanying the waveform data of sample point 1 is stored in the upper 1 bit, and the waveform data of sample point 1 is stored in the upper 3 bits. The lower three bits of are stored. Further, the remaining upper 8 bits of the waveform data of sample point 1 are stored in the lower 8 bits of address A1. As shown in the figure below, the waveform data of each sample point and hidden bit data are packed and stored. In FIG. 13, the number written in the address area indicates the sample point number of the waveform data stored therein, and the shaded area indicates the area where hidden bits are stored. In this way, in order to efficiently pack data and store it in the waveform memory 15, one piece of data is divided as appropriate and stored across a plurality of addresses.

--Variable bit length processing and writing processing--An example of variable bit length processing and writing processing will be explained with reference to FIGS. 10 and 11. In FIG. 10, the control unit 68
is for controlling the entire operation of the variable bit length processing and writing processing section 58, and it is assumed that this control section 68 executes a processing program as shown in FIG. 11 to control the variable bit length processing and writing processing. good. The sample and frame counter 69 uses a sample clock SC to set the sample number SN of the waveform data to be read from the block buffer 55.
The frame number FN is incremented according to K, and the frame number FN is also incremented every 16 samples. The sample reading unit 70 includes a sample and frame counter 6
Control is performed to read waveform data from the block buffer 55 in accordance with the sample number SN specified by 9. The least significant bit BNLSB of the block number data counted by the block counter 42 (FIG. 5) is given to the sample reading unit 70 to inform whether the block number for which the compression process has been completed is even/odd. As a result, block buffer 5
5 two waveform data buffers BW(A), BW(B)
(FIG. 6) from which waveform data should be read. For example, even block numbers 0, 2, 4
,... are stored in the waveform data buffer BW(A), and waveform data of odd block numbers 1, 3, 5,... are stored in the waveform data buffer BW(B). Least significant bit of data BNLSB
If is “0”, the compression process has just been completed for the even numbered block, and this is the waveform data buffer BW(A).
The previous block has an odd block number and is stored in the waveform data buffer BW(B). Therefore, the preceding block is an odd numbered block stored in the waveform data buffer BW(B), and the waveform data is controlled to be read from this buffer BW(B). On the other hand, if the least significant bit BNLSB of the block number data is "1", the compression process has just been completed for the odd-numbered block, and the preceding block is the even-numbered block stored in the waveform data buffer BW(A). Since it is a block of numbers, this buffer BW (
Control is performed so that waveform data is read from side A).

The shift data reading unit 71 reads the parameter buffers BP(A) and BP(
Controls reading of shift data (weighting coefficients) from B). The least significant bit BNLSB of the block number data is given to this shift data reading section 71 to inform whether the block number that has completed the compression process is even/odd. This results in
Two parameter buffers BP of block buffer 55
(A) and BP(B) (FIG. 6) from which to read the shift data is instructed. For example, in the above example, if BNLSB is "0", the waveform data buffer B is used as the preceding block (odd numbered block).
Since the data of W(B) is read and written to the waveform memory 15, the next block (even numbered block)
The parameter data regarding is stored in the parameter buffer BP (
A), the shift data reading unit 71 reads the shift data regarding the next block from the parameter buffer BP(A). On the other hand, if BNLSB is "1", waveform data buffer B is used as the preceding block (even numbered block).
Since the data of W(A) is read and written to the waveform memory 15, this shift data reading section 71 stores the shift data regarding the next block in the parameter buffer BP.
Read from (B).

The compression coefficient reading unit 72 reads parameter buffers BP(A) and BP(B) in the block buffer 55.
Control is performed to read the compression coefficients a0, a1, b0, and b1 from. As described above, the least significant bit BNLSB of the block number data is given to this compression coefficient reading unit 72, and the block buffer 5
5 two parameter buffers BP(A), BP(B)
The compression coefficient for the next block is read from one of the blocks. The next frame bit number data reading unit 73 reads frame-by-frame bit number data FB regarding the next frame according to the frame number FN from the sample and frame counter 69.
N, parameter buffer B in block buffer 55
Control is performed to read from either P(A) or BP(B). For example, the least significant bit BNLSB of block number data
If is "0", the waveform data stored in the waveform data buffer BW(B) as the preceding block is read and written to the waveform memory 15, so that the next frame is read from the parameter buffer BP(B) of the preceding block. The bit number data FBN for each frame is read out. Here, the read bit number data is written as hidden bit data.

The current frame bit number data reading unit 74 reads frame-by-frame bit number data FBN regarding the frame currently being processed according to the frame number FN from the sample and frame counter 69, and reads it into the parameter buffer BP (in the block buffer 55). Control is performed to read from either A) or BP (B). For example, if the least significant bit BNLSB of the block number data is "0", the preceding block is the B block as described above, so the bit number data for each frame regarding the frame currently being processed is extracted from the parameter buffer BP(B). Read FBN. Here, the read bit number data is used to round down the number of bits of the waveform data of the frame. The hidden bit instruction unit 75 includes a sample and frame counter 69
According to the sample number SN of , it is determined whether the sample point is where hidden bit data should be inserted and what type of data should be embedded as hidden bit data. As explained with reference to FIG. 12, the bit number data of the next frame, the shift data of the next block, and each compression coefficient of the next block are the lower order of the waveform data of a predetermined sample number (sample number within one block). Since the data is distributed and embedded as hidden bit data, the predetermined sample number is determined and an appropriate instruction is given.

The hidden bit adding unit 76 adds a predetermined value to the lower part of the waveform sample data read out from the sample reading unit 70 at the sample number to which hidden bit data is to be added, in accordance with the instruction from the hidden bit specifying unit 75. This adds one bit of hidden bit data. Data to be embedded as hidden bit data (4-bit shift data, 8-bit compression coefficients a0 to b1, 4-bit data) are received from the shift data reading unit 71, compression coefficient reading unit 72, and next frame bit number data reading unit 73, respectively. Next frame bit number data) is given to the hidden bit adding section 76. In the hidden bit adding unit 76, as explained with reference to FIG. 12, corresponding to a predetermined sample number,
One predetermined bit is selected from among them and added as hidden bit data to the lower part of the waveform sample data of the sample number. The addition section 77 includes a hidden bit instruction section 75.
In response to an instruction from , 1 is added to the bit number data of the current frame read from the current frame bit number data reading section 74 at the sample number to which hidden bit data is to be added. As a result, at the sample point where hidden bit data is added, the value of the current frame bit number data is increased by 1 corresponding to the addition of 1 bit.

The waveform data output from the hidden bit addition section 76 is input to the upper bit input MSBIN of the data synthesis section 78.
given to. Lower bit input LS of data synthesis unit 78
The output of selector 79 is applied to BIN. The data synthesis unit 78 controls the synthesis position so that the waveform data applied to the input MSBIN is located above the bit position specified by the bit position instruction data BPP output from the bit position instruction counter 80. The data of the upper bit input MSBIN and the data of the lower bit input LSBIN are combined to create 32-bit data. The 32-bit data output from the data synthesis section 78 is delayed by one sample clock in the buffer register 81. Of the 32-bit output of the buffer register 81, the upper 16 bits MSB16 are given to the "1" input of the selector 79, and the lower 16 bits LSB16 are given to the "0" input of the selector 79.
given to.

[0060] The bit position indication counter 80
This is a modulo 16 counter that adds the bit number data of the current frame outputted from 7 in accordance with the sample clock SCK, and outputs bit position indication data BPP in accordance with the count value. Further, when the count value overflows (exceeds 16), an overflow signal OVF is output. The overflow signal OVF is applied to the selection control input of the selector 79, and if no overflow has occurred, the lower 16 of the buffer register 81 is applied.
The bit output LSB16 is selected via the “0” input of the selector 79, and the lower bit input LSB of the data synthesis unit 78 is selected.
Enter IN. On the other hand, if an overflow occurs, the upper 16 bits output MSB1 of the buffer register 81
6 is selected via the "1" input of the selector 79 and inputted to the lower bit input LSBIN of the data synthesis section 78. Further, the overflow signal OVF is applied to the waveform memory writing unit 82 and instructs the waveform memory 15 to write the lower 16-bit output LSB 16 of the buffer register 81 when an overflow occurs. Waveform memory 15
The write address of is indicated by the write address counter 83. The write address counter 83 is initially set with a write start address, and thereafter incremented in accordance with the overflow signal OVF.

The data synthesizing section 78 guides the data input to its upper bit input MSBIN to one of the 32 bit output bit position ranges according to the instruction of the bit position instruction data BPP, and outputs the data. Also, the 16-bit data input to the lower bit input LSBIN is directly guided to the lower 16 bit range of the 32-bit output and output, but the bit position to which the data input to the upper bit input MSBIN is guided is as follows. Data input to the upper bit input MSBIN is output with priority. This is because the data input to the upper bit input MSBIN is stuffed into the upper "0" bit of the 16-bit data input to the lower bit input LSBIN, so in effect, the data input to the upper bit input MSBIN is The data will appear on the output side as is. The bit position instruction data BPP takes 16 values from 0 to 15, and this value specifies the bit position of one of the lower 16 bits of the 32-bit output of the data synthesis section 78. upper bit input MSBI
The data input to N is guided so that the least significant bit of the data comes to N. When the data of sample number 0 is input to the upper bit input MSBIN of the data synthesis section 78, the value of the bit position instruction counter 80 is 0, and the bit position instruction data BPP indicates 0, and the data synthesis state is changed. An example is shown in FIG. At this time, the data of sample number 0 inputted to the upper bit input MSBIN of the data synthesizing section 78 is packed closer to the least significant bit of the data synthesizing section 78, as shown in FIG. 14(a).

At the next sample timing, the data of the lower 16 bits LSB16 of the data synthesizer 78 is applied to the lower bit input LSBIN of the data synthesizer 78 via the register 81 and the "0" input of the selector 79. At this time, the bit position indication counter 80 is counting the number of bits x of the data of sample number 0, and the bit position indication data BPP indicates x. Also, at this time, the data of the next sample number 1 is input to the upper bit input MSBIN of the data synthesis section 78, and this is
In response to the instruction of BPP=x, as shown in FIG. 14(b), data is packed into the bit position range immediately above the data of sample number 0. When the data shown in FIG. 14(b) is output from the register 81, the bit position indication counter 80 further adds the number of bits x of the data of sample number 1, and the count value becomes 2x. This value 2x is
Assume that the value causes an overflow. Then, due to this overflow, the lower 16 bit data LSB16 of the register 81 is written into the waveform memory 15. In other words, the data of sample number 0 and part of the data of sample number 1 are written tightly packed into one address=16 bits.

At that time, the selector 79 selects the register 81
The upper 16 bit data MSB16 of
Enter N. That is, the remainder of the data of sample number 1 is input to the lower bit input LSBIN of the data synthesis section 78. At this time, data of the next sample number 2 is input to the upper bit input MSBIN of the data synthesis section 78. Then, the value of the bit position indication counter 80 is B
PP=2x-16, and as shown in FIG. 14(c), the data of sample number 2 is packed into the bit position range immediately above the remaining data of sample number 1. In this way, only data corresponding to the effective number of bits (plus 1 if hidden bit data is included) indicated by the bit number data is extracted, packed without waste, and written into the waveform memory 15.

Next, the entire flow of variable bit length processing and writing processing will be explained according to FIG. Set to . Then, when starting processing of each block, the least significant bit BNLSB of the block number data at that time is taken in and used for the above-mentioned even/odd determination of the block number. Next, the sample and frame counter 69 is reset. Then, the waveform data specified by the sample number SN of the sample and frame counter 69 is read out from one waveform data buffer BW (A) or BW (B) in the block buffer 55 . Then, according to the sample number SN, the bit number data of the next frame, the shift data of the next block, and each compression coefficient of the next block are added to the waveform data as hidden bit data. and,
The number of bits of data is determined according to the bit number data of the current frame and the presence or absence of hidden bits, the number of bits of data is rounded down to this number of bits, and processing is performed to fill and write into the waveform memory 15 as described above. Then, the above process is repeated for one frame. Thereafter, the parameter for the number of bits per frame is changed and the above-described process is repeated. and,
When processing for one block is completed, this processing ends.

Note that when the writing process for all blocks related to the waveform is completed, the write address counter 83 of the waveform memory 15 indicates the end address. In step 39 of FIG. 3, the end address data at this time is stored in the header section, or size data indicating the storage address range is obtained from the difference between this end address and the write start address and is stored in the header section. do.

--Reproduction Process-- An example of a process for reproducing compressed and reduced waveform data stored in the waveform memory 15 and generating sound will be described below. The sound source section 23 in FIG. 2 performs reproduction processing, and one embodiment thereof is shown in FIG. 15. In FIG. 2, the microcomputer scans the keyboard section 22 and the operator section 20, detects key presses and key releases, detects the selected state of tone, etc., and selects a plurality of key press information (for example, 8).
Performs processing for assigning to one of the musical tone generation channels. The microcomputer outputs for each channel a key code KC indicating the key assigned to each channel and a key-on signal KON indicating whether the assigned key is kept pressed or released, and also outputs the selected tone. Tone color number data TN indicating the key press and touch data TD indicating the key press touch.
Output. The output of the microcomputer is taken into the sound source section 23 via the interface 90. The interface 90 outputs the key code KC of the key assigned to each channel and the key-on signal KON in a time-sharing manner according to predetermined channel time-sharing timing, and also outputs the tone number data TN and touch data TD of the selected tone. do. The sound source section 23 performs various processes on an eight-channel time-division basis based on the data provided from the interface 90, and generates eight-channel musical waveform signals on a time-division basis.

The F number generation circuit 91 generates an F number, which is a constant corresponding to the pitch frequency of the musical tone to be generated, in accordance with the key code KC given from the interface 90, and is made of, for example, a ROM or a table. . This F number is repeatedly accumulated by an accumulator 92, and a carry signal from an appropriate digit is output as a note clock pulse NCL. This note clock pulse NCL corresponds to the pitch frequency of the musical tone to be generated, and instructs to increment the sample point every pulse. This note clock pulse NCL, ie, sample point increment, is a command to read data for one sample point to the waveform memory 15 for each pulse. The clock and timing signal generation circuit 93 generates a system clock pulse and various other timing signals and supplies them to each circuit, and also forms and outputs a key-on pulse and a key-off pulse based on the key-on signal KON given from the interface 90. . The system clock pulse is a two-phase clock, and one period corresponds to the time slot width of one channel. The first key-on pulse KONP1 is 1 in the time slot of the corresponding channel when the key-on signal KON rises from "0" to "1", that is, at the start of key depression.
This is a pulse that becomes “1” only once. The second key-on pulse KONP2 is a pulse that becomes "1" only once in the time slot of the corresponding channel in the next time-division channel cycle after the key-on pulse KONP1 becomes "1". The key-off pulse KOFP occurs when the key-on signal KON falls from "1" to "0", that is, when the key is released.
This is a pulse that becomes "1" only once in the time slot of the corresponding channel. These pulses are given to each circuit in order to control processing in synchronization with key-on and key-off.

The parameter data generation circuit 94 sets the tone of a musical tone, performs touch control, and performs key scaling based on the tone number data TN, touch data TD, and key code KC given from the interface 90. Generate various parameter data for Examples of parameter data generated in consideration of the selected tone, key touch, and key scaling are envelope setting data EVD for setting the envelope, start address data SA specifying the waveform readout start address, and initial There are initial data length data ILENG indicating the data bit length of the first frame of the block, compression coefficient data ICO regarding the first block, shift data ISF regarding the first block, etc. Among these parameter data, those stored in the header section of the waveform memory 15 are as follows:
Readout via waveform memory interface 16.

The envelope generator 95 creates and outputs envelope waveform data ED in a time-division manner for each channel based on the key-on pulses KONP1 and KONP2, the key-off pulse KOFP, and the envelope setting data EVD. The data retrieval and reproduction section 96 includes an accumulator 92
According to the note clock pulse NCL given from
A sample point increment is performed to specify the sample point number of the data to be read from the waveform memory 15, and the address where the data to be read is stored is specified from this sample point number and the data length of the data to be read, and the address signal is Generate CA. This address signal CA is a relative address within an area that stores waveform data corresponding to one tone, so by adding start address data SA, which is an absolute address, to this address signal, the generated address signal can be changed to an absolute address. It is converted into a signal and inputted into the waveform memory 15 as an address. The waveform memory 15 reads out 16-bit stored data from one storage address in accordance with the input address signal.

Further, the data retrieval/reproduction unit 96 receives the 16-bit data R read out from the waveform memory 15.
D is input, and data for one necessary sample point having a variable bit length is extracted from it. Furthermore, if data for one necessary sample point is stored across multiple addresses, the necessary data is connected and extracted from the data read from the multiple addresses. Furthermore, the data retrieval/reproduction section 96 also includes the waveform memory 15.
"Hidden bit" data is extracted from the 16-bit data read from the 16-bit data, and these are connected to create each hidden bit data HB0 to HB3, HS0 to HS3.
, HC0 to HC7, and extracts bit number instruction data for each frame, shift data for each block, and compression coefficient data for each block stored in the waveform memory 15 as "hidden information". Using the bit number instruction data extracted from the hidden bits, waveform memory 1
From the 16-bit data read from 5,
Processing is performed to extract data for one sample point having a variable bit length. In the first frame, the initial data length data ILENG from the parameter data generation circuit 94 is used to extract the variable length data for one sample point.

The waveform sample data CWD extracted by the data extraction and reproduction section 96 is input to the compressed data demodulation circuit 97, and is converted into normal PCM encoded waveform data W.
Demodulates to D. In this case, the compression coefficients a0, a1, b0, and b1 extracted from the hidden bits are used to perform compression and demodulation calculations on the waveform data of the corresponding block section. Note that in the first block section, demodulation calculation is performed using the initial compression coefficient data ICO from the parameter data generation circuit 94. The waveform sample data WD output from the compressed data demodulation circuit 97 is input to a shift circuit 98 and restored to a weight common to all blocks. In this case, the shift data SFD extracted from the hidden bits is used to restore the weight of the waveform data in the corresponding block section. In the first block section, initial shift data ISF from the parameter data generation circuit 94 is used to generate shift data SFD, and weight restoration calculation is performed. The data shift direction by shift circuit 98 is exactly opposite to the shift direction by shift circuit 47 in FIG.

The waveform data output from the shift circuit 98 is multiplied by the envelope waveform data ED from the envelope generator 95 in a multiplier 99, and the volume amplitude level is controlled according to the envelope waveform. Reproduction and control of the waveform data up to the multiplier 99 is performed on a time-division basis for each channel, and the output of the multiplier 99 is accumulated between each channel in a channel accumulator 100 during one channel time-division cycle. and sum the musical waveform data of all channels. This output is the digital/analog converter 2
4 (FIG. 2) and acoustically produced via a sound system 25.

--Description of data retrieval and playback section--Figure 1
6 is a block diagram showing an example of the internal configuration of the data retrieval/reproducing section 96, in which the note clock pulse NCL for instructing data reading for each sample point is connected to a sample counter 101, a data length counter 102, and an address counter 1.
03, the data position reproducing circuit 104, the hidden bit reproducing circuit 105, and the data register 106, respectively. The sample counter 101 receives the note clock pulse NC
L is counted and a sample number SN indicating the number of the sample point to be reproduced as a relative number within one block is output. A detailed example of this is shown in FIG. 17, in which the sample counter 101 includes an adder 107 and an 8-stage/4-bit system that dynamically stores the addition result of the adder 107 for each channel in synchronization with the time division timing. A shift register 108 and a gate 109 for gating the output of the shift register 108 are provided. The output of gate 109 is input to adder 107 and summed with the note clock pulse NCL applied to the other input of adder 107. gate 10
The output of 9 is output as sample number SN. This 10-bit sample number SN specifies relative sample numbers 0 to 1023 within one block. Also,
The gate 109 is closed by the second key-on pulse KONP2, but is otherwise open. In addition, the display "8D" in the block of the shift register 108
indicates that there are eight stages, which are shift-controlled in synchronization with the channel time division timing by the two-phase system clock pulses mentioned above. The same applies to the other shift registers marked "8D".

With this configuration, the sample counter 101
is once cleared by the second key-on pulse KONP2 at the beginning of the key press, and thereafter the note clock pulse NCL
, and generates a sample number SN indicating the number of the sample point to be reproduced as a relative number 0 to 1023 within one block. The generated sample number SN is input to the hidden bit control signal generation circuit 110. The hidden bit control signal generation circuit 110 generates each hidden bit data H.
It recognizes the sample numbers to which B0 to HB3, HS0 to HS3, and HC0 to HC7 are assigned. First, a NOR gate 111 is provided to recognize the first four sample numbers within one frame to which hidden bit data HB0 to HB3 corresponding to the bit number data of each frame consisting of 4 bits are assigned. . Of the sample number SN consisting of 10 bits, the lowest 4 bits S
0, S1, S2, S3 identify 16 sample points within one frame, of which the upper 2 bits S2, S
3 is input to the NOR gate 111. At the first four sample points within one frame, the sample number SN
The above two bits S2 and S3 are both "0" and the output of the NOR gate 111 is "1", but in other cases the output of the NOR gate 111 is "0". The output of this NOR gate 111 is given to other circuits as a hidden bit control signal HBC1 of bit number data, and this signal HB
When C1 is "1", it indicates that the sample point is assigned the hidden bits HB0 to HB3 corresponding to the bit number data. Lower 4 bits of sample number SN S0,
S1, S2, S3 are input to AND gate 112, and at the last sample point of the frame these bits S0-S
3 are all "1", and the output of the AND gate 112 becomes "1", which is given to other circuits as the frame change signal HBC2.

[0075] For recognition of four sample numbers from 5th to 8th in the first frame of each block to which hidden bit data HS0 to HS3 corresponding to shift data of each block consisting of 4 bits is assigned. A NOR gate 113 and an AND gate 114 are provided. The most significant 4 of the 10-bit sample number SN
Bits S6, S7, S8, and S9 are input to NOR gate 113. During the first four frames (frames 0 to 3) in one block, the most significant 4 bits S6, S7, S
8 and S9 are all "0", and the output of the NOR gate 113 becomes "1". The output signal of this NOR gate 113, the third bit S2 of the sample number SN, and the bit S3 from the fourth bit to the sixth bit of the sample number SN.
, S4, and S5 are input to the AND gate 114. The output of Noah gate 113 is “1”
Then, bit S2 is “1” and bits S3, S4, S5
is all “0” at the four sample numbers 4 and 5 from the 5th to the 8th of the first frame 0 of the block.
, 6, 7. At this time, the output of the AND gate 114 becomes "1", which is given to other circuits as the shift data hidden bit control signal HSC.

Each of the first four frames (frames 0-3
), a Noah gate 113 and an AND gate 115 are used to recognize eight sample numbers from the 9th to the 16th in
-118 are provided. As described above, the output of the NOR gate 113 is "1" during the first four frames (frames 0 to 3) within one block. The output signal of the NOR gate 113, the fourth bit S3 of the sample number SN, and the inverted signals of the fifth and sixth bits S4 and S5 of the sample number SN are input to the AND gate 115. The output of NOR gate 113 is “1”, bit S3 is “1”, and bits S4 and S
5 becomes “0” when 9 of the first frame of the block
This is the case for eight sample numbers 8 to 15 from the 16th to the 16th. At that time, the output of the AND gate 115 is “1”
", and this is given to other circuits as the hidden bit control signal HCb1 for the compression coefficient b1. As shown in FIG. 12, the hidden bit data HC0 to HC7 of the compression coefficient b1 are assigned to these sample numbers 8 to 15. ing.

The output signal of the NOR gate 113, the 4th bit S3 and the 5th bit S4 of the sample number SN,
A signal obtained by inverting the bit S5 is input to the AND gate 116. The output of Noah gate 113 is “1”
Then, bits S3 and S4 are “1” and bit S5 is “0”.
” occurs at eight sample numbers 24 to 31 from the 9th to the 16th frame of the second frame of the block.At that time, the output of the AND gate 116 becomes “1”, and this is the value for the compression coefficient b0. Hidden bit control signal HC
It is given to other circuits as b0. As shown in FIG. 12, hidden bit data HC0 to HC7 of compression coefficient b0 are assigned to these sample numbers 24 to 31. Similarly, the output signal of the NOR gate 113, the fourth bit S3 and the sixth bit S5 of the sample number SN, and the signal obtained by inverting the fifth bit S4 are output to the AND gate 113.
7 is input. At eight sample numbers 40 to 47 from the 9th to the 16th frame of the third frame of the block, the output of the AND gate 117 becomes "1", and this is sent to other circuits as the hidden bit control signal HCa1 for the compression coefficient a1. given to. Further, the output signal of the NOR gate 113 and bits S3, S4, and S5 from the fourth bit to the sixth bit of the sample number SN are input to the AND gate 118. At eight sample numbers 56 to 63 from the 9th to the 16th of the 4th frame of the block, the output of the AND gate 118 becomes "1", and this is sent to other circuits as the hidden bit control signal HCa0 for the compression coefficient a0. Given.

Each hidden bit control signal HBC1 to HCa0
are OR-combined by an OR gate 137, and a hidden bit control signal HC indicating the presence of a hidden bit is output. All bits of sample number SN are given to AND gate 119,
At the last sample number 1023 of the block, the output of the AND gate 119 becomes "1", which is given to other circuits as the block end control signal BFC.

Returning to FIG. 16, the data length counter 102 inputs the data length instruction data LENG output from the data register 106, and uses this as the note clock pulse N.
This is a modulo 16 counter that accumulates at each CL timing. This modulo number of 16 corresponds to the number of bits of one address in the waveform memory 15, which is 16. Therefore,
The count value of the data length counter 102 indicates the boundary of variable length data at the memory address. A detailed example of this is shown in FIG.
The adder 120 and the addition result of the adder 120 are "1"
A selector 121 input to the input, an 8-stage/4-bit shift register 122 that inputs the output of the selector 121 and dynamically stores it in synchronization with the time division timing for each channel, and gates the output of the shift register 122. A gate 123 is provided. The output of gate 123 is input to adder 120 and added to data length instruction data LENG added to the other input of adder 120. Further, the output of the gate 123 is input to the “0” input of the selector 121. The gate 123 is closed by the second key-on pulse KONP2, but is otherwise open. The selector 121 selects the addition result of the adder 120 to be added to the "1" input when the note clock pulse NCL occurs (when it is "1"), and selects the addition result of the adder 120 to be added to the "1" input when the note clock pulse NCL does not occur (when it is "0"). Select and hold the count value to be added to.

With this configuration, the data length counter 102
is once cleared by the second key-on pulse KONP2 at the beginning of the key press, and thereafter the note clock pulse NCL
The data length instruction data LENG is accumulated every time the error occurs. Note that the data length instruction data LENG indicates the net data length of the waveform data portion, that is, the number of bits, and does not indicate the data length including hidden bits HB0 to HC7. Therefore, in order to add the actual data length at sample points including hidden bits HB0 to HC7, the hidden bit control signals HBC1, HSC, HCb1, HCb0
, HCa1, HCa0, is inputted to the carry-in input Cin of the adder 120, and 1 is added as a hidden bit. The count output of the data length counter 102 is output from the gate 123, and this is the pull out pointer (extract pointer).
It is given to other circuits as POP. This pull out pointer POP indicates the bit position in the storage address where the least significant bit of the data of one sample point to be retrieved is located.

For example, in the case of the example shown in FIG. 13, the pull-out pointer POP of the first sample point 0 points to "0", that is, the least significant bit 0 of the storage address, when cleared by the key-on pulse KONP2. Next, when the timing of the note clock pulse NCL arrives, 11 of the data length instruction data LENG and the hidden bit control signal HBC1
1 is added by the adder 120, resulting in POP=12, which indicates bit 12 of the storage address. Next, when the timing of the note clock pulse NCL arrives, 12
Since +12=24, “1” is generated in the carry-out output Cout in the adder 120, and the addition result is 8.
Indicates bit 8 of the storage address. Thus, the pull out pointer POP points to the bit position in the storage address where the least significant bit of the data of one sample point to be retrieved is located.

Carry-out output Cou of adder 120
The signal at t is the address increment pulse ADINC.
The data length counter 102 outputs the data as follows. The address counter 103 counts addresses for reading out the waveform memory 15 based on the address increment pulse ADINC and the note clock pulse NCL, and sends an address signal C which is a relative value of the read address.
Output A. The address is counted up by one using the address increment pulse ADINC generated at the timing of the note clock pulse NCL as an effective address increment pulse.

A detailed example of this is shown in FIG. 18, where the address counter 103 is an 8-stage/1-bit shift register 124 that delays the note clock pulse NCL.
AND gate 1 inputs the output of this shift register 124 and address increment pulse ADINC.
25, an adder 126 which inputs the output of the AND gate 125 to one side, a gate 127 which gates the addition result of the adder 126, and a gate 127 which inputs the output of this gate 127 and synchronizes with the time division timing for each channel. and an 8-stage/22-bit shift register 128 for dynamic storage. The output of the shift register 128 is sent to the adder 12
6 and is added to the output of AND gate 125. In addition, the key-on pulses KONP1 and KONP2 are input to the NOR gate 1294, and the output of the key-on pulses KONP1 and KONP2
7 is controlled.

In the data length counter 102, the timing at which the carry-out output is generated from the adder 120 is as follows.
Due to the delay caused by the shift register 122, the timing of the note clock pulse NCL is delayed by 8 system clocks, so in order to match this, the note clock pulse NCL is delayed by 8 system clocks in the shift register 124. Therefore, at the timing of the note clock pulse NCL, the data length instruction data LEN
As a result of adding G, address increment pulse AD
When INC occurs, the output of AND gate 125 becomes “1”
Therefore, the address counter 103 counts up one address. In the address counter 103, the gate 12
The output of 7 is output as the address signal CA.

For example, in the case of the example shown in FIG. 13, the address signal CA is initially cleared by key-on pulses KONP1 and KONP2 to indicate "0", that is, the storage address A0, and the 16-bit data stored at this address A0 is Read out. Next note clock pulse NCL
When the timing of , the addition output of the adder 120 of the data length counter 102 becomes 12 as described above, which is selected by the selector 121 and sent to the shift register 122.
8 system clocks later, POP=12 is output. At this time, the adder 120 further adds 12 and the carry-out output Cout becomes "1", and the address increment pulse ADINC is "1" and the note clock pulse NCL delayed by 8 system clocks.
is added to AND gate 125, and address counter 1
03 is counted up. Therefore, address signal C
A indicates "1", that is, the storage address A1, and the 16-bit data stored at this address A1 is read out. On the other hand, the selector 121 does not select the output of the adder 120, and the output POP of the data length counter 102 maintains 12.

As can be understood here, sample number 1 stored across two addresses A0 and A1
Regarding data, pull out pointer POP points to bit 12 in address A0 where the least significant bit of the data is located, and output address signal CA of address counter 103 points to the next address A1. In other words, address signal CA precedes pull-out pointer POP by one address. this is,
As will be explained later, the data position reproducing circuit 104 uses the data at the previous address read from the waveform memory 15 in order to reproduce data for one sample point stored across two addresses. This is because the pull-out pointer POP is designed to indicate the least significant bit of the data to be taken out with respect to the temporarily held read data of the previous address.

The data position reproducing circuit 104 inputs the 16-bit data RD read from the waveform memory 15, and (a) collects one set of data for one sample point stored across two addresses; (b) By performing processing to align the bit positions of data according to the least significant bit of variable bit length data, variable bit length data can be reproduced from among 16-bit data. This function performs preprocessing to extract only the necessary part of the data for one sample point. A detailed example of this is shown in FIG. 19, where the data position recovery circuit 104 includes a 32-bit parallel input/16-bit parallel output shifter 130. The 16-bit data RD read from the waveform memory 15 is directly input to the upper 16-bit input of the shifter 130 . This read data RD is added to the "0" input of the selector 131, and the output of the selector 131 is input to the 8-stage/16-bit shift register 132.
The output of 32 is added to the “1” input of selector 131 and is also applied to the lower 16 bit input of shifter 130. Note clock pulse NCL and key-on pulse KONP1
is added to the NOR gate 133, and when the output signal of the NOR gate 133 is "0", the "0" input of the selector 131 is selected, and when it is "1", the "1" input is selected.

The control input of the shifter 130 includes a pull out pointer PO from the data length counter 102 in FIG.
P is input. This pull out pointer POP is connected to 16 of the 32-bit parallel input data of shifter 130.
Indicates the bit corresponding to the least significant bit of the data to be extracted as bit-parallel output data. For example, POP
If = 0, the least significant bit of the 32-bit parallel input data is the least significant bit of the 16-bit parallel output data,
The upper 16-bit data is extracted from there. Also, P.O.
If P=1, the bottom 2 of 32-bit parallel input data
The upper 16-bit data is extracted from the least significant bit of the 16-bit parallel output data with the first bit as the least significant bit. Also,
If POP=12, the 13th bit from the bottom of the 32-bit parallel input data is taken as the least significant bit of the 16-bit parallel output data, and the upper 16-bit data is extracted from there.

Of the 32-bit parallel input to the shifter 130, the upper 16 bits are the data RD currently being read from the waveform memory 15, and the lower 16 bits input from the shift register 132 are the data RD read from the previous address. It is data. Therefore, if the read data of two addresses are arranged in the shifter 130 and the data of one sample point is stored across two addresses, the sum of the two addresses arranged in the shifter 130 is It is now possible to extract the necessary data of one sample point from the 32-bit parallel data. Also, since the pull out pointer POP points to the least significant bit of variable bit length data,
A process of aligning the data bit position to match the least significant bit of variable bit length data by indicating the input bit position of the data to be extracted as the least significant bit of the 16-bit parallel output data using this pull out pointer POP. This allows 16
Preprocessing can be performed to extract only a necessary portion of data for one sample point of variable bit length from data having a bit structure.

An example is shown in FIG. 13. When the first key-on pulse KONP1 occurs, the address counter 103 in FIG. 18 is cleared, the address signal CA becomes "0", and data is read from address A0. At this time, due to the output "0" of the NOR gate 133, the selector 131 selects the read data RD from the address A0.
is selected and loaded into the shift register 132. In the next cycle, the selector 131 outputs the output of the NOR gate 133 “
1" selects the output of the shift register 132 and stores and holds the read data RD from address A0. At this time, the pull-out pointer POP is "0", and the lower 16 bits of the input to the shifter 130, that is, the shift The read data from address A0 held in register 132 is selectively output as is. This includes the entire data of sample point 0 in the lower 12 bits. In other words, the least significant bit of the data at sample point 0 to be extracted first is extracted in its entirety in accordance with the least significant bit of the 16-bit output. This is schematically shown in Figure 2.
It is like (a) of 0.

Next, when the note clock pulse NCL occurs, the pull out pointer POP becomes "12" eight system clocks later, and the address signal CA switches to the address A1 (see FIG. 18). . However, since the note clock pulse NCL input to the NOR gate 133 is not delayed, the output of the NOR gate 133 becomes "0" due to this note clock pulse NCL.
”, the address signal CA has not changed yet and the read data RD from the address A0 is sent to the selector 13.
1 and stored in the shift register 132. Therefore, eight system clocks later, the read address of the waveform memory 15 changes to A1, and the upper one of the shifter 130
When read data RD of A1 is input to the 6th bit,
The lower 16 bits of shifter 130 contain the previous address A.
Read data of 0 is provided from shift register 132. In this way, the read data of two consecutive addresses are arranged at the input of the shifter 130. At this time,
Pull out pointer POP is "12" and indicates the position of the least significant bit of the data at sample point 1 at the preceding address A0. As a result, the least significant bit of the data at sample point 1 is changed to the least significant bit, and the 16 bits of data above it are taken out from the shifter 130. This includes the entire data of sample point 1 in the lower 12 bits, and in this way, the data of sample point 1, which had been stored separately in two addresses, is now aligned, and the lowest The bits are output aligned with the least significant bit of the 16-bit output. This is schematically shown in FIG. 20(b). In this way, the shifter 130 outputs 16-bit data D1 in which the bit positions of the target variable data length data to be extracted are aligned in order from the least significant bit. This 16-bit structured data D1 may contain unnecessary data on the upper bit side, so the desired one
It does not mean that only sample data with variable data length is extracted. Therefore further processing is required.

Returning to FIG. 16, the data position reproducing circuit 10
The data D1 outputted from the shifter 130 of No. 4 is sent to the data matching circuit 1 via the hidden bit separation circuit 134.
35. Hidden bit separation circuit 134 separates data D1 if it includes hidden bits HB0 to HC7, takes out only the net waveform data, and inputs it to data matching circuit 135 as data D2. The data matching circuit 135 is for extracting only one target sample of variable bit length waveform sample data from the data D2. The 1-bit hidden bit possibility signal HBP (this is a signal that may be any one of hidden bits HB0 to HC7) separated by the hidden bit separation circuit 134 is input to the hidden bit recovery circuit 105. be done. The hidden bit recovery circuit 105 receives a hidden bit possibility signal HB given from the hidden bit separation circuit 134.
Based on P, a set of each hidden bit data HB0 to HB
3. Regenerate HS0 to HS3 and HC0 to HC7. Regenerated hidden bit data HB0 to HB3, HS0 to HS
3. HC0 to HC7, that is, bit number data for each frame (data length instruction data LENG), shift data (weighting coefficient) for the next block, and compression coefficient data a0, a1, b0, b1 are given to the data register 106. It will be done.

A detailed example of the hidden bit separation circuit 134 and the data matching circuit 135 is shown in FIG. In this embodiment, the bit length or size of the net waveform sample data is variable in the range of 2 bits to 15 bits. Therefore, the maximum bit length of valid data is
It is 16 bits if it includes hidden bits, and 15 bits if it does not. Therefore, the maximum data length of valid data of the data D1, which may include hidden bits, is 16 bits, and therefore, this data D1 is extracted in a 16-bit configuration. Further, the maximum bit length of valid data of data D2 after hidden bit separation is 15 bits. Further, it is assumed that the most significant bit of variable length waveform data for one sample is a sign bit.

In FIG. 21, hidden bit separation circuit 13
4 consists of a selector 138 which inputs the lower 15 bits of the data D1 to the "0" input, and inputs the upper 15 bits of the data D1 to the "1" input. The selector 138 inputs the aforementioned hidden bit control signal HC (see FIG. 17) to the selection control input, selects the "1" input when HC is "1", and selects the "0" input when HC is "0". do. Therefore, when extracting sample point data including hidden bits HB0 to HC7, HC is set to "1" to select the upper 15 bits of data D1 and exclude the least significant 1 bit of hidden bits HB0 to HC7. This 15-bit data is sufficient to ensure valid bits of the net waveform data as described above. On the other hand, hidden bits HB0~
When extracting sample point data that does not include HC7, the lower 15 bits of data D1 are selected by HC being "0". This 15-bit data is also sufficient data to ensure valid bits of the net waveform data as described above. The net waveform data D2 having a 15-bit configuration from which the hidden bits have been separated is sent to the data matching circuit 1.
35. As mentioned above, this data D2 is
It is possible that not only the waveform data of one target sample point but also part of the waveform data of the next sample point is included.

In the data matching circuit 135, the data D2
When extracting only the desired waveform data of one sample point from , extracting the data size as it is variable length will cause problems for later data processing, so it is necessary to match the data size to a fixed length of 15 bits. I try to do that. To do this, first extract only the waveform data of the desired one sample point from the data D2, and then
If the sample point waveform data alone does not satisfy the fixed length data size of 15 bits, by extending the sign bit to all remaining upper bits,
Even though only the waveform data of one sample point of variable length is taken out, the overall data size is matched to a fixed length of 15 bits. In data matching circuit 135 in FIG. 21, data D2 is input to sign bit extraction circuit 139, and sign bit SB is extracted. The data length instruction data LENG is decoded by the decoder 140, and one output line corresponding to the most significant bit of the variable length data among the 15 decode output lines becomes a signal "1". The output of this decoder 140 indicates the position of the code bit SB to be extracted in the code bit extraction circuit 139. For example, when the bit length is 10 bits, the 10th bit of the data D2 is the most significant bit of the variable length data, that is, the sign bit SB, and this is extracted in response to the signal “1” from the 10th output line of the decoder 140. It will be done.

In the data matching circuit 135 of FIG. 21, the bit-by-bit independent selector 141 selects only the waveform data for one target sample point, excludes some data of other sample points, and sign bit SB instead
It is intended to expand. The lower 14 bits of data D2 (the most significant bit can only be the sign bit SB,
(This can be set by the output of the sign bit extraction circuit 139, so it can be excluded here.) Since the data of the least significant bit 0 is always the waveform data for one target sample point, it is not input to the selector 141 and is output. register 1
42 may be entered directly. Among the lower 14 bits of data D2, data of bits 1 to 13 other than the least significant bit 0 are input to bit-specific A inputs 1A to 13A of the selector 141, respectively. The signal of the code bit SB extracted from the code bit extracting circuit 139 is commonly inputted to the bit-specific B inputs 1B to 13B of the selector 141, respectively. Bit-by-bit selection control of the selector 141 is performed by 13 signal lines provided from a select signal generation circuit 143, respectively. The select signal generation circuit 143 provides a selection control signal "1" corresponding to all the upper bits from the bit position of the sign bit SB in accordance with the output signal of the decoder 140.

For example, if the sign bit SB is the second lower bit 1 of the data D2, all 13 signal lines of the select signal generation circuit 143 are set to "1", and the independent bit selector 141 sets all 13 signal lines to "1". The bit selects the sign bit SB of B inputs 1B to 13B. Further, assuming that the sign bit SB is the third lower bit 2 of the data D2, the lower one signal line of the select signal generation circuit 143 is set to "0", the upper 12 signal lines are set to "1", and the bit In the separate independent selector 141, bit 1 selects the waveform data of A input 1A, and bits 2 to 13 select B input 2B to 1.
3B sign bit SB is selected. Also, the sign bit S
Assuming that B is the fourth lower bit 3 of data D2, the lower two signal lines of the select signal generation circuit 143 are
0", the upper 11 signal lines are set to "1", and in the bit independent selector 141, bits 1 and 2 select A inputs 1A and 2A.
Select the waveform data of B input 3B~ with bits 3~13.
13B sign bit SB is selected. Thereafter, as the position of the sign bit SB is shifted, the selection mode for each bit is similarly shifted, and in the end, only the waveform data for one target sample point is selectively extracted, and the data for other sample points is excluded. However, extending the sign bit SB is instead achieved.

[0098] Least significant bit of data D2 and selector 14
Data consisting of a total of 15 bits consisting of the 13 bits output from 1 and the sign bit SB taken out from the sign bit extraction circuit 139 is input to the output register 142, and the data is input to the output register 142 at the rising timing of the system clock pulse φ2.
be taken in. The rising timing of this system clock pulse φ2 is in the middle of one time slot of the time-division channel timing, and data is taken in when the data at the time-division channel timing has sufficiently risen. The output of this output register 142 is output as one sample of waveform data CWD for which extraction has been completed. 22 and 23 show detailed examples of the hidden bit reproducing circuit 105 and the data register 106. Hidden bit reproduction circuit 105 and data register 106 are provided corresponding to the types of hidden bits. In FIG. 22, a hidden bit recovery circuit 105A and a data register 106A for "bit number data" are shown.
and a hidden bit regeneration circuit 10 for "shift data"
5B and a detailed example of the data register 106B. Figure 2
3 shows a detailed example of hidden bit recovery circuits 105C to 105F and data registers 106C to 106F for each compression coefficient b1, b0, a1, and a0.

According to FIG. 22, the hidden bit regeneration circuit 105A and data register 10 for "bit number data"
6A, hidden bit regeneration circuit 105A
is an AND gate 145 inputting the note clock pulse NCL delayed by an 8-stage/1-bit shift register 144 and the hidden bit control signal HBC1;
Second key-on pulse KNOP2 and AND gate 145
The selector 147 is controlled by the output of the OR gate 146, and the 8-stage/4-bit shift register 148 receives the output of the selector 147. The output of the shift register 148 is directly applied to the "0" input of the selector 147. The most significant bit of the four bits input as "1" to the selector 147 is given the signal of the least significant bit of the data D1 output from the shifter 130, that is, the hidden bit possibility signal HBP. "1" of selector 147
Of the four input bits, the remaining three lower bits are input with the output of the shift register 148 shifted one bit lower.

With this configuration, first, when the second key-on pulse KONP2 becomes "1", the OR gate 1
The output "1" of the selector 146 selects the "1" input of the selector 147. At this time, data with sample number 0 read from address A0 is given as data D1 based on the address clear by the first key-on pulse KONP1 that occurred one cycle before, and as hidden bit possibility signal HBP. Since the output of the hidden register 148 stored with sample number 0 may initially have any value, it will be described as x (x may be either 0 or 1). As a result, from the upper bit, HB0,
4-bit data with the content x, x, x is sent to the selector 14
7 into the shift register 148 via the "1" input. In the next cycle, the output of the OR gate 146 is “0”.
”, and the data HB0, x, x, x taken into the shift register 148 is held in the shift register 148 via the “0” input of the selector 147.

Next, when the note clock pulse NCL is generated and the data of sample number 1 is given as data D1, "1" of HBC1 and the delayed output "1" of the note clock pulse NCL (shift register 144
The delay due to is to synchronize with HBC1: Figure 17
), the output of the AND gate 145 becomes "1", the output of the OR gate 146 becomes "1", and the selector 1
47 "1" input is selected. At this time, since the hidden bit HB1 stored along with sample number 1 is given as the hidden bit possibility signal HBP, H
4-bit data with contents B1, HB0, x, x is transferred to the shift register 14 via the “1” input of the selector 147.
Incorporated into 8. In the next cycle, the output of the OR gate 146 becomes "0", and the data HB1, HB0, x, x taken into the shift register 148 are held in the shift register 148 via the "0" input of the selector 147. Next, note clock pulse NCL occurs, and data D1
When the data of sample number 2 is given, the hidden bit HB2 stored along with sample number 2 is given as the hidden bit possibility signal HBP, and according to the above, HB2, HB1, HB0, x are transferred to the shift register 148. captured and retained.

Furthermore, when the note clock pulse NCL is generated and the data of sample number 3 is given as data D1, the hidden bit HB3 stored along with sample number 3 is given as hidden bit possibility signal HBP. According to the above, HB3, HB2, HB1, HB0
is taken into the shift register 148 and held. Thereafter, within that frame, the note clock pulse NCL
Even if the above-mentioned H
B3, HB2, HB1, HB0 are shift registers 148
is held in In this way, the 4-bit hidden bit HB3
, HB2, HB1, and HB0 are reproduced and held in the shift register 148. This is stored in the data register 106 as hidden information HD indicating the data bit length of the next frame.
given to A.

[0103] The data register 106A has 8 stages/
It includes a 4-bit shift register 149 and a selector 150. Initial data length data ILENG is input to the “10” input of the selector 150, and “01”
The hidden information HD, ie, data indicating the data bit length of the next frame, is input to the input, and the output of the shift register 149 is input to "00". selector 150
The first key-on pulse KONP1 is input to the upper bit of the 2-bit control input, and the output of the AND gate 151 is input to the lower bit. The frame change signal HBC2 and note clock pulse NCL from the AND gate 112 in FIG. 17 are applied to the AND gate 151. With this configuration, first the key-on pulse KONP1 becomes “1”.
At this time, the selector 150 selects the initial data length data ILENG of "10" input, and selects the initial data length data ILENG of the shift register 14.
Import into 9. In the next cycle, the selector 150 is “00
” input and hold the captured data ILENG. The output of the shift register 149 is given to each circuit as the data length instruction data LENG as described above. Therefore, in the first frame 0, the initial data length data IL given from the parameter data generation circuit 94
ENG is used as data length instruction data LENG. In this frame 0, as mentioned above, the hidden information HD indicating the data bit length of the next frame is sent to the selector 1.
given to 50.

Next, when the frame is switched, the output of the AND gate 151 becomes "1", the selector 150 selects the information HD of the "01" input, and the shift register 14
Import into 9. In the next cycle, the selector 150 is “00
” input and hold the imported data HD. In this way, in the second and subsequent frames, the hidden information HD indicating the data bit length stored as hidden information together with the waveform data of the previous frame is transferred to the data length instruction data LE.
Use as NG. First key-on pulse KONP1
The second key-on pulse KONP2 may be generated by delaying 8 system clocks by an 8-stage/1-bit shift register 152. The hidden bit reproducing circuit 105B and data register 106B for shift data have almost the same configuration as the hidden bit reproducing circuit 105A and data register 106A. The difference is that an AND gate 14 corresponding to the above AND gate 145
5B, the hidden bit control signal HSC for shift data output from the AND gate 114 in FIG.
AND gate 151 corresponding to the above AND gate 151
B is the point at which the block end control signal BFC output from the AND gate 119 in FIG. 17 is input. As a result, the shift register 148B stores hidden bit data HS3, H corresponding to the shift data regarding the next block.
S2, HS1, and HS0 are reproduced and stored, and are taken into the shift register 149B at the end of the block. Therefore, shift register 149B outputs shift data SFD regarding the block currently being processed.

In FIG. 23, the hidden bit reproducing circuit 105C and data register 106C for compression coefficient b1 are the same as the hidden bit reproducing circuit 105B and data register 1.
It has almost the same configuration as 06B. The difference is that the number of bits of the shift registers 148C and 149C is 8 bits, and the AND gate 145C corresponding to the AND gate 145B has hidden bit control for the compression coefficient b1 output from the AND gate 115 in FIG. The point where the signal HCb1 is input and the initial data given to the "10" input of the selector 150C are the initial compression coefficients I corresponding to b1.
The point is that CO. The AND gate 151C has Figure 1
The block end control signal BFC output from the AND gate 119 of No. 7 is input. As a result, the hidden bit data HC0 to HC7 corresponding to the compression coefficient b1 regarding the next block are reproduced and stored in the shift register 148C.
This is the end of the block and is taken into shift register 149C. Therefore, the shift register 149C outputs the compression coefficient b1 regarding the block currently being processed. Hidden bit reproduction circuits 105D, 105E, 105F and data registers 106D, 106E, 106F for other compression coefficients b0, a1, a0 have almost the same configuration as the hidden bit reproduction circuit 105C and data register 106C. The difference is that each AND gate 145D, 145E, 145F corresponds to the above AND gate 145C.
At this point, the hidden bit control signals HCb0, HCa1, and HCa0 for the compression coefficients b0, a1, and a0 output from the AND gates 116, 117, and 118 in FIG. 17 are respectively input. As a result, each register 106D, 1
Compression coefficients b0, a1, and a0 regarding the block currently being processed are output from 06E and 106F, respectively.

--Example of compressed data demodulation circuit--If the waveform data CWD extracted and reproduced by the data extraction and reproduction section 96 is compressed by the linear predictive coding (LPC) method, the compression shown in FIG. The data demodulation circuit 97 uses an LPC demodulation circuit. In that case,
The compressed data demodulation circuit 97 can be configured by an LPC demodulation circuit as shown in FIG. In the figure, 15
3,154 is a limiter, 155 to 158 are adders, 15
9 to 162 are multipliers, and 163 to 166 are 8-stage shift registers. It has a configuration opposite to that of the compression filter circuit shown in FIG. As the first stage compression coefficients a0, a1
use.

--Another example of compression and reduction processing (second embodiment)-- In the above embodiment, data reduction processing using weighting coefficients (shift data) is performed before data compression processing using a compression filter. However, as described below, it may be performed at a later stage of the data compression process. FIG. 25 shows an example of the configuration of a circuit for compression and reduction operations when data reduction processing is performed using weighting coefficients (shift data) at a subsequent stage of data compression processing. The compression filter circuit is formed by cascading two stages of secondary filters as described above, and the first stage filter 48A includes a subtracter 170, adders 171 and 172, multipliers 173 and 174, and a delay section 1.
It consists of 75,176. The second stage filter 48B includes a subtracter 177, adders 178 and 179, and multipliers 180 and 1.
81 and delay sections 182 and 183. The waveform data to be compressed is input to the subtracter 170 of the first-stage filter 48A, and the subtracter 170 subtracts the quadratic convolution sum by the coefficients a0 and a1. Subtractor 1 of second stage filter 48B
The output of 77 is the output signal of the compression filter. This compression filter output signal is input to the shift circuit 47, and is weighted (shifted) in the direction of reduction using a weighting coefficient (shift data). The output of the shift circuit 47 is temporarily stored in the block buffer 55 as compressed and reduced waveform sample data, and then written into the waveform memory 15.

The shift circuit 184 shifts data by the same amount in the opposite direction to the shift direction by the shift circuit 47, and simulates weight restoration during reproduction. The output of this shift circuit 184 is then passed through adders 178, 171 to delay units 175, 176,
182 and 183, whereby the compression coefficient multiplication operation is performed on the signal that simulates the weight restoration during reproduction. This makes it possible to perform highly accurate compression filter calculations that absorb data truncation errors due to data shift down. In the case of this second embodiment, compression filter coefficients a0, a1, b0, b
1 may be calculated using the same method as in the first embodiment described above. Since the position of the shift circuit 47 is different, the functional block diagram of FIG. 5 cannot be applied to this second embodiment in its entirety. However, the shift circuit 47 and compression filter section 48 in FIG.
It is only necessary to make appropriate changes so that the following configuration can be implemented. Also,
In the case of the second embodiment, the steps of demodulating compressed data and restoring weights during playback are opposite to those of the first embodiment, so as shown in FIG. The configuration of the sound source section 23 may be changed so that it is placed in the front stage of the sound source section 23.

--Example of modification-- Not limited to either the first stage or the second stage of data compression processing,
It is also possible to perform data reduction processing using weighting coefficients (shift data) in both cases. Also. Data reduction calculation processing using weighting coefficients (shift data) may be inserted in the middle of data compression processing. The weight calculation is not limited to data shift, but may also employ multiplication, division, or the like. The division of the waveform section is not limited to the one consisting of blocks and frames as in the above embodiment, and may be divided in any manner. The data bit length does not need to be variable and may be fixed. Furthermore, it is not necessary to cram the waveform data into the memory and write it. Furthermore, control data for reproduction (compression coefficients and weighting coefficients) is not limited to the form of hidden bits, and may be provided separately as appropriate. The data compression method is not limited to the LPC method, but any other method such as DPCM, ADPCM, delta modulation, etc. may be adopted.

[0110] In the above embodiment, the present invention is applied to musical sound waveform data, but the present invention is not limited to this, but is applicable to envelope waveform data for setting the volume level, envelope waveform data for various controls, or temporal changes in filter coefficients, etc. The present invention can be applied to various types of waveform data in electronic musical instruments, such as various types of control data. Furthermore, the present invention is applicable not only to waveform data in electronic musical instruments, but also to compression of waveform data in other audio signals or sound signal processing devices. In the above embodiment, the data retrieval/reproduction unit requires multiple processing steps such as sample counting, data length counting, address counting, data position regeneration, and hidden bit regeneration in order to retrieve and reproduce one sample of data. ,
This is done at the timing of one sample. Therefore, it may be necessary to take a longer time for one sample. To solve this problem, it is best to use a pipeline processing method to perform processing across multiple sampling timings within the same channel timing, thereby shortening the time for one sample and increasing the data readout speed. Can be done. Note that the present invention is not limited to a completed single electronic musical instrument, but may be applied to a component of a modularized electronic musical instrument. Furthermore, the present invention can be applied to a device that does not have a keyboard or switch means for selecting a tone, but generates musical tones based on the input of chord information. Furthermore, there are devices that generate musical tone signals,
It can also be applied to devices that generate data related to the formation or control of musical tone signals without having a speaker or the like that acoustically produces musical tones, and in this invention, electronic musical instruments are used in an extremely broad sense. It is a word to do. Further, the present invention can also be applied to a general sound signal processing device or an audio signal processing device.

[0111]

As described above, according to the present invention, while performing predetermined data compression processing on waveform data, the values of the waveform data can be changed at any stage before or after the data compression processing. Since further reduction processing is performed according to an arbitrary weighting coefficient, the value of the waveform data compressed by data compression processing can be further reduced, and further data compression can be promoted. Moreover, control such as changing the reduction rate or not reducing the image at all by changing the weighting coefficient can be easily and freely performed. Therefore, if you want to further compress data in some sections of a waveform, or compress data to different degrees depending on sections of the waveform, you can change the weighting coefficient without changing the predetermined data compression processing method itself. This can be done extremely easily by simply making a change. You can also reduce the value of waveform data according to an arbitrary weighting factor,
Since this is an extremely simple process (this process can be performed by appropriate coefficient operations such as data shift, division, or multiplication), the configuration is also simple.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing the overall flow of waveform data compression/reproduction processing in an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of the hardware configuration of an electronic musical instrument that can be used to perform waveform data compression and playback processing according to the present invention.

FIG. 3 is a flowchart outlining the overall process from compression of waveform data to writing to memory, which is executed under control by a microcomputer in the same embodiment.

FIG. 4 is a diagram illustrating a format of a storage area of compressed waveform data in the waveform memory of FIG. 2;

FIG. 5 is a functional block diagram showing an example of waveform data compression and reduction processing performed under the control of the microcomputer shown in FIG. 2;

FIG. 6 is a diagram illustrating a memory format of a block buffer in FIG. 5;

FIG. 7 is a diagram conceptually showing a configuration example of a shift circuit and a compression filter section in FIG. 5;

FIG. 8 is a diagram showing an example of a hardware circuit of a compression filter section consisting of one stage of secondary filters.

FIG. 9 is a flowchart illustrating an example of a compression filter coefficient generation calculation procedure according to a linear prediction method.

FIG. 10 is a functional block diagram for explaining processing operations of the variable bit length processing and writing processing section in FIG. 5;

FIG. 11 is a flowchart outlining the procedure of variable bit length processing and writing processing executed by the variable bit length processing and writing processing section.

FIG. 12 is a diagram showing an example of a data format of variable bit length processed waveform sample data and hidden bit data.

13 is a diagram showing an example of a memory format when variable bit length data having the format shown in FIG. 12 is actually packed and stored in a waveform memory; FIG.

FIG. 14 is a diagram for explaining a process of stuffing variable bit length data and writing it into memory.

FIG. 15 is a block diagram showing an embodiment of the sound source section in FIG. 2;

FIG. 16 is a block diagram showing an example of the internal configuration of the data retrieval and playback section in FIG. 15;

FIG. 17 is a block diagram showing a specific example of the sample counter and hidden bit control signal generation circuit in FIG. 16;

FIG. 18 is a block diagram showing a detailed example of the data length counter and address counter in FIG. 16;

FIG. 19 is a block diagram showing a detailed example of the data position reproducing circuit in FIG. 16;

20 is a diagram illustrating an example of the operation of the shifter in FIG. 19. FIG.

FIG. 21 is a block diagram showing a detailed example of the hidden bit separation circuit and data matching circuit in FIG. 16;

FIG. 22 is a block diagram showing a detailed example of the hidden bit reproduction circuit and data register in FIG. 16;

FIG. 23 is a block diagram showing another detailed example of the hidden bit regeneration circuit and data register in FIG. 16;

FIG. 24 is a block diagram showing an example of the compressed data demodulation circuit in FIG. 15;

FIG. 25 is a block diagram conceptually showing an embodiment in which a shift circuit for data reduction calculation is provided at a subsequent stage of the compression filter section.

FIG. 26 is a block diagram showing an embodiment of a sound source section for reproducing waveform data that has been compressed and reduced according to the example of FIG. 25;

[Explanation of symbols]

13... Analog signal external input section, 14... Sampling device, 15... Waveform memory, 21... Waveform buffer memory, 2
3... Sound source section, 44... Limit bit number register, 45... Shift data generation section, 46... Shift data register, 47...
Shift circuit (weight calculation circuit), 48... compression filter section,
49...Hamming window multiplication section, 51...Coefficient generation calculation section, 55
... block buffer, 56 ... bit number detection section, 58 ... variable bit length processing and writing processing section, 76 ... hidden bit adding section, 78 ... data synthesis section, 96 ... data extraction and reproduction section, 97 ... compressed data demodulation circuit, 98...Shift circuit for weight restoration.

Claims (4)

[Claims] Claim 1: A first device that provides waveform data to be compressed.
and a second step of performing predetermined data compression processing on the waveform data, in which the value of the waveform data is 1. A waveform data compression method, comprising a third step of further reducing the data according to an arbitrary weighting coefficient. 2. Reduction calculation means that inputs waveform data to be compressed and performs an operation to reduce the value of the waveform data according to an arbitrary weighting factor; Waveform data compression comprising compression filter means for performing data compression filter processing on waveform data, and coefficient generation means for creating filter coefficients to be used in the compression filter means by a linear prediction method and supplying the generated filter coefficients to the compression filter means. Device. 3. Compression filter means for inputting waveform data to be compressed and performing data compression filter processing on the waveform data, and reducing the value of the waveform data output from the compression filter means according to an arbitrary weighting coefficient. 1. A waveform data compression device, comprising: reduction calculation means for performing calculations; and coefficient generation means for creating filter coefficients to be used in the compression filter means by a linear prediction method and supplying the generated filter coefficients to the compression filter means. 4. Waveform storage means storing waveform data subjected to predetermined data compression processing and data value reduction processing according to a weighting coefficient, a coefficient for demodulating the compressed data, and the weighting coefficient. a coefficient providing means for providing;
compressed data demodulation means for performing compressed data demodulation processing on the waveform data read from the waveform storage means according to the coefficients for demodulation; a calculation means for performing a calculation on the waveform data read from the waveform storage means to restore the waveform data to a normal state.