JPH04360375A - Image forming device - Google Patents

Abstract

PURPOSE:To attain sure correction against a change in the environment and to attain print with high quality by deciding type and presence of correction based on the result of arithmetic operation of the weighting sum of data representing the peripheral environment state and presence1absence of edges among dots. CONSTITUTION:A weighing means 103 classifies each edge data detected by an edge detection means 102 and selected by an edge selection means 107 depending on kinds of edges at the upper/lower and to the left/right if a dot corresponding to a correction object picture data in the middle of a sample window and collects the result depending on the dot corresponding to the object picture data with respect to the dots at the upper/lower and to the left/right. A logic arithmetic operation means 104 uses a weighing means 103 to multiply a prescribed numeral with each edge data and applies logic arithmetic operation to the result, and a value deciding the kind of dot correction corresponding to the picture data according to the environment data outputted from an environment detection means 108 is revised and the correction data is outputted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus such as a laser printer that forms image data constituting orthogonal matrices in row and column directions by horizontal and vertical scanning.

0002

2. Description of the Related Art In recent years, laser printers have come into use as output devices for computers and the like. One of the features of this laser printer is that it has a high resolution, but depending on the type of character, it is required to be able to obtain a smoother outline than the resolution. For this reason, various smoothing techniques have been devised.

[0003] The image forming apparatus will be explained below using a laser beam printer as an example. FIG. 18 is a schematic configuration diagram of a mechanical section of the image forming apparatus, FIG. 19 is a perspective view of a main part of the mechanical section of the image forming apparatus, and FIG. 20 is an explanatory diagram of the operation of the mechanical section of the image forming apparatus. 18 and 19, 1901 is a photosensitive drum driven in direction A by a motor (not shown), and this photosensitive drum 1901 consists of a metal cylinder coated with a layer of organic photoconductive material. It continues to rotate during printing, and rotates several times each time one page is printed. The photosensitive drum 1901 is physically and electrically cleaned in a cleaning section 1916 before forming an image on the area to be printed.
The drum surface 2001 is subjected to pretreatment for holding an electrostatic latent image. First, physical cleaning is performed by scraping the toner remaining on the drum from the previous cycle from the photosensitive drum 1901 using a rubber cleaning blade 1902, and the scraped toner is placed in a waste toner container (see Fig. (not shown). Electrostatic cleaning is performed by irradiating light onto the organic photoconductive material layer of the photosensitive drum 1901 using a static elimination lamp 1903.
01 by neutralizing the charge remaining from the previous cycle. Next, the cleaned drum surface 200
1, the photosensitive drum 1901 rotates and the ionization area generated by the corona generator 1904 is transferred to the photosensitive drum 1.
By passing a layer of organic photoconductive material of 901,
A negative charge is transferred from the corona generator 1904 to the drum surface 20.
01 and is uniformly charged with a negative charge of 600 volts. A laser beam 190 is applied to the drum surface 2001, which is uniformly charged with this negative charge, according to the image.
By focusing 5 and irradiating the area, the surface potential of the irradiated area is discharged and an electrostatic latent image is formed.

The above operation will be explained in more detail with reference to FIG. The semiconductor laser 2002 emits a laser beam 1905
occurs when the power is turned on, and stops when the power is turned off. A laser beam 1905 generated by a semiconductor laser 2002 is collimated by a collimator lens 2003 and focused onto a scanning mirror 2005 by a cylindrical lens 2004 . The scanning mirror 2005 is a rotating polygon mirror consisting of six surfaces, and is rotated at a constant speed by a scanner motor 2006. The laser beam 1905 is scanned in the direction of arrow B in FIG. 20 by the rotation of the scanning mirror 2005, and the focus of the scanned laser beam 1905 is
007 and mirror 2008, the drum surface 2001
can be adjusted to The laser beam 1905 scans the drum surface 2001 in the direction of arrow B, and the photosensitive drum 1901 rotates in the direction of arrow A in FIG. 20, so that the drum surface 2001 is covered with a raster image.

Here, the speed of the main motor (not shown) that rotates the photosensitive drum 1901 is the same as that of the laser beam 190.
5 scans over the drum surface 2001, 1/300
The drum surface 2001 is synchronized to move inch by inch, and the laser beam 1905 generated by the semiconductor laser 2002 is moved along the line 20 in FIG.
Modulation is applied so that dots of light strike every 1/300 inch in the direction along 01. As a result, a resolution of 300 dots x 300 dots per inch (dpi) is obtained.

At the beginning of each scan, laser beam 1905 is reflected by beam detection mirror 2012 and sent to optical fiber 2009 before reaching photosensitive drum 1901 . This instantaneous pulse of light is sent to the controller unit 2010 via an optical fiber 2009, where it is converted into an electrical signal and used to synchronize the output of scanning-related data with other data, or to control other printers. , and used for test functions, etc.

Laser beam 1 to photosensitive drum 1901
After irradiation 905, an invisible electrostatic latent image is formed on the drum surface 2001.

In other words, the portion exposed by the laser beam 1905 has a negative potential of about 100 volts due to discharge, and the drum surface 2001 that was not exposed by the laser beam 1905 has a negative potential of 600 volts. are doing.

In the developing section 1917 shown in FIG. 18, toner particles 1906 as a developer are attached to the electrostatic latent image formed on the drum surface 2001. The toner particles 1906 are a powdered substance made of a black synthetic resin combined with iron particles, and the iron particles forming the toner particles 1906 are formed by a metal rotating cylinder 1907 having a permanent magnet. It is sucked together with the resin. The synthetic resin constituting the toner particles 1906 acquires a negative surface charge by being rubbed against a rotating cylinder 1907 connected to a negative DC power source (not shown). The electrostatic charge obtained by the toner particles 1906 is
06 is an electrostatic charge that adheres to the areas of the drum surface 2001 that were exposed by the laser beam 1905, but is repelled from the areas that were not exposed.

In the transfer section 1908, the drum surface 2001
The toner image formed thereon is transferred to print paper 1909. During this transfer, the print paper 1909 advances at the same speed as the drum surface 2001, and
Contact 001. The corona assembly 1910 applies a positive charge to the print paper 1909 from the side opposite the photosensitive drum 1901, pulling the negatively charged toner particles 1906 away from the drum surface 2001 and adhering them to the print paper 1909. The static charge remover 1911 separates the drum surface 2001 which has a negative charge and the print paper 190 which has a positive charge.
9 to prevent the printing paper 1909 from wrapping around the photosensitive drum 1901. Print paper 1909 with toner particles 1906 attached is transferred to transfer unit 190
8 to the fixing unit 1912, and the photosensitive drum 1901
is rotated, and a cleaning section 1916 performs preprocessing for holding the next electrostatic latent image.

In the fixing section 1912, the toner particles 1906 are melted by heat and pressure and pressed against the print paper 1909, thereby fixing the toner image onto the print paper 1909. This fixing unit 1912 includes a non-adhesive heating roller (fusing roller) that is internally heated by a high-intensity lamp 1913.
1914, and a pressure roller 1915 made of a soft member that is provided in contact with the heating roller 1914 and shrinks slightly when pressed by the heating roller 1914, increasing the contact area with the heating roller 1914. The printing paper 1909 is configured to pass between the pressure roller 1915 and the heating roller 1914 with the surface to which the toner particles 1906 are attached facing the heating roller 1914 side. When the print paper 1909 passes between the heating roller 1914 and the pressure roller 1915, the toner particles 1906 attached to the print paper 1909 are melted and pushed into the fibers of the paper.

The controller section 2010 shown in FIG.
A central processing unit (hereinafter referred to as CPU) and a read-only memory (hereinafter referred to as ROM) in which dot patterns of desired character sets, that is, bitmap images are stored.
It is abbreviated as. ), a ROM cartridge that stores added bitmap image data, and a readable and writable memory (hereinafter abbreviated as DRAM) that stores coded image data input from an external device such as a personal computer. ), a block that controls the printer engine, etc., converts print data sent from an external device etc. into image bitmap image data, and further drives the laser drive unit 2011 with this image bitmap image data. The image dot signal is replaced with an image dot signal and outputted to the laser driving unit 2011 in serial form. The laser driving unit 2011 drives the semiconductor laser 20 according to the image dot signal sent from the controller unit 2010.
02 to modulate the laser beam and illuminate the drum surface 200.
Expose 1.

FIG. 21 is a block diagram of the controller section 2010 of the image forming apparatus shown in FIG. 19. In FIG. 21, a 16-bit central processing unit (hereinafter abbreviated as CPU) 201 controls the operation of the controller unit 2010. A ROM controller 202 stores program data to be executed by the CPU 201 stored in a program ROM 203, bitmap pattern data of character fonts stored in a font ROM 204, a font card 205, and a font card 206.
The optional character font bitmap data stored in the CPU 201 is inputted via the data bus 207 according to address information from the CPU 201 and outputted to the main data bus 208. The font cards 205 and 206 are in the form of a connector-in type ROM card. 20
Reference numeral 9 denotes a printer engine section that constitutes a system related to image printing processing, including a control panel (not shown) and the like. An engine controller 210 controls the printer engine unit 209 according to address information and data from the CPU 201 via the engine interface 211, reads data from the printer engine unit 209, and encodes data from the external device 212. Image data is transferred to parallel interface 21
3. Furthermore, engine controller 2
Reference numeral 10 denotes an electric erasable programmable ROM (hereinafter referred to as EEP) provided for storing information such as print status and page count from the control panel of the printer engine unit 209.
It is abbreviated as ROM. ) 214, read and write information according to address information from the CPU 201. 215 is coded image data input from the external device 212, character font bitmap data,
A DRAM 216 that can be read and written at any time and stores other data is connected to the DRAM 215.
A DRAM controller that generates DRAM address information and timing signals necessary for reading and writing data according to address information from the CPU 201, accesses data to the DRAM 215, arbitrates the main data bus 208, and refreshes data in the DRAM 215. be. Furthermore, the DRAM controller 216
converts the image data stored in the DRAM 215 from parallel to serial, and generates a video data synchronization signal (V
CLK), it is output to the compensation circuit 218 as image bitmap image data. Further, the DRAM controller 216 has a function of shifting image data in order to overlap or offset images according to information from the external device 212 or the control panel of the printer engine unit 209. In addition, DRAM21
The memory area of No. 5 can be expanded by expansion DRAMs 219 and 220.

Here, the compensation circuit 218 receives a video data synchronization signal (VCLK) from the DRAM controller 216.
The image bitmap image data that is input in synchronization with is replaced with an image dot signal that drives the laser drive unit 2011, and this image dot signal is corrected to improve print quality, and the corrected image dot signal after correction is (VD
O) is output to the laser drive unit 2011. For example, in the process of converting analog characters into digital bitmap images, this compensation eliminates steps, step-like distortions, and print quality that occur due to the low resolution of the bitmap image or the low sampling rate of the desired analog image. Reduce deterioration, etc.

FIG. 22 shows a block diagram of a compensation circuit using a matching network that constitutes a controller section of an image forming apparatus disclosed in US Pat. No. 4,847,641. In FIG. 22, reference numeral 101 denotes a temporary storage means for temporarily storing a part of the image bitmap image data. It is provided for the purpose of sampling the column image bitmap image data, and has a sample window circuit composed of a shift register, and the image bitmap image data is sequentially stored in the shift register that constitutes this sample window circuit. be done. A sample window diagram of this sample window circuit is shown in FIG. D in Figure 23
4 is the target of correction. 2201 is a matching network means for comparing whether the sample pattern stored in the sample window matches a plurality of predetermined template patterns; an example of the plurality of predetermined template patterns is shown in FIG. show. Reference numeral 106 denotes a matching network means 2201, which is a signal generating means for correcting the signal of the image bitmap image data to be corrected into a predetermined signal when the sample pattern matches one of a plurality of predetermined template patterns. It is.

FIG. 25 is a block diagram of the temporary storage means 101. In FIG. 25, 301 is a memory control circuit that generates addresses and other control signals necessary for reading and writing data to the memory. 3
02 is a memory circuit, which is a high-speed static RAM (hereinafter referred to as S
It is abbreviated as RAM. ), and reading out a video signal (VDIN) which is image bitmap image data configured with flip-flops and converted to serial data;
Writing is performed using the address output by the memory control circuit 301 and other control signals. A sample window circuit 303 is composed of a shift register and stores SRAM data read from the memory circuit 302 and outputs a sample pattern.

FIG. 26 is a circuit diagram of the memory control circuit 301, FIG. 27 is a circuit diagram of the memory circuit 302, FIG. 28 is a circuit diagram of the sample window circuit 303, and FIG. 29 is a circuit diagram of the comparison circuit that is part of the matching network means 2201. It is a circuit diagram. In FIG. 26, 2401 to 2403
is a 4-bit synchronous counter; in FIG. 27, 2501 is an SRAM; 2502 is an 8-bit latch; and 2503 is an inverter; in FIG. 28, 2601 to 2607 are 8-bit shift registers; in FIG.
0 is a two-input exclusive OR (hereinafter abbreviated as Ex-OR), and 2801 is a multi-input NAND (hereinafter referred to as NAN).
It is abbreviated as D. ), 2802 is a multi-input OR (hereinafter referred to as OR
It is abbreviated as. ).

The operation of the compensation circuit constituting the controller section of the image forming apparatus using the matching network configured as described above will be described below. In FIG. 27, the video signal (VDIN), which is image bitmap image data sent via the video signal (VDIN) line, is connected to the video data synchronization signal (VCLK).
Accordingly, the SRA is serially input to D0 of the 8-bit latch 2502, latched at the falling edge of the video data synchronization signal (VCLK), and input to A0 to A11 of the SRAM 2501 by addresses SRA0 to SRA11.
Stored in IO0 of M2501. This address SRA
0 to SRA11 are the 4-bit synchronization counter 240 in FIG.
1 to 2403 are video data synchronization signals (VCLK) and are 0
It is obtained by counting up from (H). Similarly, the address of the next video signal (VDIN) is incremented at the rising edge of the video data synchronization signal (VCLK) and stored in IO0 of the SRAM 2501. Through this series of operations, one line of main scanning of the image bitmap image data is transferred to IO0 of the SRAM2501.
is stored in

[0019] This one line is the IO of SRAM2501.
When stored at 0, the 4-bit synchronization counter 240 in FIG.
1 to 2403 are reset by the main scanning reference signal (NLSYNC), and the video signal (VDIN), which is the image bitmap image data of the second line, is transferred to the 8-bit latch 2502 according to the video data synchronization signal (VCLK).
At D0 of the SRAM 2501, the first line data stored in IO0 of the SRAM 2501 is read out in order from address 0 (H), input to D1 of the 8-bit latch 2502, latched, and input to D0 of the 8-bit latch 2502. The data is at address 0 (H) of IO0 of SRAM2501
Then, the data input to D1 of the 8-bit latch 2502 is stored at address 0 (H) of IO1 of the SRAM 2501.

By repeating the above operations, the SRAM
Image bitmap image data is input to IO0 to IO6 of 2501 for each line, and at the same time as this operation is performed, the output of 8-bit latch 2502 is transferred to 8-bit shift register 2601 that constitutes the sample window circuit shown in FIG. 2607, and the 8-bit shift registers 2601 to 2607 shift the input data according to the video data synchronization signal (VCLK), and convert the input data into a video signal (VD) which is image bitmap image data.
The data shown in FIG. 23 of IN) is stored. The stored sample pattern data and the predetermined template pattern data shown in FIG. 24 are respectively input to Ex-ORs 2803 to 2840 of the comparison circuit of the matching network means 2201 shown in FIG. OR2803-2840 outputs L level when the input data match, and outputs H level when they do not match to multi-input NAND 2801, and connects the multi-input NAND
D2801 is all L from Ex-OR2803 to 2840
When the level is output, the H level is outputted to the signal generating means 106 shown in FIG. 22 via the multi-input OR 2802.

The signal generating means 106 shown in FIG. 22 uses this H level to convert the image bitmap image data signal to be corrected into a template pattern used when the multi-input NAND 2801 outputs the H signal via the multi-input OR 2802. Replace with a corrected image dot signal according to.

Here, the signal generating means 106 shown in FIG.
FIG. 30 shows the corrected image dot signal output from the. X
signal, Y signal, Z signal, and W signal are multi-input NAN
Approximately 1/3 front, approximately 2/3 rear, approximately 2/3 front, and approximately 1/3 rear of one dot, corresponding to the template pattern used when D2801 outputs an H signal via multi-input OR2802.
This is a corrected image dot signal that outputs only 3.

Through the above series of operations, the result shown in FIG. 31(a) is
, and the image bitmap image data shown in FIG. 32(a) is a 1-bit signal of the image bitmap image data to be corrected, as shown in FIGS. 31(b) and 32(c) By replacing this with a corrected image dot signal that outputs only 1/3 or 2/3 of the front and rear or top and bottom of normal dots, steps such as diagonal lines are smoothed out.

[0024]

[Problems to be Solved by the Invention] However, in the above configuration, the template pattern used for correcting the image bitmap image data remains the same even when the surrounding environmental conditions change, but the photoreceptor temperature,
Sensitivity changes depending on environmental conditions such as humidity and type of light source, so the amount of toner adhering to the photoreceptor changes, and depending on the surrounding environment, the size of the correction dot may be too large or too small, resulting in insufficient correction. This has the problem that there are cases where the following occurs.

[0025]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention sets a part of an area where an image composed of dots of an orthogonal matrix is written as a window, and moves this set position within the area. a first edge detection means for detecting a difference in image data between a predetermined dot and a dot adjacent to the predetermined dot in the window set by the window setting means capable of controlling the window setting means, and a direction of the difference; Detecting a difference in the image data between adjacent dots other than a predetermined dot and an edge having a difference in the same direction as the direction of the difference detected by the first edge detection means, and outputting it as edge data. and a predetermined value according to the position of the edge corresponding to the edge data output from the second edge detection means relative to the position of the edge detected by the first edge detection means. weighting means;
A calculation means for obtaining the sum of predetermined values set by the weighting means, and a threshold value for detecting the environmental condition around the device and determining the type of correction for a predetermined dot based on the value obtained by the calculation means, depending on the environmental condition. environmental condition detection means for generating a signal for changing the size of a predetermined dot according to the value obtained by the calculation means and the information obtained by the environmental condition detection means for generating a signal for changing the size of a predetermined dot. It is equipped with the following.

[0026]

[Operation] With the above-described configuration, the present invention is capable of detecting a difference in image data between a predetermined dot in the sample window and a dot adjacent to the predetermined dot, and a difference in image data corresponding to the dots adjacent to each other. Set a predetermined value, obtain the sum of these values, use the obtained value to change the threshold value that determines the type of correction for a predetermined dot, depending on the environmental condition around the device, and then calculate the predetermined value based on these results. Correction can be performed by changing the size of the dots.

[0027]

Embodiment An image forming apparatus according to an embodiment of the present invention will be described below. Here, the mechanical section of the image forming apparatus and the controller section other than the compensation circuit of the image forming apparatus are the same as those shown in the above-mentioned conventional technology, and therefore the explanation thereof will be omitted.

FIG. 1 is a block diagram of a compensation circuit constituting a controller section of an image forming apparatus according to an embodiment of the present invention. In FIG. 1, 101 is a temporary storage means, 301
is a memory control circuit, 302 is a memory circuit, 30
Reference numeral 3 denotes a sample window circuit, which has the same configuration as that shown in the above-mentioned conventional technique, so detailed explanation will be omitted. Reference numeral 102 denotes an edge detection means for detecting an edge from the image bitmap image data in the sample window shown in FIG. (0 or 1) and the attributes of the data of 1 bit of data of the dots on the top, bottom, left and right of this dot are different (for example, the image data of 1 dot at a predetermined position is 0, and the data of the data of the dots on the top, bottom, left and right of this dot are different) If the image data of 1 dot at a predetermined position is 1, and the image data of 1 dot at a predetermined position is 1,
, the image data of the dots adjacent to the top, bottom, left, and right is 0.
) is determined to have an edge, and if there is an edge, 1 is output as edge data; otherwise, 0 is output as edge data. Among the edge data detected by the edge detection means 102, edge data located at a specific location within the sample window is selected by the edge data selection means 107.
Depending on the edge data located at a specific location within the sample window other than the edge data located at this specific location, it is selected whether to output it as edge data or not. Reference numeral 103 refers to a plurality of edge data detected by the edge detection means 102 and selected by the edge data selection means 107 to the upper, lower, left and right edges of the dot corresponding to the image data D4 to be corrected located at the center of the sample window. (Whether the data adjacent to the image data D4 in the vertical and horizontal directions is from 0 to 1 or from 1 to 0, and whether the edge direction is upward,
108 is an ambient temperature; An environment detection means 104 detects environmental conditions such as humidity, the type of photoreceptor and light source, and outputs environmental data; reference numeral 104 denotes a plurality of edge data summarized by the weighting means 103, and the top, bottom, left and right of the dot corresponding to the image data D4. Multiplying by a predetermined numerical value according to the position with respect to the edge and performing a logical operation, and changing the threshold value for determining the type of correction of the dot corresponding to the image data D4 according to the environmental data output from the environment detecting means 108, logical operation means for generating and outputting correction data;
Reference numeral 106 denotes a signal generating means for replacing the signal of the image data D4 to be corrected with a corrected image dot signal for driving the laser driving section 2011 shown in FIG. be.

FIG. 2 shows a configuration diagram of the edge detection means 102, edge data selection means 107, weighting means 103, logic operation means 104, and environment detection means 108. In FIG. 2, 401 detects whether there is an edge between adjacent bits in the main scanning direction of the image bitmap image data in the sample window shown in FIG. 23, and outputs the detected edge as edge data. , a vertical edge detection and selection circuit 402 that detects whether or not there is an edge between adjacent bits in the sub-scanning direction, and a horizontal edge detection and selection circuit that selects whether or not to output the detected edge as edge data. This vertical edge detection and selection circuit 40 is an edge detection and selection circuit.
1. The horizontal edge detection and selection circuit 402 constitutes the edge detection means 102 and edge data selection means 107 shown in FIG. 403A detects a plurality of pieces of edge data existing between bits adjacent in the main scanning direction, detected by the vertical edge detection and selection circuit 401, and extracts each edge data of the image data D4 to be corrected located at the center of the sample window shown in FIG. Types of left and right edges (with respect to image data D4, whether the data adjacent to the left and right is from 0 to 1 or from 1 to 0, and whether the direction of the edge is to the right or to the left) When the image data D4 to be corrected is 0, the signal line A
A vertical edge data weighting circuit outputs 1 to DD and 1 to the signal line DEL when it is 1. 403B is a vertical edge data weighting circuit that outputs 1 to the signal line DEL when it is 1; 403B is a vertical edge data weighting circuit that outputs 1 to the signal line DEL; The types of the upper and lower edges of the image data D4 to be corrected located in the center of the sample window shown in FIG. to 0, and whether the edge direction is upward or downward), and grouped according to the position of the image data D4 with respect to the upper and lower edges, and if the image data D4 to be corrected is 0. A horizontal edge data weighting circuit outputs 1 to the signal line ADD when 1, and 1 to the signal line DEL when 1, and the vertical edge data weighting circuit 403A and the horizontal edge data weighting circuit 403B perform the weighting means shown in FIG. 103 is configured. Reference numeral 408 denotes an environment detector that detects the temperature of environmental conditions such as ambient temperature, humidity, and the type of photoreceptor and light source, and outputs environmental data. This is the environment detection means 108 shown in FIG. 404A, 404B, 404C, 404
D is a plurality of edge data summarized by the vertical edge data weighting circuit 403A and the horizontal edge data weighting circuit 403B at positions relative to the top, bottom, left, and right edges of the image data D4 to be corrected located in the center of the sample window shown in FIG. It has a multiplication function that multiplies a predetermined value according to the number, and adds after multiplying each plurality of edge data by a predetermined value, and when the addition result is 8 or more, 1 is added as data to the signal line Z8. Addition circuits that output 1 as data to signal line Z9 when the result is 9 or more; 407A to 407D are addition circuits 404A and 40
Z8 output from 4B, 404C, 404D or
Selectors 406A to 406H select one of Z9 according to environmental data sent directly from the environment detector 408 or via the inverter 405, and selectors 407A to 407D are selected from adder circuits 404A, 404B, 404C, and 404D. data sent through the signal lines ADD and DE from the vertical edge data weighting circuit 403A and the horizontal edge data weighting circuit 403B.
These adder circuits 404A, 404B, 40
4C, 404D, inverter 405, selector 407A
407D and two-input ANDs 406A to 406H constitute the logic operation means 104 shown in FIG.

FIG. 3 is a circuit diagram of the environment detector 408, and FIG. 4 is a circuit diagram of a vertical edge detection circuit constituting a portion of the edge detection means 102 of the vertical edge detection and selection circuit 401.
5 is a circuit diagram of a vertical edge data selection circuit that constitutes the edge data selection means 107 portion of the vertical edge detection and selection circuit 401, and FIG. 6 is a circuit diagram that constitutes the edge detection means 102 portion of the horizontal edge detection and selection circuit 402. A circuit diagram of a horizontal edge detection circuit. FIG. 7 is a circuit diagram of a horizontal edge data selection circuit constituting a portion of the edge data selection means 107 of the horizontal edge detection and selection circuit 402. FIGS. 8 and 9 are a circuit diagram of a vertical edge data weighting circuit 403A. In the circuit diagram of , the horizontal edge data weighting circuit 403B is also shown in FIGS. 8 and 9.
This is the same circuit diagram. FIG. 10 shows adder circuits 404A, 40
4B, 404C, and 404D. FIG. 11 is a circuit diagram of the signal generating means 305 shown in FIG.

In FIG. 3, 5001 is a thermistor provided around the photosensitive drum of the laser printer;
02 is a comparator, 5003 is a resistor for voltage division, 500
4, 5005 is a resistor for creating a reference voltage, 5006
is a pull-up resistor, and in FIG. 4, 501 to 528 are 2
Input AND, 529-549 are inverters, In Fig. 5, 601-608 are 3-input AND, 609-616 are inverters, In Fig. 6, 701-728 are 2-input A
ND, 729 to 749 are inverters, and in FIG. 7, 8
01 to 808 are 3-input ANDs, 809 to 816 are inverters, and in FIG. 8, 1001 to 1012 are AND-Os.
R inverter, 1013 to 1024 are inverters, 10
25, 1026 are buffers, 1027 is 2 input OR, 1
028 to 1031 are 3-input OR, in FIG. 9, 110
1 to 1112 are AND-OR inverters, 1113 to 1
124 is an inverter, 1125 and 1126 are buffers,
1127 to 1129 are 2 input OR, 1130 to 1133
is a 3-input OR, in Figure 10, 1301 to 1310 are 3-input 1-bit full adders, 1311 is a 4-input OR, 1
312 is a 3-input OR, and 1313 is a 2-input AND. In FIG. 11, 1501, 1502, 1507, 15
08 is 3 input OR, 1503, 1506 is 4 input OR,
1504 and 1505 are 5-input OR, and 1509 is an 8-bit parallel load serial output shift register (hereinafter referred to as 8
It is abbreviated as bit shift register. ), 1510 is 6-input NOR, 1511 is 2-input AND, 1512, 151
3 is a two-input OR, and 1514 is an inverter.

The operation of the compensation circuit constituting the controller section of the image forming apparatus constructed as described above will be explained below.

In the environment detection circuit shown in FIG. 3, a temperature change around the photosensitive drum of a laser printer is converted into a voltage change by a thermistor 5001 and a resistor 5003 provided around the photosensitive drum, and the voltage is input to a comparator 5002. do. In the comparator 5002, the thermistor 50
The voltage corresponding to the ambient temperature change converted by 01 and resistor 5003 is compared with the reference voltage created by resistors 5004 and 5005, and if the ambient temperature has not reached the reference temperature, 1 (" If the temperature exceeds the reference temperature, 0 ("L" level) is output as the environmental data.

In the vertical edge detection circuit shown in FIG.
3-A5, B3-B5, C3-C5, D3-D5, E3
~E5, F3~F5, G3~G5, the image data sent from the sample window circuit 303 of FIG.
528, the image data in the 3rd and 4th columns and the 4th and 5th columns of the sample window shown in FIG. It is detected whether the edge changes from 1 to 1 or from 1 to 0 (hereinafter referred to as white to black or black to white) and outputs it as edge data. This edge data sets 1 to the signal line V1 when the 3rd column of row A is white and the 4th column is black, and when the 3rd column of row B is white and the 4th column is black, it is a signal. 1 is output to the line V2, and in the case of the C-th to G-th lines, 1 is output to each of the signal lines V3 to V7. Furthermore, if the third column is black and the fourth column is white in each row from the A-th row to the G-th row, 1 is assigned to each of the signal lines NV1 to NV7, and A
In each row from row G to row G, the 4th column is white and 5
If the column is black, 1 is applied to each of the signal lines VV1 to VV7.
If the fourth column is black and the fifth column is white in each row from A to G, the signal lines NVV1 to NVV
Output 1 to each of 7.

In the vertical edge data selection circuit of FIG. 5, signal lines B2, B3, B5, B6, F2, F3, F5, F6
The image data sent from the sample window circuit 303 in FIG. 1 and the signal lines NVV5, VV5, N
The edge data sent from the vertical edge detection circuit of FIG.
01 to 608, the second and third columns of row B, the fifth and sixth columns of row B, and the second column of row F of the sample window shown in FIG. The image data in the 3rd column and the 5th and 6th columns of the F row are 0 in the main scanning direction.
to 1 or from 1 to 0, edge data from signal lines NVV5, VV5, edge data from signal lines NV5, V5, signal lines NVV3, V
Depending on the edge data from V3 and the edge data from signal lines NV3 and V3, it is selected whether to output each as edge data. This edge data selection means that the edge data from the signal line NVV5 is 1, that is, the 4th edge data in the E row.
When the column is black and the fifth column is white, the edge data when the second column of row B is black and the third column is white is selected as edge data, and 1 is set to the signal line NV12, and so on. Signal line VV
If the edge data from 5 is 1, that is, the 4th column of row E is white and the 5th column is black, the edge data when the 2nd column of row B is white and the 3rd column is black is edge data. If the edge data from the signal line NV5 is 1, that is, the third column of the E row is black and the fourth column is white, then B
The edge data when the 5th column of the row is black and the 6th column is white is selected as edge data, and 1 is set to the signal line NVV12.
If the edge data from signal line V5 is 1, that is, the 3rd column of row E is white and the 4th column is black, then the 5th column of row B is white and 6.
The edge data when the column is black is selected as edge data, and the signal line VV12 is set to 1, and the edge data from the signal line NVV3 is 1, that is, when the 4th column of the C row is black and the 5th column is white. , the edge data when the second column of the F row is black and the third column is white is selected as the edge data and is sent to the signal line NV1.
If the edge data from the signal line VV3 is 1, that is, the 4th column of the C row is white and the 5th column is black, then the 2 of the F row
The edge data when the column is white and the third column is black is selected as edge data, and 1 is set to the signal line V16, and the signal line NV3 is set to 1.
The edge data from is 1, that is, the 3rd column of row C is black and 4
When the column is white, the edge data when the 5th column of the F row is black and the 6th column is white is selected as edge data, and the edge data from the signal line NVV16 is set to 1, and the edge data from the signal line V3 is set to 1. In other words, if the third column of row C is white and the fourth column is black, then F
Edge data when the fifth column of the row is white and the sixth column is black is selected as edge data and outputs 1 to the signal line VV16.

In the horizontal edge detection circuit of FIG.
1 to C7, D1 to D7, and E1 to E7, the image data sent from the sample window circuit 303 in FIG.
~728, the C-th row and D from the 1st column to the 7th column of the sample window shown in FIG.
It is detected whether the image data of the row, D row, and E row change from 0 to 1 or from 1 to 0 in the sub-scanning direction, and output as edge data. If the C row is white and the D row is black in each column from the 1st column to the 7th column, 1 is sent to the signal lines H1 to H7, respectively.
If the C row is black and the D row is white in each column from the 1st column to the 7th column, set 1 to each of the signal lines NH1 to NH7, and each of the signal lines from the 1st column to the 7th column. D in the column
If the row is white and the E row is black, the signal lines HH1 to H
If 1 is set for each H7, and the D row is black and the E row is white in each column from the 1st column to the 7th column, the signal line NHH
Outputs 1 from 1 to NHH7, respectively. In the horizontal edge data selection circuit of FIG. 7, signal lines B2, C2, B6, C6,
The image data sent from the sample window circuit 303 in FIG. 1 and the signal lines NHH5, HH5, NHH3, HH3, NH5, H5 are sent to each of E2, F2, E6, and F6.
, NH3, and H3, the edge data sent from the vertical edge detection circuit of FIG.
816 and 3-input ANDs 801 to 808, the B-th and C-th rows of the second column, the B-th and C-th rows of the sixth column, and the second column of the sample window shown in FIG. It is detected whether the image data of the E-th and F-th rows and the E-th and F-th rows of the sixth column change from 0 to 1 or from 1 to 0 in the main scanning direction, and the signal lines NHH5, Depending on the edge data from HH5, the edge data from signal lines NHH3 and HH3, the edge data from signal lines NH5 and H5, and the edge data from signal lines NH3 and H3, select whether to output them as edge data or not. do. This edge data selection is performed when the edge data from the signal line NHH5 is 1, that is, the D row of the 5th column is black and the E row is white, the B row of the 2nd column is black and the C row is black. The edge data when it is white is selected as edge data and 1 is set in the signal line NH12. Similarly, if the edge data from the signal line HH5 is 1, that is, the D row of the 5th column is white and the E row is black. , the edge data when the B row of the second column is white and the C row is black is selected as edge data, and the signal line H12 is set to 1, and the signal line NH is set to 1.
If the edge data from H3 is 1, that is, the D row of the 3rd column is black and the E row is white, the edge data when the B row of the 6th column is black and the C row is white is the edge data. When the edge data from the signal line HH3 is 1, that is, the D row of the third column is white and the E row is black, the B row of the sixth column is white and C The edge data when the row is black is selected as edge data, and 1 is set to the signal line H16.
The edge data from signal line NH5 is 1, that is, C in the 5th column.
When the row is black and the D row is white, the edge data when the E row of the second column is black and the F row is white is selected as edge data, and the signal line NHH12 is set to 1, and the signal line H5 is set to 1. If the edge data from is 1, that is, the C row of the 5th column is white and the D row is black, the edge data when the E row of the 2nd column is white and the F row is black is the edge data. Selected signal line HH1
If the edge data from the signal line NH3 is 1, that is, the third column C row is black and the D row is white, then the edge data from the signal line NH3 is 1.
The edge data when the row is black and the F row is white is selected as edge data, and the signal line NHH16 is set to 1, and the signal line H is set to 1.
If the edge data from 3 is 1, that is, the C row of the 3rd column is white and the D row is black, the edge data when the E row of the 6th column is white and the F row is black is the edge data. is selected and outputs 1 to the signal line HH16.

In the vertical edge data weighting circuits of FIGS. 8 and 9, signal lines A1 to A7, NA1 to NA7, B1 to B
7, NB1-NB7, A12, NA12, B12, NB
12, A16, NA16, B16, NB16,
From the vertical edge detection circuit in Figure 4, the signal lines V1 to V7 and NV
1 to NV7, VV1 to VV7, NVV1 to NVV7, and the signal line V12 from the vertical edge data selection circuit of FIG.
, NV12, VV12, NVV12, V16, NV16
, VV16, and NVV16 are input to the AND-OR inverter 1001 in FIG.
1012, inverters 1013-1024, buffers 1025, 1026, 2-input OR 1027, and 3-input AND 1028-1031; in FIG. 9, AND-OR inverters 1101-1
112, inverters 1113 to 1124, and buffer 11
25, 1126, 2 input OR1127, and 3 input A
The data selection block consisting of ND1130 to ND1133 selects the left and right edge types (
In the vertical edge data weighting circuit of FIG. 8, the vertical edge data weighting circuit of FIG.
Regarding an edge of the same type as the left edge of image data D4 of the sample window shown in , if the edge exists between the third and fourth columns of row A of the sample window, the signal line AX11 is 1, row B, 3rd column and 4
If it exists between the C-th column and the G-th row, set 1 to the signal line AX12, and similarly from the C-th row to the G-th row, set the signal line AX13 to
outputs 1 from each to AX17.

Here, regarding the edge of the same type as the leftward edge of the image data D4 in the signal line AX12,
In addition to the case where the edge exists between the third and fourth columns of row B of the sample window, the image data D4
Regarding the same type of edge as the leftward edge of , in the sample window selected by the vertical edge data selection circuit of FIG. If there is an edge of the same type as the eye edge, and if there is an edge of the same type as the edge in the 3rd and 4th columns of E row between the 5th and 6th columns of B row However, 1 is output. Similarly, in the signal line AX16, regarding the same type of edge as the leftward edge of the image data D4, only when the edge exists between the 3rd and 4th columns of the F row in the sample window. Image data D
Regarding the same type of edge as the leftward edge of 4, Fig. 5
If there is an edge of the same type as the edge in the 4th column and 5th column of the C row in the 2nd column and 3rd column of the F row of the sample window selected by the vertical edge data selection circuit of the F 1 even if there is an edge of the same type as the edge in the 3rd and 4th columns of the C row between the 5th and 6th columns of the row.
is output.

Furthermore, if the edge exists between the 4th and 5th columns from the A-th row to the C-th row, the signal line AX
1 is output to each of signal lines 21 to AX23, and when the edge exists between the fourth and fifth columns from the Eth row to the Gth row, 1 is outputted to each of the signal lines AX25 to AX27.

Also, in the vertical edge data weighting circuit of FIG. 9, similarly to the vertical edge data weighting circuit of FIG. 8, regarding the same type of edge as the right edge of the image data D4 of the sample window shown in FIG. 4 whose edges are from row A to row G of the sample window
If it exists between the 5th column and the 5th column, the signal line BX1
1 to BX17, and if the edge exists between the 3rd and 4th columns from row A to row C, set 1 to each of the signal lines BX21 to BX23, and the edge is set to row E. If it exists between the third and fourth columns from the Gth row to the Gth row, 1 is output to each of the signal lines BX25 to BX27.

Here, regarding the edge of the same type as the right edge of the image data D4 in the signal line BX12,
Not only when the edge exists between the 4th and 5th columns of row B of the sample window, but also when the edge exists in the image data D4
Regarding the edge of the same type as the rightward edge of If there is an edge of the same type as the eye edge, and if there is an edge of the same type as the edge in the 3rd and 4th columns of E row between the 5th and 6th columns of B row However, 1 is output. Similarly, for the signal line BX16, regarding the same type of edge as the right edge of the image data D4, only when the edge exists between the 3rd and 4th columns of the F row in the sample window. Image data D
Regarding the same type of edge as the rightward edge of 4, Fig. 5
If there is an edge of the same type as the edge in the 4th column and 5th column of the C row in the 2nd column and 3rd column of the F row of the sample window selected by the vertical edge data selection circuit of the F 1 even if there is an edge of the same type as the edge in the 3rd and 4th columns of the C row between the 5th and 6th columns of the row.
is output.

Furthermore, in the vertical edge data weighting circuit of FIG. 9, when the image data D4 to be compensated is 0, 1 is output to the signal line ADD, and when it is 1, 1 is output to the signal line DEL.

[0043] Horizontal edge data weighting circuit 403B
Since this circuit is similar to the vertical edge data weighting circuit of FIGS. 8 and 9, the explanation of the circuit will be omitted. In the horizontal edge data weighting circuit 403B, signal lines A1 to A7, NA1
~NA7, B1~B7, NB1~NB7, A12, A1
6, NA12, NA16, B12, B16, NB12,
From the horizontal edge detection circuit of FIG. 6, signal lines H1 to H7, NH1 to NH7, HH1 to HH7, and NH
H1 to NHH7, and signal lines H12, H16, NH12, NH16, H from the horizontal edge data selection circuit in FIG.
The horizontal edge data sent via H12, HH16, NHH12, and NHH16 is converted to image data D4 to be corrected located in the center of the sample window shown in FIG.
The image of the sample window shown in Figure 23 is classified according to the type of the upper and lower edges (white to black, black to white, and whether the edge direction is upward or downward). The signal lines AX11 to AX17, AX21 to AX according to the position relative to the upper and lower edges of data D4
23, AX25 to AX27, and BX11 to BX
17. Output 1 from BX21 to BX23, and from BX25 to BX27.

Here, the vertical edge data weighting circuit 403A classifies the image data D4 to be corrected located at the center of the sample window shown in FIG. 23 according to the type of the left and right edges, and the image data D4
Figures 12(a) and 12(b) show the state of vertical edge data that is grouped according to the position relative to the left and right edge positions of
Then, the horizontal edge data weighting circuit 403B classifies the image data D4 to be corrected located at the center of the sample window shown in FIG. FIGS. 13(a) and 13(b) show the states of horizontal edge data that are collected accordingly. Figure 12(a)
, FIG. 12(b), FIG. 13(a), and FIG. 13(b), the number written between the bits indicates that the edge between the bits is the weight related to the compensation of the central bit D4. It shows.

In FIG. 12(a), when there is an edge between the center bit D4 and the bit D5 on the right side, the weight of the right edge of the bit in the fourth column, which is the same column as the center bit D4, is all 1. , the weight of the left edge of the bit in the fourth column is 2
Or it becomes 4, and the right edge of the second column of the B row is E
If the edge on the right side of the 4th column of the row B is the same type of edge, then the edge on the left side of the 6th column of the B row is the same type of edge as the left edge of the 4th column of the E row. , if the right edge of the 2nd column of the F row is the same type of edge as the right edge of the 4th column of the C row, and the left edge of the 6th column of the F row is the edge of the C row If the edges are of the same type as the left edge in the fourth column, the weight of these edges is 1.

FIG. 12(b) shows that when there is an edge between the center bit D4 and the bit D3 on the left side, the weight of the left edge of the bit in the fourth column, which is the same column as the center bit D4, is all 1. , the weight of the right edge of the fourth column bit is 2
Or it becomes 4, and the right edge of the second column of the B row is E
If the edge on the right side of the 4th column of the row B is the same type of edge, then the edge on the left side of the 6th column of the B row is the same type of edge as the left edge of the 4th column of the E row. , if the right edge of the 2nd column of the F row is the same type of edge as the right edge of the 4th column of the C row, and the left edge of the 6th column of the F row is the edge of the C row If the edges are of the same type as the left edge in the fourth column, the weight of these edges is 1.

FIG. 13(a) shows that when there is an edge between the center bit D4 and the bit E4 below it, the weight of the lower edge of the bit in the D-th row, which is the same row as the center bit D4, is All 1, the weight of the upper edge of the D-th row bit is 2
Or it becomes 4, and the upper edge of the second column of the C row is D
E If the lower edge of the 2nd column of the row is the same type of edge as the upper edge of the 5th column of the D row, and the lower edge of the 6th column of the E row is the same type of edge as the upper edge of the 5th column of the D row If the edges are of the same type as the upper edge, the weight of these edges is 1.

FIG. 13(b) shows a case where there is an edge between the center bit D4 and the bit C4 above it, and the weight of the upper edge of the bit in the D-th row, which is the same row as the center bit D4, is all 1, the lower edge of the bit in row D is 2 or 4, and the upper edge in row C, 2nd column is the same type of edge as the lower edge in row D, 5th column, If the upper edge of the 6th column of the C row is the same type of edge as the lower edge of the 3rd column of the D row, then the lower edge of the 2nd column of the E row is the same type of edge as the lower edge of the 6th column of the D row. If it is the same type of edge as the upper edge, and 6 of the Eth row
If the lower edge of the column is the same type of edge as the upper edge of the third column of the D-th row, the weight of these edges is 1.

In the adder circuit of FIG. 10, the signal line VAX11
~VAX17, VAX21~VAX23, VAX25~
To VAX27, from the vertical edge data weighting circuit and horizontal edge data weighting circuit of FIGS. 8 and 9, signal line AX1
1~AX17, AX21~AX23, AX25~AX2
7, or signal lines BX11 to BX17, BX21 to BX
23, sent via BX25 to BX27, Figure 2
Three inputs of edge data are classified according to the types of the top, bottom, left, and right edges of the image data D4 to be corrected located at the center of the sample window shown in 3, and are grouped according to the position relative to the top, bottom, left, and right edge positions of the image data D4. 1
Bitful adder 1301 to 1310, 2 input AND1
313, 3-input OR1312, and 4-input OR1311, edge data with a weight of 1 (signal line Edge data of VAX11 to VAX17), 2
(signal lines VAX21, VAX22,
VAX26, VAX27 edge data) and data with a weight of 4 (signal line VAX23, VAX25 edge data) are logically operated according to their respective weights, and when the result of this logical operation is a weight of 8 or more, To Z8,
When the logical operation result is 9 or more, 1 is output to Z9 as a compensation signal for compensating the image data D4 to be compensated located at the center of the sample window shown in FIG.

Here, the operation of the adder circuit in FIG. 10 is shown in FIG.
This will be explained using pattern diagrams of image data shown in FIGS. 14(a), 14(b), 15(a), and 15(b). Figure 14(a)
, FIG. 14(b), FIG. 15(a), and FIG. 15(b), blank frames indicate white dots, and diagonally lined frames indicate black dots. In the pattern of Fig. 14(a), 1+1+1+1
+1+2+1=8, 1+1 in the pattern of Figure 14(b)
+1+4+1=8, 2+2 in the pattern of Figure 15(a)
+1+1+1+1+1=9, and in the pattern of FIG. 15(b), 1+1+1+4+2+1=10, and the adder circuit 40
4A to 404D, FIG. 14(a) and FIG. 14(
b) to Z8, and Fig. 15(a) and Fig. 15(b) to Z9.
1 is output.

In the two-input ANDs 406A to 406H in FIG. 2, four adder circuits 404A, 404B, 404C, 4
Among the data sent from 04D via signal lines Z8 and Z9, selectors 407A to 407D select one selected based on the environmental data sent from the environment detector 408, and the vertical edge data weighting circuit 403.
A. Eight signal lines L1, L2, R1,
Data is output to R2, UP1, UP2, DN1, and DN2.

The output of this data is, for example, as shown in FIG. 14(a).
In this pattern, 1 is input from the adder circuit 404B to the selector 407B via the signal line Z8. Here, if the temperature around the photosensitive drum of the laser printer is lower than the reference temperature, the environmental data from the environmental detector 408 is 1, so the signal line Z9 is selected by the selector 407B, and the signal is input to the selector 407B. The signal from line Z8 is not output and no compensation is performed. However, if the temperature around the photosensitive drum of the laser printer is higher than the reference temperature, the environmental data from the environmental detector 408 is 0, so the selector 407B selects the signal line Z8, and the signal from the selected signal line Z8 By inputting the signal 1 of 1 and the signal 1 sent from the vertical edge data weighting circuit 403A via the signal line ADD to the 2-input AND 406C, 1 is output to the signal line R1 and compensation is performed.

This means that when the environmental data is 1, that is, the temperature around the photosensitive drum is below the reference temperature, the sensitivity of the photosensitive drum of the laser printer is lower than when the surrounding temperature is above the reference temperature, and the toner Since the amount of adhesion decreases and the image dots become thinner, if the same compensation is applied when the ambient temperature is higher than the reference temperature, cuts will occur in the diagonal lines. For this reason, even if compensation is performed when the temperature around the photosensitive drum is above the standard temperature, compensation is prohibited when the surrounding temperature is below the standard temperature, and the print quality is improved by preventing cuts in the diagonal lines. It aims to improve the

[0054]Although temperature is described in this example, regarding humidity, etc., when the surrounding humidity is higher than the reference humidity, the temperature of the photosensitive drum of the laser printer is lower than when the surrounding humidity is below the reference humidity. Since the sensitivity decreases, the same effect can be obtained by setting the environmental data to 1 and prohibiting correction.

In the signal generation circuit of FIG. 11, the two inputs A of FIG.
Eight signal lines L1, L2 from ND406A to 406H,
Data is input via R1, R2, UP1, UP2, DN1, and DN2, and according to these data, a signal corresponding to the image data D4 to be corrected located at the center of the sample window shown in FIG. 23 is corrected, Output from 8-bit shift register 1509.

The output of this signal is, for example, as shown in FIG. 14(a).
In this pattern, if the temperature around the photosensitive drum is higher than the reference temperature, the data of signal line R1 becomes 1, and 3 inputs O
8 via R1501, 1502, 4 input OR1503
1 (
"H" level), 0 ("L" level) is input to D3 to D7, and the data of D0 to D7 is 8 bits by the PS signal sent via the signal line PS with the timing shown in FIG. Loaded into shift register 1509. Next, a corrected image dot signal OW4 is output to the signal line VDO by a CLKIN signal as shown in FIG. 16, which is sent from the signal line CKIN via the inverter 1514.

FIG. 16 shows the two-input AND406A~ of FIG.
8 signal lines L1, L2, R1, R2, U from 406H
A timing chart of each corrected image dot signal for data sent via P1, UP2, DN1, and DN2 is shown. In FIG. 16, OW1 is eight signal lines L1
, L2, R1, R2, UP1, UP2, DN1, DN2
The output signal is shown when all the data sent through is 0 and the image data D4 to be corrected located in the center of the sample window shown in FIG. 23 is 1, that is, no correction is performed at all. For OW2, the data on signal line L1 is 1
OW3 is the output signal corresponding to when the data on signal line L2 is 1, OW4 is the output signal corresponding to signal line R1
OW5 is an output signal corresponding to when the data on signal line R2 is 1, OW6 is an output signal corresponding to when the data on signal line R2 is 1.
indicates an output signal corresponding to the case where the data on the signal line UP2 or the signal line DN2 is 1, OW7 indicates an output signal corresponding to the case where the data on the signal line UP1 or the signal line DN1 is 1, and multiple corrected image dot signals are If they are output at the same time, the logical sum of those outputs is taken and output.

FIG. 17 shows an image diagram of image data for the corrected image dot signal. 1701 is a black dot image, 1702 is a white dot image, and 1703 is a black dot image.
1705 corresponds to the case where the data on the signal line L2 is 1, and the right 1/3 of the black dot is deleted, and 1705 corresponds to the case where the data on the signal line R2 is 1, and the left 1/3 of the black dot is deleted.
The dot 1706 corresponds to the case where the data of the signal line R1 is 1, and the dot 1704 corresponds to the case where the right 1/3 dot is added to the white dot, and the data 1704 corresponds to the case where the data of the signal line L1 is 1.
Corresponding to the case, 1707 corresponds to the case where the left 1/3 dot is added to the white dot, and 1708 corresponds to the case where the data of the signal line UP2 is 1, and the lower 1/3 dot of the black dot is deleted. corresponds to the case where the data of the signal line DN2 is 1, and the upper 1/3 dot of the black dot is deleted, 1
709 corresponds to the case where the data of the signal line UP1 is 1, and is a dot with an upper 1/3 dot added to the white dot, 1710
corresponds to the case where the data on the signal line DN1 is 1, and indicates a dot in which a lower ⅓ dot is added to a white dot. These replacement data are selected based on the edge of the center dot D4 of the sample window shown in FIG. 23 and the surrounding environment.

In this embodiment, dots are added and deleted in the horizontal direction as shown in 1703 to 1706 in FIG. 17 by controlling the current application time of the laser output. However, the controls shown in 1707 to 1710 require changing the laser irradiation position and are difficult to implement. Therefore, for 1707 and 1708, 1
As shown in 711, this is achieved by reducing the diameter of the dot by reducing the current application time compared to normal dots. Similarly, regarding 1709 and 1710, it is necessary to add minute dots at the top or bottom of the dot position, but in this example, this is handled by forming dots with a short current application time as shown at 1712. There is.

In this embodiment, with the above-described configuration and series of operations, FIGS. 31(a) and 32(a) are as shown in FIG.
1(b) and Fig. 32(b), and in Fig. 32(b), the periphery becomes ambiguous due to the printing resolution and the visual resolution, so a very smooth line with no visible breaks appears. That is, the image data can be corrected as shown in FIG. 32(c).

Here, in the case where the environment detection means 108 is not provided, the pattern as shown in FIG. 33(a) is
Correction is made as shown in b), but if the temperature around the photosensitive drum is lower than the reference temperature, the sensitivity of the photosensitive drum may decrease and the dots may become thinner, resulting in a break in some of the diagonal lines. Therefore, if the ambient temperature is lower than the reference temperature, the threshold value for selecting the type of correction is changed based on the calculation result, so that even if the dots become thinner, no breaks will occur as shown in Figure 33(c). Corrections will be made.

[0062]

[Effects of the Invention] As described above, the image forming apparatus of the present invention has
A part of the area where an image composed of dots in an orthogonal matrix is written is set as a window, and a predetermined dot in the window and a predetermined position are set by a window setting means that can move this setting position within the area. a first edge detection means for detecting a difference in image data between the dot and a dot adjacent to the dot and a direction of the difference; and a first edge detection means for detecting a first edge between dots adjacent to each other other than a predetermined dot within the window. a second edge detection means for detecting a difference in the image data detected by the means and an edge having a difference in the same direction as the direction of the difference; and an edge corresponding to the edge data output from the second edge detection means; weighting means for setting a predetermined value according to the position of the edge detected by the first edge detection means; calculation means for obtaining the sum of the predetermined values set by the weighting means; an environmental condition detecting means for generating a signal for changing a threshold value for determining the type of correction for a given dot according to the environmental condition based on the value obtained by the calculating means; and the value obtained by the calculating means and the environmental condition. Information obtained by the detection means and a signal generating means for generating a signal that changes the size of the predetermined dot according to the information obtained by the detection means, the predetermined dot in the sample window and the dot adjacent to the predetermined dot can be detected. A predetermined value is set according to the difference in image data between the It is possible to make corrections by changing the threshold value that determines the value depending on the environmental conditions around the device and changing the size of the predetermined dots based on these results. There is no need to prepare separate template patterns for the sample window, and there is no need for a comparison circuit for the matching network means that compares the sample window pattern with the template pattern, which simplifies the circuit configuration and reduces costs. , any pattern and changes in the surrounding environment can be compensated reliably and accurately, and high-quality printing can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a compensation circuit that constitutes a controller section of an image forming apparatus in an embodiment of the present invention.

FIG. 2 is a configuration diagram of edge detection means, edge data selection means, weighting means, logical operation means, environment detection means, and correction control means of the image forming apparatus in one embodiment.

FIG. 3 is a circuit diagram of an environment detection circuit of an image forming apparatus in one embodiment.

FIG. 4 is a circuit diagram of a vertical edge detection circuit of an image forming apparatus in one embodiment.

FIG. 5 is a circuit diagram of a vertical edge data selection circuit of an image forming apparatus in one embodiment.

FIG. 6 is a circuit diagram of a horizontal edge detection circuit of an image forming apparatus in one embodiment.

FIG. 7 is a circuit diagram of a horizontal edge data selection circuit of an image forming apparatus in one embodiment.

FIG. 8 is a circuit diagram of a vertical edge data weighting circuit and a horizontal edge data weighting circuit of an image forming apparatus in one embodiment.

FIG. 9 is a circuit diagram of a vertical edge data weighting circuit and a horizontal edge data weighting circuit of an image forming apparatus in one embodiment.

FIG. 10 is a circuit diagram of an addition circuit of an image forming apparatus in one embodiment.

FIG. 11 is a circuit diagram of a signal generating means of an image forming apparatus in one embodiment.

FIG. 12(a) shows that the vertical edge data weighting circuit of the image forming apparatus in one embodiment classifies the right edge of the image bitmap image data to be corrected located at the center of the sample window; , the state diagram (b) of the vertical edge data grouped according to the position relative to the right edge of the image bitmap image data to be corrected is determined by the vertical edge data weighting circuit of the image forming apparatus in one embodiment. A state diagram of vertical edge data classified according to the type of the left edge of the image bitmap image data to be corrected located at and grouped according to the position relative to the left edge of the image bitmap image data to be corrected.

FIG. 13(a) shows that the horizontal edge data weighting circuit of the image forming apparatus in one embodiment classifies the lower edge of the image bitmap image data to be corrected located at the center of the sample window; , the state diagram (b) of the horizontal edge data grouped according to the position with respect to the lower edge of the image bitmap image data to be corrected is determined by the horizontal edge data weighting circuit of the image forming apparatus in one embodiment. A state diagram of horizontal edge data that is classified according to the type of edge below the image bitmap image data to be corrected located in the image bitmap image data to be corrected and grouped according to the position with respect to the lower edge of the image bitmap image data to be corrected.

FIG. 14 (a) is a pattern diagram of image data of an image forming apparatus in one embodiment; (b) is a pattern diagram of image data of an image forming apparatus in one embodiment;

FIG. 15 (a) is a pattern diagram of image data of an image forming apparatus in one embodiment; (b) is a pattern diagram of image data of an image forming apparatus in one embodiment;

FIG. 16 is a timing chart of signal generating means of an image forming apparatus in one embodiment.

FIG. 17 is an image diagram of image data for corrected image dot signals of an image forming apparatus in one embodiment.

FIG. 18 is a schematic configuration diagram of a mechanical section of a conventional image forming apparatus.

FIG. 19 is a perspective view of the main parts of a mechanical section of a conventional image forming apparatus.

FIG. 20 is an explanatory diagram of the operation of a mechanical section of a conventional image forming apparatus.

FIG. 21 is a block diagram of a controller section of a conventional image forming apparatus.

[Fig. 22] Block diagram of a correction circuit of a conventional image forming apparatus

[Fig. 23] Sample window diagram of a sample window circuit of a conventional image forming apparatus

FIG. 24 is an example diagram of a plurality of predetermined template patterns of a conventional image forming apparatus.

FIG. 25 is a block diagram of temporary storage means of a conventional image forming apparatus.

FIG. 26 is a circuit diagram of a memory control circuit of a conventional image forming apparatus.

FIG. 27 is a circuit diagram of a memory circuit of a conventional image forming apparatus.

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FIG. 28: Circuit diagram of a sample window circuit of a conventional image forming apparatus

FIG. 29 is a circuit diagram of a comparison circuit that is part of a matching network means of a conventional image forming apparatus.

FIG. 30: Compensated image dot signal output from signal generation means of a conventional image forming apparatus.

FIG. 31 (a) is a dot diagram of image bitmap image data before compensation of a conventional image forming apparatus; (b) is a dot diagram of image bitmap image data after compensation of a conventional image forming apparatus;

FIG. 32(a) is a dot diagram of image bitmap image data before compensation of a conventional image forming apparatus; (b) is a dot diagram of image bitmap image data after compensation of an image forming apparatus in one embodiment; ) is a dot diagram of the corrected image bitmap image data of a conventional image forming device.

FIG. 33 (a) is a dot diagram of image bitmap image data before correction of a conventional image forming apparatus; (b) is a dot diagram of image bitmap image data after correction of a conventional image forming apparatus; Dot diagram of image bitmap image data after correction of image forming apparatus in one embodiment

[Explanation of symbols]

101 Temporary storage means 102 Edge detection means 103 Weighting means 104 Logical operation means 106 Signal generation means 108 Environmental detection means

Claims (3)

[Claims] 1. A window setting means capable of setting a part of an area in which an image composed of dots of an orthogonal matrix is written as a window and moving the set position within the area; and the window setting means. a first edge detection means for detecting a difference in image data between a predetermined dot and a dot adjacent to the predetermined dot in the window set by the method, and a direction of the difference; a second edge detection means for detecting a difference between adjacent dots other than dots in the image data detected by the first edge detection means and an edge having a difference in the same direction as the direction of the difference; weighting means for setting a predetermined value according to the position of the edge corresponding to the edge data output from the second edge detection means relative to the position of the edge detected by the first edge detection means; and weighting means set by the weighting means. a calculation means for calculating the sum of the predetermined values, and a threshold value for detecting the environmental condition around the device and determining the type of correction for the predetermined dot based on the value obtained by the calculation means according to the environmental condition. environmental condition detection means for generating a signal that changes the size of the predetermined dot according to the value obtained by the calculation means and the information obtained by the environmental condition detection means; An image forming apparatus comprising: means. 2. The image forming apparatus according to claim 1, wherein the environmental state detection means detects the temperature around the apparatus. 3. The image forming apparatus according to claim 1, wherein the environmental state detection means detects humidity around the apparatus.