JP2532762B2 - Image forming device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus such as a laser printer which forms image data forming an orthogonal matrix in the row and column directions by horizontal and vertical scanning.

[0002]

2. Description of the Related Art In recent years, laser printers have come to be used as output devices for computers and the like. One of the features of this laser printer is that it has a high resolution, but it is desired that a smooth outer shape can be obtained above the resolution depending on the type of character. Therefore, various smoothing techniques have been devised.

An image forming apparatus will be described below by taking a laser beam printer as an example. 15 is a schematic configuration diagram of a mechanical portion of the image forming apparatus, FIG. 16 is a perspective view of a main portion of the mechanical portion of the image forming apparatus, and FIG. 17 is an operation explanatory view of the mechanical portion of the image forming apparatus. In FIG. 15 and FIG. 16, 1901 is a photosensitive drum driven in the direction A by a motor (not shown), and this photosensitive drum 1901 is composed of a metal cylinder coated with a layer of an organic photoconductive material. It continues to rotate during printing, and rotates several times every time one page is printed. The photosensitive drum 1901 is physically and electrically cleaned by a cleaning unit 1916 before an image is formed on a portion to be printed.
A pretreatment for holding an electrostatic latent image is performed on the drum surface 2001 of the above. First, the physical cleaning is performed by scraping off the toner remaining on the drum in the previous cycle from the photosensitive drum 1901 with the rubber cleaning blade 1902, and the scraped toner is put in the waste toner (see FIG. (Not shown). The electrostatic cleaning is performed by irradiating the layer of the organic photoconductive material of the photosensitive drum 1901 with light with the static elimination lamp 1903 to remove the light.
01 by neutralizing the charge remaining in the previous cycle. Next, the cleaned drum surface 200
1 is that when the photosensitive drum 1901 rotates and the layer of the organic photoconductive material of the photosensitive drum 1901 passes through the ionized region generated by the charge corona generator 1904, a negative charge is generated from the corona generator 1904. It moves to the drum surface 2001 and is uniformly charged by the negative charge of 600 volts. According to the image, the laser beam 1 is applied to the drum surface 2001 uniformly charged by the negative charge.
By irradiating with the focus of 905, the surface potential of the irradiated area is discharged and an electrostatic latent image is formed.

The above operation will be described in more detail with reference to FIG. The semiconductor laser 2002 has a laser beam 1905.
Occurs when the power is turned on and stops when the power is turned off. A laser beam 1905 generated by the semiconductor laser 2002 is collimated by a collimator lens 2003 and focused on a scanning mirror 2005 by a cylindrical lens 2004. The scanning mirror 2005 is a rotary polygonal mirror having six surfaces and is rotated at a constant speed by a scanner motor 2006. The laser beam 1905 is scanned in the direction of arrow B in FIG. 17 by the rotation of the scanning mirror 2005, and the focus of this scanned laser beam 1905 is the converging lens 2.
007 and mirror 2008, drum surface 2001
Is adapted to. The laser beam 1905 scans the drum surface 2001 in the direction of arrow B, the photosensitive drum 1901 rotates in the direction of arrow A in FIG. 17, and the drum surface 2001 is covered with the raster image.

Here, the speed of the main motor (not shown) for rotating the photosensitive drum 1901 is set to the laser beam 190.
1/300 every time 5 scans over drum surface 2001
The laser beam 1905 generated by the semiconductor laser 2002 is synchronized so that the drum surface 2001 moves by inch, and the line 21 in FIG. 17 is changed according to the speed of the scanner motor 2006 that rotates the scanning mirror 2005.
Modulation is applied so that a dot of light hits every 1/300 inch in the direction along 01. As a result, a resolution of 300 dots × 300 dots per inch (dpi) can be obtained.

At the start of each scan, the laser beam 1905 is reflected by the beam detection mirror 2012 and sent to the optical fiber 2009 before reaching the photosensitive drum 1901.
This instantaneous pulse of light is sent to the controller unit 2010 by the optical fiber 2009, converted into an electric signal, and used for synchronizing the output of data relating to scanning with other data, or controlling other printers. , And test functions.

Laser beam 1 on photosensitive drum 1901
After irradiation of 905, an invisible electrostatic latent image is formed on the drum surface 2001.

That is, the portion exposed by the laser beam 1905 has a negative potential of about 100 V due to discharge, and the drum surface 2001 not exposed by the irradiation of the laser beam 1905 has a negative potential of 600 V. are doing.

In the developing section 1917 of FIG. 15, toner particles 1906 as a developer are attached to the electrostatic latent image formed on the drum surface 2001. This toner particle 1906
Is a powdery substance made of black synthetic resin combined with iron particles, and the iron particles constituting the toner particles 1906 are sucked together with the synthetic resin constituting the toner particles 1906 by the metal rotating cylinder 1907 having a permanent magnet. It The synthetic resin forming the toner particles 1906 is a rotary cylinder 1907 connected to a negative DC power source (not shown).
A negative surface charge is obtained by being rubbed against. The electrostatic charge obtained by the toner particles 1906 is such that the toner particles 1906 adhere to the area of the drum surface 2001 exposed by the laser beam 1905, but repel from the area not exposed.

At the transfer portion 1908, the drum surface 2001
The toner image formed above is transferred to the print paper 1909. When this transfer is performed, the print paper 1909 advances at the same speed as the drum surface 2001 and moves on the drum surface 2
Touch 001. The corona assembly 1910 applies a positive charge from the opposite side of the print paper 1909 from the side of the photosensitive drum 1901, and separates the negatively charged toner particles 1906 from the drum surface 2001 and makes them adhere to the print paper 1909. The electrostatic charge remover 1911 includes a drum surface 2001 having a negative charge and a print paper 190 having a positive charge.
9 to prevent the print paper 1909 from winding around the photosensitive drum 1901. The print paper 1909 to which the toner particles 1906 are attached is the transfer unit 190.
8 to the fixing unit 1912, the photosensitive drum 1901
Rotates and the cleaning unit 1916 performs pretreatment for holding the next electrostatic latent image.

In the fixing unit 1912, the toner particles 1906 are melted and pressed against the print paper 1909 by heat and pressure, and the toner image is fixed on the print paper 1909. The fixing portion 1912 is provided in contact with a non-adhesive heating roller (fusing roller) 1914 that is internally heated by a high-intensity lamp 1913, and is provided in contact with the heating roller 1914. The pressure roller 1915 is formed of a soft member having a large contact area with the heat roller 1914. The surface of the print paper 1909 to which the toner particles 1906 are attached is heated between the heat roller 1914 and the pressure roller 1915. It is configured to pass on the side. When the print paper 1909 passes between the heating roller 1914 and the pressure roller 1915, the print paper 1
Toner particles 1906 attached to 909 melt and are pressed into the fibers of the paper.

The controller unit 2010 shown in FIG.
A central processing unit (hereinafter, abbreviated as CPU) and a read-only memory (hereinafter, ROM) in which a dot pattern of a desired character set, that is, a bitmap image is stored.
Is abbreviated. ), A ROM cartridge in which data of an added bitmap image is stored, and a readable / writable memory (hereinafter, abbreviated as DRAM) that stores coded image data or the like input from an external device such as a personal computer. ), A block for controlling the printer engine, etc., and converts print data sent from an external device or the like into image bitmap image data, and further drives this laser image driving unit 2011 with this image bitmap image data. The image dot signal is output to the laser drive unit 2011 in serial. In the laser driving unit 2011, the controller unit 2010
Semiconductor laser 2 by the image dot signal sent from
002 to drive the laser beam to modulate the drum surface 20
01 is exposed.

FIG. 18 is a block diagram of the controller unit 2010 of the image forming apparatus of FIG. In FIG. 18, 201 is a 16-bit central processing unit (hereinafter abbreviated as CPU) that controls the operation of the controller unit 2010. 202 is a ROM controller,
Program data to be executed by the CPU 201 stored in the program ROM 203, bitmap data of character fonts stored in the font ROM 204, font card 205, and font card 20.
Bit map data of the optional character font stored in 6 is input via the data bus 207 according to the address information from the CPU 201, and the main data bus 208 is input.
Output to. This font card 205 and 206
Is a connector-in type ROM card format. Two
Reference numeral 09 denotes a printer engine section that includes a control panel (not shown) and the like, which constitutes a system relating to image print processing. An engine controller 210 controls the printer engine unit 209 according to the address information and data from the CPU 201 via the engine interface 211, reads data from the printer engine unit 209, and encodes the data from the external device 212. Image data is parallel interface 2
It is input via 13. Further, the engine controller 210 is an electric-erasable programmable ROM (hereinafter referred to as EEPRO) provided to store information such as print status and page count from the control panel of the printer engine unit 209.
It is abbreviated as M. ) 214, information is read and written according to the address information from the CPU 201. Reference numeral 215 denotes a DRAM that stores coded image data input from the external device 212, bit map data of character fonts, and other data and that can be read and written at any time. 216 is necessary for reading and writing data to the DRAM 215. This is a DRAM controller that generates DRAM address information and timing signals in accordance with the address information from the CPU 201, performs data access to the DRAM 215, arbitrates the main data bus 208, and refreshes data in the DRAM 215. Further, the DRAM controller 216
Is a video data synchronization signal (V) obtained by performing parallel-serial conversion of the image data stored in the DRAM 215 and dividing the clock from the clock generator 217 by the correction circuit 218.
CLK), and outputs it as image bit map image data to the correction circuit 218. Further, the DRAM controller 216 has a function of shifting image data in order to superimpose or offset images according to the information on the control panel of the external device 212 or the printer engine unit 209. The DRAM 2
The 15 memory areas can be expanded by the expansion DRAMs 219 and 220.

Here, the compensation circuit 218 receives the video data synchronization signal (VCLK) from the DRAM controller 216.
The image bit map image data input in synchronism with the image dot signal for driving the laser driving unit 2011 is replaced, the image dot signal is subjected to correction for improving print quality, and the corrected image dot signal after correction is applied. (VD
O) is output to the laser driving unit 2011. Due to this correction, for example, in the process of converting an analog character into a digital bitmap image, the resolution of the bitmap image is low, or the sampling rate of the desired analog image is low. To reduce deterioration and the like.

FIG. 19 is a block diagram of a compensation circuit using a matching network which constitutes a controller unit of the image forming apparatus disclosed in US Pat. No. 4,847,641. In FIG. 19, reference numeral 101 denotes a temporary storage means for temporarily storing a part of the image bitmap image data, and in order to compensate the 1-bit shape of the image bitmap image data, 7 rows × 7 in the periphery thereof. It is provided for the purpose of sampling the image bitmap image data of a column, and has a sample window circuit configured by a shift register, and the image bitmap image data is sequentially stored in the shift register configuring this sample window circuit. To be done. A sample window diagram of this sample window circuit is shown in FIG. The correction target is D4 in FIG. Reference numeral 2201 denotes matching network means for comparing whether or not the sample pattern stored in the sample window and a plurality of predetermined template patterns match, and an example of the plurality of predetermined template patterns is shown in FIG. Show. 105 is a matching network means 2201,
When the sample pattern matches one of a plurality of predetermined template patterns, it is a signal generating means for correcting the signal of the image bitmap image data to be corrected to a predetermined signal.

FIG. 22 is a block diagram of the temporary storage means 101. In FIG. 22, reference numeral 301 denotes a memory control circuit, which generates addresses necessary for reading and writing data to the memory and other control signals. Three
A memory circuit 02 is a high-speed static RAM (hereinafter, S
It is abbreviated as RAM. ), And reading of a video signal (VDIN) which is image bitmap image data composed of flip-flops and converted into serial data,
Writing is performed by the address output from the memory control circuit 301 and other control signals.
Reference numeral 303 is a sample window circuit configured by a shift register that stores the SRAM data read from the memory circuit 302 and outputs a sample pattern.

FIG. 23 is a circuit diagram of the memory control circuit 301, FIG. 24 is a circuit diagram of the memory circuit 302, FIG. 25 is a circuit diagram of the sample window circuit 303, and FIG. 26 is a comparison circuit which is a part of the matching network means 2201. It is a circuit diagram. In FIG. 23, 2401 to 2403
24 is a 4-bit synchronous counter, 2501 is an SRAM, 2502 is an 8-bit latch, 2503 is an inverter, 2601 to 2607 are 8-bit shift registers in FIG. 25, and 2803 to 284 in FIG.
0 is a 2-input exclusive OR (hereinafter abbreviated as Ex-OR), 2801 is a multi-input NAND (hereinafter NAN).
It is abbreviated as D. ) And 2802 are ORs (hereinafter abbreviated as OR).

The operation of the compensating circuit constituting the controller section of the image forming apparatus using the matching network configured as described above will be described below. In FIG. 24, a video signal (VDIN), which is image bit map image data sent via a video signal (VDIN) line, is a video data synchronization signal (VCLK).
According to the address SRA0 to SRA11 input to D0 of the 8-bit latch 2502, latched at the falling edge of the video data synchronization signal (VCLK) and input to A0 to A11 of the SRAM 2501, the SRA
It is stored in IO0 of M2501. This address SRA
0 to SRA11 are 4-bit synchronous counters 240 of FIG.
1 to 2403 are video data synchronization signals (VCLK) and are 0
It is obtained by counting up from (H). Similarly, the next video signal (VDIN) is incremented in address at the rising edge of the video data synchronization signal (VCLK) and stored in IO0 of the SRAM 2501. By this series of operations, one line of the main scanning of the image bit map image data is IO0 of the SRAM 2501.
Stored in.

The one line corresponds to the IO of the SRAM 2501.
When stored in 0, the 4-bit synchronous counter 240 of FIG.
1-2403 are reset by the main scanning reference signal (NLSYNC), and the video signal (VDIN) which is the image bitmap image data of the second line is an 8-bit latch 2502 according to the video data synchronization signal (VCLK).
Data of the first line stored in IO0 of the SRAM 2501 are sequentially read from address 0 (H), input to D1 of the 8-bit latch 2502, latched respectively, and input to D0 of the 8-bit latch 2502. Data is the address 0 (H) of IO0 of SRAM 2501
Then, the data input to D1 of the 8-bit latch 2502 is stored in the address 0 (H) of IO1 of the SRAM 2501.

By repeating the above operation, the SRAM
Image bit map image data is input to IO0 to IO6 of 2501 on a line-by-line basis. At the same time when this operation is performed, the output of the 8-bit latch 2502 is an 8-bit shift register 2601 forming the sample window circuit shown in FIG. .. to 2607, the 8-bit shift registers 2602 to 2607 shift the input data according to the video data synchronization signal (VCLK) to generate a video signal (VD) which is image bitmap image data.
The data corresponding to (IN) shown in FIG. 20 is stored. The stored sample pattern data and the predetermined template pattern data shown in FIG. 21 are input to Ex-ORs 2803 to 2840 of the comparison circuit of the matching network means 2201 shown in FIG. 26, respectively. The ORs 2803 to 2840 output the L level to the multi-input NAND 2801 when the input data match and the H level to the multi-input NAN if they do not match.
D2801 is L from Ex-OR2803 to 2840
When the level is output, the H level is output to the signal generating means 105 shown in FIG. 19 through the multi-input OR2802.

In the signal generation means 105 shown in FIG. 19, the template pattern used when the multi-input NAND 2801 outputs the H signal through the multi-input OR 2802, which is the image bit map image data signal to be corrected by the H level. Is replaced with the adjusted image dot signal.

Here, the signal generating means 105 shown in FIG.
FIG. 27 shows the corrected image dot signal output from the device. X
Signal, Y signal, Z signal, and W signal are multi-input NAN
About 1/3 before one dot, about 2/3 after one dot, about 2/3 before, about 1/3 after 1 dot corresponding to the template pattern used when the D2801 outputs the H signal via the multi-input OR2802.
It is a corrected image dot signal that outputs only 3.

By the above series of operations, FIG.
As shown in FIGS. 28B and 29C, the image bitmap image data shown in FIGS. 28A and 29A is one of the image bitmap image data to be corrected. By replacing the bit signal with a compensated image dot signal that outputs only 1/3, 2/3 above and below or above or below a normal dot, a step such as a diagonal line is smoothed.

[0024]

However, in the above-mentioned configuration, in order to perform the correction of the image bitmap image data, the template patterns are separately prepared for all the image bitmap image data that need the adjustment. The number of comparison circuits of the matching network means for comparing the sample pattern and the template pattern is increased, the circuit configuration is complicated, and the cost is increased. Even if it is difficult to prepare the pattern and the image bitmap image data needs to be corrected, there is a problem that the correction may not be performed because there is no template.

[0025]

Since the present invention SUMMARY OF] is to solve the above problems, some of the images constructed by the dot straight <br/> exchange matrix sent from outside as image data as a window set, corresponding to the dot adjoining the set position to the image data <br/> this predetermined dot corresponding to a predetermined dot in the window set by the window setting means capable of moving in the image Edge detection means for detecting a difference from the image data and the direction of the difference, and a difference between the image data corresponding to adjacent dots other than a predetermined dot in the window, and detecting the difference between the adjacent dots. edges exist having the same direction of the difference between the difference image data edge detection means detects
If present , weighting means for setting a predetermined value according to the position of this edge with respect to the edge position of a predetermined dot, calculation means for obtaining the sum of the predetermined values set by the weighting means, and calculation means A signal generating means for generating a signal for changing a predetermined dot size according to the obtained value, and a signal generating means for generating a signal according to the signal generated by the signal generating means.
And a recording means for recording by changing the size of the unit .

[0026]

DETAILED DESCRIPTION OF THE INVENTION The present invention with the configuration described above, the difference between the image data corresponding to the dot adjacent to the image data and the predetermined dot corresponding to a predetermined dot in the window guiding image corresponding to the dots adjacent to each other Compensation can be performed by detecting a difference in data and changing the size of a predetermined dot based on these detection results.

[0027]

EXAMPLE An image forming apparatus according to an example of the present invention will be described below. Here, the mechanical section of the image forming apparatus and the controller section other than the compensating circuit of the image forming apparatus are the same as the configuration shown in the above-mentioned conventional technique, and therefore description thereof is omitted.

FIG. 1 is a block diagram of a compensation circuit which constitutes a controller section of an image forming apparatus according to an embodiment of the present invention. In FIG. 1, 101 is a temporary storage means, 301
Is a memory control circuit, 302 is a memory circuit, 30
Reference numeral 3 is a sample window circuit, which has the same configuration as that of the above-mentioned conventional technique, and therefore detailed description thereof will be omitted.
Reference numeral 102 denotes an edge detecting means for detecting an edge from the image bit map image data in the sample window shown in FIG. 20. Here, the edge detection is an attribute of 1-bit image data of 1 dot at a predetermined position in the sample window. (0 or 1) is different from the attribute of the 1-bit data of the dots on the top, bottom, left, and right of this dot (for example, 1 dot of image data at a predetermined position is adjacent to the dot on the top, bottom, left, and right with respect to 0). If the image data of 1 is 1 and the image data of 1 dot at a predetermined position is 1
However, the image data of the dots that are vertically, horizontally and adjacently adjacent to
If there is an edge, 1 is output, and if there is no edge, 0 is output. Reference numeral 103 denotes a plurality of pieces of edge data detected by the edge detecting means 102, and the types of edge edges on the top, bottom, left, and right of the dot corresponding to the image data D4 to be corrected located in the center of the sample window (up and down with respect to the image data D4. Depending on whether the adjacent data on the left and right are 0 to 1 or 1 to 0, and whether the edge direction is upward, downward, rightward, leftward) Along with classifying
Weighting means for collecting the dots corresponding to the image data D4 according to the positions of the upper, lower, left, and right edges, and 104 for each of the plurality of edge data collected by the weighting means 103, for the upper, lower, left, and right edges of the dots corresponding to the image data D4. A logical operation unit that generates and outputs data for correction by multiplying a predetermined numerical value according to the position and performs a logical operation. Reference numeral 105 is an object of correction according to the correction data output from the logical operation unit 104. It is a signal generating means for replacing the signal of the image data D4 with a corrected image dot signal for driving the laser driving section 2011 shown in FIG.

FIG. 2 shows a simple circuit diagram of the edge detecting means 102, the weighting means 103, and the logical operation means 104.
In FIG. 2, 401 is a vertical edge detection circuit that detects whether or not there is an edge between adjacent bits in the main scanning direction of the image bitmap image data in the sample window shown in FIG. 20, and 402 is adjacent in the sub scanning direction. In the horizontal edge detection circuit that detects whether or not there is an edge between bits, the vertical edge detection circuit 401 and the horizontal edge detection circuit 402 constitute the edge detection means 102 shown in FIG. Reference numeral 403A denotes a plurality of pieces of edge data detected by the vertical edge detection circuit 401, which are present between adjacent bits in the main scanning direction, and are arranged on the left and right sides of the image data D4 to be corrected located in the center of the sample window shown in FIG. Type of edge (whether data adjacent to the left and right of the image data D4 is 0 to 1 or 1 to 0,
And the direction of the edge is the right direction or the left direction), and the image data D4 is grouped according to the positions with respect to the left and right edges, and when the image data D4 to be corrected is 0, the signal line ADD Vertical edge data weighting circuit that outputs 1 to the signal line DEL when 1, and a plurality of edge data detected between horizontal bits in the sub-scanning direction detected by the horizontal edge detection circuit 401. Is the type of the upper and lower edges of the image data D4 to be corrected located in the center of the sample window shown in FIG. 20 (when the vertically adjacent data is 0 to 1 or 1 to 0 with respect to the image data D4, Existing and whether the edge direction is upward or downward), and summarizes according to the positions of the image data D4 with respect to the upper and lower edges. At the same time, the horizontal edge data weighting circuit outputs 1 to the signal line ADD when the image data D4 to be corrected is 0 and outputs 1 to the signal line DEL when the image data D4 is 0. The weighting circuit 403B constitutes the weighting means 103 shown in FIG. 404A, 404
B, 404C, and 404D denote the upper, lower, left, and right of the image data D4 to be corrected, which is located in the center of the sample window shown in FIG. It has a multiplication function that multiplies a predetermined numerical value according to the position with respect to an edge, multiplies each of a plurality of edge data by a predetermined numerical value, performs addition, and outputs 1 as data when the addition result is 8 or more. Adder circuits 405 to 412 are adder circuits 404A and 404.
Two-input AND which takes a logical product of the data output from B, 404C and 404D and the data sent from the vertical edge data weighting circuit 403A and the horizontal edge data weighting circuit 403B via the signal lines ADD and DEL.
Then, these adder circuits 404A, 404B, 404C,
404D and 2-input ANDs 405-412 and FIG.
The logical operation means 104 shown in FIG.

FIG. 3 is a circuit diagram of the vertical edge detection circuit 401, FIG. 4 is a circuit diagram of the horizontal edge detection circuit 402, and FIG.
FIG. 6 is a circuit diagram of the vertical edge data weighting circuit 403A, and the horizontal edge data weighting circuit 403B is the same circuit diagram as FIG. 5 and FIG. FIG. 7 shows addition circuits 404A and 40
4B, 404C and 404D, and FIG. 8 is a circuit diagram of the signal generating means 305 shown in FIG.

In FIG. 3, reference numerals 501 to 528 denote two inputs A.
ND, 529 to 549 are inverters, 7 in FIG.
01 to 728 are 2-input ANDs, 729 to 749 are inverters, and in FIG. 5, 1001 to 1012 are AND-O.
R inverters, 1013 to 1024 are inverters, 10
25 and 1026 are buffers, 1027 is a 2-input OR, and in FIG. 6, 1101 to 1112 are AND-OR inverters, 1113 to 1124 are inverters, 1125 and 1125.
126 is a buffer, 1127 to 1129 are 2-input ORs,
7, 1301 to 1309 are 3-input 1-bit full adders, 1310 and 1311 are 2-input ORs, and in FIG. 8, 1501, 1502, 1507 and 1508 are 3-input ORs, 1504 and 1505 are 5-input ORs, 1503,
1506 is a 4-input OR, 1509 is an 8-bit parallel load serial output shift register (hereinafter abbreviated as 8-bit shift register), 1510 is a 6-input NOR,
1511 is a 2-input AND, 1512 is an inverter, 15
Reference numerals 13 and 1514 are 2-input ORs.

The operation of the compensating circuit that constitutes the controller section of the image forming apparatus having the above-described configuration will be described below.

In the vertical edge detection circuit of FIG. 3, image data A3 to A5, B3 to B5, C3 to C5, D3 to D sent from the sample window circuit 303 shown in FIG.
5, E3 to E5, F3 to F5, and G3 to G5 are logically operated by the inverters 529 to 549 and the 2-input ANDs 501 to 528, so that 3 from the A line to the G line of the sample window shown in FIG. Rows 4 and 4, and 4
It is detected whether or not the image data in the fifth and fifth columns changes from 0 to 1 or 1 to 0 (hereinafter referred to as white to black or black to white) in the main scanning direction, and as edge data. Output. This edge data is 1 for the signal line V1 when the third column of the A-th row is white and the fourth column is black, and is the signal when the third column of the B-th row is white and the fourth column is black. 1 on line V2
Similarly, in the case of the Cth row to the Gth row, 1 is output to each of the signal lines V3 to V7. Further, in each of the rows A to G, when the third column is black and the fourth column is white, the signal lines NV1 to NV7 are respectively set to 1, and the A to G rows are respectively set. If the 4th column is white and the 5th column is black, the signal lines VV1 to VV7 are set to 1 respectively, and the 4th column is black and the 5th column is set to each of the rows A to G. Is white, 1 is output to each of the signal lines NVV1 to NVV7.

In the horizontal edge detection circuit of FIG. 4, the image data C1 to C7, D1 to D7 and E1 to E7 sent from the sample window circuit 303 shown in FIG. 1 are converted into inverters 729 to 749 and 2-input ANDs 701 to 728. 20 by performing a logical operation by using the C window, the C row, the D row, and the D row from the first column to the seventh column of the sample window shown in FIG.
It is detected whether the image data of the lines E and E changes from 0 to 1 or from 1 to 0 in the sub-scanning direction, and output as edge data. This edge data is from the first column to 7
When the C-th row is white and the D-th row is black in each of the columns up to the first column, the signal lines H1 to H7 are set to 1 and the C-th row is set in each of the first to seventh columns. When black and the D-th row is white, the signal lines NH1 to NH7 are each set to 1 and when the D-th row is white and the E-th row is black in each of the first to seventh columns, a signal is output. 1 each on lines HH1 to HH7
If the Dth row is black and the Eth row is white in each of the first to seventh columns, the signal lines NHH1 to NHH
1 is output to 7 respectively.

In the vertical edge data weighting circuit of FIGS. 5 and 6, the signal lines A1 to A7, NA1 to NA7, B1 to B are used.
7, NB1 to NB7 to the signal lines V1 to V7, NV1 to NV7, VV1 to V7 from the vertical edge detection circuit of FIG.
Vertical edge data sent via V7 and NVV1 to NVV7 is converted into AND-OR inverter 100 in FIG.
1 to 1012, inverters 1013 to 1024, buffers 1025 and 1026, and 2-input OR 1027 in FIG. 6, AND-OR inverters 1101 to 1112 and inverters 1113 to 11
24, buffers 1125, 1126, and 2-input OR
With the data select block consisting of 1127, FIG.
The types of edges on the left and right of the image data D4 to be adjusted located in the center of the sample window shown in (1) (whether white to black, black to white, and the edge direction is rightward or leftward). In the vertical edge data weighting circuit of FIG. 5, the edge of the same type as the left edge of the image data D4 of the sample window shown in FIG.
If it is between the third and fourth columns of the row, the signal line AX11 is 1, and if it is between the third and fourth columns of the B row, the signal line AX11. 1 for AX12, and so on for C
In the case of the rows G to G, 1 is output to each of the signal lines AX13 to AX17. Further, when the edges are present between the 4th and 5th columns from the A-th row to the C-th row, the signal lines AX21 to AX23 are each set to 1, and the edges are from the E-th row to the G-th row. If it exists between the 4th and 5th columns of, the signal lines AX25 to AX27 output 1 respectively.
Further, in the vertical edge data weighting circuit of FIG. 6 as well, similar to the vertical edge data weighting circuit of FIG. 5, with respect to the edge of the same type as the right edge of the image data D4 of the sample window shown in FIG. Signal lines BX11 to BX when present between the fourth and fifth columns from the Ath row to the Gth row of the window
1 for each of 17 and the signal line BX21 when the edge exists between the third and fourth columns from the Ath row to the Cth row.
To BX23, 1 is output to each of the signal lines BX25 to BX27 when the edge exists between the third and fourth columns from the Eth row to the Gth row. Further, in the vertical edge data weighting circuit of FIG. 6, when the image data D4 to be corrected is 0, 1 is added to the signal line ADD,
When it is 1, 1 is output to the signal line DEL.

Horizontal edge data weighting circuit 403B
Is the same circuit as the vertical edge data weighting circuit of FIGS. 5 and 6, and the description of the circuit is omitted. In the horizontal edge data weighting circuit 403B, the signal lines A1 to A7, NA1
To NA7, B1 to B7, NB1 to NB7, respectively, as shown in FIG.
Signal lines H1 to H7, NH1 to
The horizontal edge data sent via NH7, HH1 to HH7, and NHH1 to NHH7 is the image data D to be corrected which is located in the center of the sample window shown in FIG.
The upper and lower edges of 4 are classified according to the type of edge (whether white to black, black to white, and edge direction is upward or downward), and Signal lines AX11 to AX17 and AX21 to A depending on the positions of the upper and lower edges of the image data D4.
X23, AX25 to AX27, and BX11 to B
X17, BX21 to BX23, BX25 to BX27
1 is output to each.

The vertical edge data weighting circuit 403A classifies the image data D4 to be corrected in the center of the sample window shown in FIG.
9 (a) and 9 (b) show the states of vertical edge data that are grouped according to the left and right edge positions of
The horizontal edge data weighting circuit 403B classifies the image data D4 to be corrected located at the center of the sample window shown in FIG. 20 according to the types of upper and lower edges, and according to the positions of the image data D4 with respect to the upper and lower edges. The states of the horizontal edge data to be put together are shown in FIGS. 10 (a) and 10 (b). 9A and FIG.
(B), FIG. 10 (a), and FIG. 10 (b), the numbers between the bits indicate that the edge between the bits indicates the weight for the correction of the central bit D4. There is.

FIG. 9A shows the case where there is an edge between the center bit D4 and the bit D5 on the right side of the center bit D4. 1 and the left edge of the bit in the 4th column is 2
Or it will be 4. Next, in FIG. 9B, when there is an edge between the central bit D4 and the bit D3 on the left side of the central bit D4, the weights of the edges on the left side of the bits in the fourth column, which is the same column as the central bit D4, are all 1s. The right edge of the bit in the fourth column is 2 or 4. FIG. 10A shows a case where there is an edge between the central bit D4 and the bit E4 below the central bit D4, and all the weights of the lower edges of the bits of the Dth row, which is the same row as the central bit D4, are 1 And the upper edge of the bit on the D-th row becomes 2 or 4. FIG.
(B) shows a case where there is an edge between the central bit D4 and the upper bit C4, and the weights of the upper edges of the bits of the Dth row, which is the same row as the central bit D4, are all 1, and the D row The lower edge of the eye bit is 2 or 4.

In the adder circuit of FIG. 7, the signal lines VAX11 to VAX11 to
VAX17, VAX21 to VAX23, VAX25 to V
To the AX27, the signal line AX11 from the vertical edge data weighting circuit and the horizontal edge data weighting circuit of FIGS.
~ AX17, AX21 to AX23, AX25 to AX2
7, or signal lines BX11 to BX17, BX21 to BX
23, BX25 to BX27, FIG.
The edge data classified into the upper, lower, left, and right edges of the image data D4 to be corrected, which is located in the center of the sample window shown in 0, is classified according to the position of the upper, lower, left, and right edge positions of the image data D4, and three pieces of edge data are input. 1
Bit full adder 1301-1309, 2-input OR13
In the edge data shown in FIG.
9 (b), 10 (a), and 10 (b) with a weight of 1 (signal lines VAX11 to VAX17 edge data), with a weight of 2 (signal line VAX2
1, VAX22, VAX26, VAX27 edge data), with a weight of 4 (signal lines VAX23, VA
X25 edge data) are logically operated according to their respective weights, and when the result of the logical operation becomes a weight of 8 or more, the image data D4 to be corrected located at the center of the sample window shown in FIG. 1 is output to the signal line Z8 as a correction signal for correcting.

Here, the operation of the adder circuit of FIG. 7 is shown in FIG.
This will be described with reference to the pattern diagrams of the image data shown in (a), FIG. 11 (b), FIG. 12 (a), and FIG. 12 (b). FIG.
In (a), FIG. 11 (b), FIG. 12 (a), and FIG. 12 (b), the blank frame shows white dots, and the shaded frame shows black dots. In the pattern of FIG. 11A, 2 + 2 +
4 + 1 + 1 + 1 = 11, 1 in the pattern of FIG.
+ 1 + 1 + 4 + 2 = 9, 2 in the pattern of FIG.
+ 2 + 1 + 1 + 1 + 1 = 8, 1 + 1 + 1 + 4 + 2 + 2 = 11 in the pattern of FIG. 12B, and the adder circuit 40
1 is output to the signal line Z8 from each of 4A to 404D. In the 2-input ANDs 405 to 412 shown in FIG. 2, the data sent from the four adder circuits 404A, 404B, 404C, and 404D via the respective signal lines Z8, the vertical edge data weighting circuit 403A, and the horizontal edge data weighting circuit. Eight signal lines L1, L2, R1, R2, UP1 and UP are obtained by taking the logical product of each of the data and the data sent from 403B via the signal lines ADD and DEL.
2, data is output to DN1 and DN2.

The output of this data is, for example, as shown in FIG.
In this pattern, 1 is input from the adder circuit 404B via the signal line Z8, 1 is input from the vertical edge data weighting circuit 403A via the signal line ADD to the 2-input AND 407, and 1 is output to the signal line R1.

In the signal generating circuit of FIG. 8, the 2-input AN of FIG. 2 is used.
Eight signal lines L1, L2, R1 from D405-412,
Data is input via R2, UP1, UP2, DN1, and DN2, and the signal corresponding to the image data D4 to be corrected located at the center of the sample window shown in FIG. Output from the shift register 1509.

The output of this signal is, for example, as shown in FIG.
In this pattern, the data of the signal line R1 becomes 1, and 1 is input to the inputs D0 to D2 of the 8-bit shift register 1509 via the 3-input OR 1501, 1502 and 4-input OR 1503.
("H" level), 0 ("L" level) is input to D3 to D7, and the data of D0 to D7 is set to 8 by the PS signal of the timing shown in FIG. 13 which is sent via the signal line PS. It is loaded into the bit shift register 1509.
Next, the corrected image dot signal OW4 is output to the signal line VDO by the CLKIN signal as shown in FIG. 13 sent from the signal line CKIN via the inverter 1512.

FIG. 13 shows the 2-input ANDs 405-4 of FIG.
8 signal lines L1, L2, R1, R2, UP from 12
2 shows a timing chart of each of the adjusted image dot signals for the data sent via 1, UP2, DN1 and DN2. In FIG. 13, OW1 is eight signal lines L1,
The data sent via L2, R1, R2, UP1, UP2, DN1 and DN2 are all 0, and
20 shows an output signal when the image data D4 to be corrected located at the center of the sample window shown in FIG. 20 is 1, that is, when no correction is performed. OW2 is an output signal corresponding to the case where the data on the signal line L1 is 1, OW3 is an output signal corresponding to the case where the data on the signal line L2 is 1, and OW4 is an output signal corresponding to the case where the data on the signal line R1 is 1. , OW5 is an output signal corresponding to the case where the data on the signal line R2 is 1, OW6 is an output signal corresponding to the case where the data on the signal line UP1 or signal line DN1 is 1, and OW7 is the signal line UP2 or DN2.
The output signal corresponds to the case where the data of 1 is 1, and when a plurality of corrected image dot signals are simultaneously output, the logical sum of those outputs is taken and output.

FIG. 14 shows an image diagram of the image data for the adjusted image dot signal. Reference numeral 1701 denotes a black dot image, 1702 denotes a white dot image, 1703
Corresponds to the case where the data of the signal line L2 is 1 and the right 1/3 dot of the black dot is deleted, and 1705 corresponds to the case where the data of the signal line R2 is 1 to the left of the black dot 1 /
Three dots are deleted, 1706 corresponds to the case where the data of the signal line R1 is 1, and a dot in which the right ⅓ dot is added to the white dot, 1704 is 1 of the data of the signal line L1
1707 corresponds to the case where the left 1/3 dot is added to the white dot, 1707 corresponds to the case where the data of the signal line UP2 is 1, and the dot 1708 below the black dot is deleted, 1708 Corresponds to the case where the data of the signal line DN2 is 1, and the dot 1/3 dot above the black dot is deleted, 1
Reference numeral 709 corresponds to the case where the data of the signal line UP1 is 1, and is a dot in which the upper 1/3 dot is added to the white dot, 1710
Corresponds to the case where the data of the signal line DN1 is 1, and indicates a dot obtained by adding the lower 1/3 dot to the white dot. These image data are sorted by the edge relating to the central dot D4 of the sample window shown in FIG.

Table 1 shows the output conditions of the corrected image dot signal shown in FIG.

[0047]

[Table 1] In this embodiment, by controlling the current application time of the laser output, 1703 to 1706 and 171 of FIG.
3, 1714, dots are added / deleted in the horizontal direction. However, in the control shown in 1707 and 1708, it is necessary to change the irradiation position of the laser,
It is difficult to implement. Therefore, 1707 and
With respect to 1708, as indicated by 1711, the dot diameter is made smaller by making the current application time shorter than that of a normal dot. Similarly, for 1709 and 1710, it is necessary to add a minute dot above or below the dot position, but in the present embodiment, as shown by 1712, a dot with a short current application time is formed. There is.

In the present embodiment, the configuration and the series of operations as described above are applied to FIG. 28 (a) and FIG. 29 (a).
8 (b) and FIG. 29 (b). Further, in FIG. 29 (b), since the periphery is ambiguous due to the printing resolution and the visual resolution, there is a visually very smooth line without interruption. That is, the image data can be corrected as shown in FIG.

Here, in the case where the weighting means 103 of FIG. 1 is not provided, as shown in FIGS. 30 (a) and 30 (b), the edge on the opposite side of the edge of the dot to be corrected is detected, and this edge is detected. Correction will be performed according to the number of detections. That is, for the left edge of the correction target dot in FIG. 30A, an edge of the same type as the left edge of the correction target dot on the same row as the correction target dot is detected, and the detected edge number is detected. Presence / absence of the correction is determined, and for the right edge of the correction target dot in FIG. 30B, an edge of the same type as the right edge of the left correction target dot in the same row as the correction target dot is set. The presence or absence of correction is determined according to the number of detections.

For example, when the addition result is corrected by 3 or more, in the case of the image data shown in FIG. 31 (a), the 0 → 1 edge on the right side of the correction target dot causes 0 → 1 on the left side of the same column as the correction target dot. 1 + 1 + to detect only the edge of
1 = 3 Therefore, a small dot is added on the right side of the correction target dot. In the case of the image data shown in FIG. 31 (b),
Only the 1 → 0 edge on the right side of the same row as the dot to be corrected is detected by the 1 → 0 edge on the left side of the correction target dot,
Since the correction target dot is 1, the correction is not performed, and the 0 → 1 edge on the right side of the correction target dot detects only the 0 → 1 edge on the left side of the same column as the correction target dot. Therefore, 1 + 1 + 1 = 3. Delete the small dot on the right side.
As a result of the above, the image data shown in FIG. 32 (a) is corrected as shown in FIG. 32 (b), but with the correction having the weighting means 103 in the present embodiment, as shown in FIG. 32 (c), The image data can be surely smoothed.

[0051]

As described above, the image forming apparatus of the present invention is
Sets some of the dot images constituted by orthogonal matrix the sent from outside as image data as a window, set the window by the window setting means capable of moving the setting position in the image and differences and edge detection means for detecting the direction of the difference between the image data corresponding to a predetermined dot image data corresponding to the dot adjacent to the predetermined dot in the window, each other than a predetermined dot If detecting the difference of the image data corresponding to adjacent dots, edge exists with the same direction of the difference between the difference image data edge detection unit detects between dots adjacent to each other of the edges, predetermined dot The weighting means for setting a predetermined value according to the position with respect to the edge position of the Calculating means for obtaining a sum of the predetermined value, a signal generating means for generating a signal for changing the magnitude of the predetermined dot depending on the value obtained by the calculation means, the signal
Change the dot size according to the signal generated by the generator
Since the recording means for recording is provided, the image data corresponding to a predetermined dot in the sample window is not compared without comparing the sample window with the template pattern.
Data and the image data corresponding to the dots adjacent to the predetermined dot and the difference between the image data corresponding to the dots adjacent to each other are detected, and the size of the predetermined dot is detected based on these detection results. Since it is possible to perform compensation by changing, it is not necessary to separately prepare template patterns for all possible sample window patterns, and a matching network means for comparing the sample window pattern with the template pattern. Since the comparison circuit is not required, the circuit configuration is simplified, the cost can be reduced, and even if any pattern is corrected, high quality printing can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram of a compensation circuit that constitutes a controller unit of an image forming apparatus according to an embodiment of the present invention.

FIG. 2 is a simple circuit diagram of edge detection means, weighting means, and logical operation means of the image forming apparatus in one embodiment.

FIG. 3 is a circuit diagram of a vertical edge detection circuit of an image forming apparatus according to an embodiment.

FIG. 4 is a circuit diagram of a horizontal edge detection circuit of the image forming apparatus according to the embodiment.

FIG. 5 is a circuit diagram of a part of a vertical edge data weighting circuit and a horizontal edge data weighting circuit of the image forming apparatus in one embodiment.

FIG. 6 is a circuit diagram of a part of a vertical edge data weighting circuit and a horizontal edge data weighting circuit of the image forming apparatus in one embodiment.

FIG. 7 is a circuit diagram of an adder circuit of the image forming apparatus according to an embodiment.

FIG. 8 is a circuit diagram of a signal generating unit of the image forming apparatus according to an embodiment.

FIG. 9A is classified by a vertical edge data weighting circuit of the image forming apparatus according to one embodiment, according to the right edge type of the image bitmap image data to be corrected located in the center of the sample window. A state diagram of vertical edge data collected according to a position with respect to the right edge of the image bitmap image data to be corrected is shown in (b). The vertical edge data weighting circuit of the image forming apparatus in one embodiment shows the center of the sample window. A state diagram of vertical edge data classified according to the position of the left edge of the image bitmap image data to be adjusted, which is classified according to the type of the left edge of the image bitmap image data to be adjusted located at

FIG. 10A is classified by a horizontal edge data weighting circuit of the image forming apparatus in one embodiment according to the edge type under the image bitmap image data of the correction object located in the center of the sample window. The image of the horizontal edge data to be collected according to the position with respect to the lower edge of the image bitmap image data to be corrected is shown in (b) in the center of the sample window by the horizontal edge data weighting circuit of the image forming apparatus in one embodiment. A state diagram of horizontal edge data classified according to the position of the upper edge of the image bitmap image data to be corrected and classified according to the type of edge on the image bitmap image data to be corrected located in

FIG. 11A is a pattern diagram of image data of the image forming apparatus in one embodiment, and FIG. 11B is a pattern diagram of image data of the image forming apparatus in one embodiment.

FIG. 12A is a pattern diagram of image data of the image forming apparatus in one embodiment, and FIG. 12B is a pattern diagram of image data of the image forming apparatus in one embodiment.

FIG. 13 is a timing chart of the signal generating unit of the image forming apparatus according to the embodiment.

FIG. 14 is an image diagram of image data for a corrected image dot signal of the image forming apparatus according to the embodiment.

FIG. 15 is a schematic configuration diagram of a mechanical portion of a conventional image forming apparatus.

FIG. 16 is a perspective view of a main part of a mechanical section of a conventional image forming apparatus.

FIG. 17 is an operation explanatory diagram of a mechanical section of a conventional image forming apparatus.

FIG. 18 is a block diagram of a controller unit of a conventional image forming apparatus.

FIG. 19 is a block diagram of a correction circuit of a conventional image forming apparatus.

FIG. 20 is a sample window diagram of a sample window circuit of a conventional image forming apparatus.

FIG. 21 is an example of a plurality of predetermined template patterns of a conventional image forming apparatus.

FIG. 22 is a block diagram of a temporary storage unit of a conventional image forming apparatus.

FIG. 23 is a circuit diagram of a memory control circuit of a conventional image forming apparatus.

FIG. 24 is a circuit diagram of a memory circuit of a conventional image forming apparatus.

FIG. 25 is a circuit diagram of a sample window circuit of a conventional image forming apparatus.

FIG. 26 is a circuit diagram of a comparison circuit which is a part of matching network means of a conventional image forming apparatus.

FIG. 27 is a corrected image dot signal output from the signal generating means of the conventional image forming apparatus.

28A is a dot diagram of image bitmap image data before correction of a conventional image forming apparatus, and FIG. 28B is a dot diagram of image bitmap image data after correction of a conventional image forming apparatus.

29A is a dot diagram of image bitmap image data before correction of a conventional image forming apparatus, and FIG. 29B is a dot diagram of image bitmap image data after correction of the image forming apparatus in one embodiment. ) Is a dot diagram of the image bitmap image data after the correction of the conventional image forming apparatus

30A is an explanatory diagram of an edge detection position of an example of a conventional image forming apparatus, and FIG. 30B is an explanatory diagram of an edge detection position of an example of a conventional image forming apparatus.

31A is an operation explanatory diagram of an example of a conventional image forming apparatus, and FIG. 31B is an operation explanatory diagram of an example of a conventional image forming apparatus.

FIG. 32 (a) is an operation explanatory view of a conventional image forming apparatus and an image forming apparatus of the present invention. (B) is an operation explanatory view of an example of a conventional image forming apparatus. FIG. 32 (c) is an operation explanatory view of an image forming apparatus of the present invention.

[Explanation of symbols]

 101 Temporary Storage Means 102 Edge Detection Means 103 Weighting Means 104 Logical Operation Means 105 Signal Generation Means

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Tadayuki Kajiwara 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Masanobu Narasaki 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-1-139280 (JP, A)

Claims (2)

(57) [Claims] [Claim 1] Set the part of the image data images constituted by dots of <br/> orthogonal matrix which is sent from the outside as a window, can move the setting position in the image Window setting means, and a difference between image data corresponding to a predetermined dot in the window set by the window setting means and image data corresponding to a dot adjacent to the predetermined dot, and a direction of the difference. Edge detection means for detecting the difference between the image data corresponding to mutually adjacent dots other than the predetermined dot and the direction of the difference in the window, and the edge detection means detects between the dots adjacent to each other. If an edge having the same direction of the difference between the difference image data exists, the edge, with the predetermined dot Weighting means for setting a predetermined value according to the position with respect to the position, calculating means for obtaining the sum of the predetermined values set by the weighting means, and the predetermined dot of the predetermined dot according to the value obtained by the calculating means and signal generating means for generating a signal for changing the size, the size of dots in accordance with the generated signal with the signal generating means
An image forming apparatus, comprising: a recording unit that changes the height and performs recording . Wherein the weighting means, if there is an edge having the same direction of the difference between the difference image data edge detection unit detects between dots adjacent to each other a distance with respect to the edge position having the predetermined dot of the edge The image forming apparatus according to claim 1, wherein the closer the value is, the higher the value is set.