JPH04360252A - Address conversion system for virtual storage in computer - Google Patents

Abstract

PURPOSE:To improve the using efficiency of respective translation looking aside buffers(TLBs) to be used for the address conversion of a virtual storage in a computer. CONSTITUTION:This address conversion system is hierarchically provided with plural TLBs 102a to 102d and effective bit number storing registers 101a to 101d for storing the number of effective bits whose addresses are to be converted are respectively arranged correspondingly to respective hierarchies. Thereby the size of an address space, i.e., block length, to be covered by a conversion result indicated by one entry in the TLBs 102a to 102d is hierarchically varied by user specification and respective heirarchies are used in accordance with the sizes of a logical address space and a physical address space which are continuously corresponding to each other to execute address conversion. When a continued physical address space larger than a continued logical address space corresponds to the logical address space, the number of necessary TLB entries can be reduced by using entries from a hierarchy having a larger block length. Consequently a larger logical address space can be allowed to correspond to a physical address space by a TLB buffer storage device whose capacity is restricted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation method in virtual memory of a computer, and particularly to speeding up address translation using a translation looking aside buffer.

0002

2. Description of the Related Art In a virtual memory system, a translation looking aside buffer (hereinafter referred to as TLB) operates as a buffer storage device that stores the results of translation from a logical address to a physical address using an address translation table. It is used for the purpose of speeding up address translation by eliminating the translation process, but conventionally, the width of the address space that can be covered by the translation result indicated by one TLB entry, that is, the block length, is fixed. there were. The technology related to this is described in the document "Computer Architectural
ea Quantitative Approach
chap. 8” (John L. Hennessy
& David A. Patterson, Mora
An Kanfmann Publishers, In
c. ) is shown.

0003

[Problem to be solved by the invention] As mentioned above, conventionally,
Since the block length that can be covered by one TLB entry is fixed, even if a consecutive logical address space for multiple TLB entries corresponds to a similarly consecutive physical address space, the TLB for that number of entries is It is necessary to prepare an entry, which results in redundant use of TLB entries.

[0004] The present invention was made to solve the above-mentioned problems, and its purpose is to improve the efficiency of TLB use.

[0005]

[Means for Solving the Problems] The present invention provides an address translation method in a virtual memory of a computer using a TLB that stores the result of translation from a logical address to a physical address. By providing a register for storing the number of effective bits that holds the number of effective bits to be converted for each address, the width of the address space that can be covered by the conversion result indicated by one TLB entry, that is, the block length, can be hierarchically specified by the user. The address conversion is performed using each layer according to the width of the corresponding logical address space and physical address space.

[0006]

[Operation] In this invention, when a larger continuous physical address space corresponds to a continuous logical address space, the required number of TLB entries is increased by using entries from a layer with a larger block length. can be reduced. This allows a larger logical address space to be associated with a physical address space using a TLB buffer storage device with a limited capacity.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the address translation mechanism according to this embodiment. In the figure, 101a to 101d are registers for storing the number of effective bits, 102a to 102d are TLBs, and each TLB 102a to 10 is divided into four layers.
Registers 101a to 101 for storing the number of effective bits every 2d
d is provided. Here, the address is 32 bits wide, and the block length in each layer is a multiple of 4KB. Registers 101a to 101d for storing the number of effective bits are as follows:
It holds the effective number of bits to be converted into an address based on the block length of the corresponding TLB 102a to 102d, and this content can be rewritten by the user as necessary. If each register 101a to 101d is set to the effective number of bits as shown in the figure, then the top layer TLB 10
The block length of one entry in 2a is 1024KB,
The block length of one entry in the second layer TLB 102b is 128KB, the block length of one entry in the third layer TLB 102c is 16KB, and the bottom layer TLB 102
The block length of one entry in d is 4KB. FIG. 2 shows an example of a TLB entry, which includes a logical address tag corresponding to the number of upper effective bits of the logical address registers 101a to 101d, a physical address corresponding to the number of upper effective bits, and attribute information such as protect information.

Next, the address conversion method according to this embodiment will be explained based on the flowchart shown in FIG. The search shown in step 301 is performed starting from the top layer of the TLB hierarchy shown in step 300. This search is performed by comparing the upper valid bits of the logical address registers 101a to 101d with the logical address tag in each entry. If no hits are found for all entries in step 302, it is determined in step 303 whether the hierarchy is the lowest one, and if it is not the lowest, in step 304 the hierarchy is lowered by one and the search is performed again. If there is a hit in step 302, in step 305, the valid physical address in the TLB entry minus the upper valid bits of the logical address are ORed together to obtain a physical address. If there is no hit in any hierarchy and it is determined in step 303 that it is the lowest level, an exception is notified to the CPU as a page fault in step 306, and a valid TLB entry is loaded by the system program. Note that the initial data of the TLB data is also loaded by the system program.

[0009]

[Effects of the Invention] As described above, according to the present invention, TLB
By making the block length indicated by the entries hierarchically variable, the number of required TLB entries can be reduced. This allows a larger logical address space to be physically It can be associated with the address space, and it is possible to improve the usage efficiency of the TLB, and it is expected that the speed of the computer system will be increased. Further, by providing a register for storing the number of effective bits and making the block length variable hierarchically according to user specifications, the optimum block length can be set according to the logical address space and physical address space of the system.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a TLB device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a TLB entry according to an embodiment of the invention.

FIG. 3 is a flowchart illustrating an address translation algorithm according to one embodiment of the invention.

[Explanation of symbols]

101a to 101d Effective bit number storage register 1
02a-102d TLB

Claims (1)

[Claims] 1. An address translation method in virtual memory of a computer using a translation looking aside buffer that stores a translation result from a logical address to a physical address, wherein the translation looking aside buffer is provided hierarchically, and each layer By providing a register for storing the number of effective bits that holds the number of effective bits to be translated for each address, the width of the address space that can be covered by the translation result indicated by one entry of the translation looking aside buffer can be hierarchically specified by the user. An address translation method in virtual memory of a computer, characterized in that address translation is performed using each layer according to the size of a logical address space and a physical address space that continuously correspond to each other.