JPH04358422A - Receiver - Google Patents

Abstract

PURPOSE:To shorten the time required for selection of channels without increasing the cost for a superheterodyne receiver. CONSTITUTION:A local oscillator 14 outputs a local oscillation signal having a frequency corresponding to the digital data designated by a system controller 15. A date arithmetic circuit 11 computes the DC voltage data equivalent to the desired reception frequency corresponding to the designated digital data. The computed voltage data is received by a D/A converter 10, and the converter 10 gives the DC voltage corresponding to the received data to an antenna tuning circuit 2 and an RF tuning circuit 4.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superheterodyne receiver (hereinafter also referred to as a super receiver).

0002

2. Description of the Related Art FIG. 6 is a block diagram showing a schematic configuration of a conventional synthesizer type super receiver. In this super receiver, a signal received by an antenna 41 passes through an antenna tuning circuit 42 , a high frequency amplifier (hereinafter referred to as RF amplifier) 43 , and a high frequency tuning circuit (hereinafter referred to as RF tuning circuit) 44 to a mixer 45 . is input.

On the other hand, a local oscillator 51 connected to the resonant circuit 50 obtains a local oscillator signal having a frequency that is the difference between the desired reception frequency and the intermediate frequency, and this local oscillator signal is sent to the mixer 4.
5 is input. The mixer 45 outputs an intermediate frequency component from the input received signal and local oscillation signal, and the output is amplified by an intermediate frequency amplifier 46 and provided to a speaker 49 via a demodulation circuit 47 and a low frequency amplifier 48.

Furthermore, the output of the local oscillator 51 is passed through a frequency divider 52.
The output of the reference frequency oscillator 57 is input to the phase comparator 54 via the frequency divider 53, and a DC voltage proportional to the phase difference between these two inputs is output from the phase comparator 54. .

[0005] This DC voltage is applied to the antenna tuning circuit 42, R
The input is input to the F tuning circuit 44 and the resonant circuit 50, and in the resonant circuit 50, the capacitance of the internal variable capacitance diode changes according to the above DC voltage, and as a result, the phase comparator 5
Feedback is applied so that the phase difference between the two inputs to 4 becomes zero. That is, the local oscillator 51, frequency divider 52, phase comparator 54, and resonance circuit 50 constitute a phased-locked loop (hereinafter abbreviated as PLL).

In the case of this super receiver, a crystal oscillator is used as the reference frequency oscillator 57, and phase comparison is performed using a signal obtained by dividing the output of this stable frequency source as a reference, so that the frequency stability of the local oscillator 51 is As a result, frequency stability equivalent to that of the reference frequency oscillator 57 can be ensured.

Generally, in order to make the reception frequency variable, the system controller 55 changes the frequency division ratio of the frequency divider 52 to obtain the desired local oscillation frequency, while at the same time changing the reception frequency corresponding to the local oscillation frequency. is configured to be displayed on the display 56.

Further, the DC voltage output from the phase comparator 54 is transmitted to the antenna tuning circuit 42 and the RF tuning circuit 44.
It is also applied to the variable capacitance diode, which is a component of the . Furthermore, a putting capacitor is generally inserted into the resonant circuit 50 so that the two tuning frequencies of the tuning circuits 42 and 44 can be varied depending on the oscillation frequency of the local oscillator 51 and the tracking state.

[0009] The super receiver configured in this manner is capable of receiving signals by switching the receiving bandwidth in which the ratio of the lowest receiving frequency to the highest receiving frequency is approximately 3 times at specific frequency intervals, and is widely used. .

FIG. 7 is a block diagram showing a schematic configuration of a conventional direct synthesizer type super receiver. In this super receiver, a signal received by an antenna 61 is input to a mixer 65 through a band pass filter (BPF) 62, an RF amplifier 63, and a band pass filter 64.

A local oscillator signal output from the local oscillator 70 is also input to the mixer 65. The mixer 65 outputs an intermediate frequency component from the input received signal and local oscillation signal, and the output is amplified by an intermediate frequency amplifier 66 and provided to a speaker 69 via a demodulation circuit 67 and a low frequency amplifier 68.

The frequency of the local oscillator signal output from the local oscillator 70 can be arbitrarily set by a data signal from the system controller 71, and the reception frequency corresponding to the data signal is displayed on the display 72.

[0013] In the super receiver configured as described above, the bandpass filter 6 is rationally determined in consideration of the two-signal selectivity, cross-modulation, and other performances required of the receiver.
When receiving within the 2.64 band, the receiving frequency can be switched at high speed, and the tuning time can be significantly shortened. Therefore, it is widely used as a means for realizing high-speed tuning and as a local oscillator for transceivers that require high-speed switching of transmitting and receiving frequencies.

[0014]

[Problems to be Solved by the Invention] However, in the synthesizer type super receiver employing the PLL shown in FIG.
It takes about 100 msec for the frequency of the local oscillator signal to lock up and to determine the frequency of the local oscillator signal, which is a bottleneck in shortening the channel selection operation time. Generally, if a super receiver of this type were to perform channel selection in a 50 KHz step over a bandwidth of about 20 MHz, it would take about one minute.

On the other hand, in the direct synthesizer type super receiver shown in FIG. 7, the frequency of the local oscillator signal can be switched instantaneously, and by using an appropriate circuit, the tuning operation time can be kept within 1 msec. , there is a limit to the permissible reception bandwidth. That is, in order to widen the reception bandwidth of this receiver, it is necessary to prepare a large number of bandpass filters 62 and 64 and to switch between them, resulting in an increase in cost.

[0016] Accordingly, an object of the present invention is to provide a superheterodyne type receiver that can shorten the channel selection operation time without increasing cost.

[0017]

[Means for Solving the Problems] The present invention provides a desired receiving frequency tuning means that can be controlled by an input DC voltage, and a frequency specifying means that specifies the desired receiving frequency or a local oscillation frequency corresponding thereto as digital data. , local oscillation means that oscillates at a frequency corresponding to the digital data designated by the frequency designation means, and calculation of DC voltage data to be input to the desired reception frequency tuning means based on the digital data designated by the frequency designation means. The receiver is a superheterodyne type receiver, comprising a calculation means for calculating the data calculated by the calculation means, and a DC voltage generation means for generating a DC voltage from the data calculated by the calculation means and applying it to the desired reception frequency tuning means.

[0018]

[Operation] According to the present invention, the local oscillation means outputs a local oscillation signal with a frequency corresponding to the digital data designated by the frequency designation means, and the corresponding desired reception frequency is determined by the calculation means based on the designated digital data. DC voltage data corresponding to the data is calculated, and the DC voltage generation means that receives the data provides the DC voltage corresponding to the data to the desired reception frequency tuning means. the result,
The desired receiving frequency tuning means tunes to the desired receiving frequency corresponding to the digital data specified by the frequency specifying means, and the signal of that frequency can be received, and the tuning operation time can be shortened without requiring PLL, and the cost can be reduced. can also be reduced.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a schematic configuration of a receiver which is an embodiment of the present invention. This receiver is a super receiver equipped with a programmable local oscillator 14, an antenna tuning circuit 2 and an RF tuning circuit 4 each controlled by an input DC voltage. The signal is inputted to a mixer 5 via a circuit 2, an RF amplifier 3, and an RF tuning circuit 4.

The mixer 5 is a circuit for outputting an intermediate frequency component from the received signal inputted through the RF tuning circuit 4 and the local oscillator signal inputted from the local oscillator 14, and its output is outputted to an intermediate frequency amplifier. 6 and is applied to a speaker 9 via a demodulation circuit 7 and a low frequency amplifier 8.

A frequency data register 13 is connected to the local oscillator 14 . This frequency data register 1
3 is a circuit for holding frequency data which is digital data given from the system controller 15, and the frequency data in this case is data of a local oscillation frequency fo corresponding to the desired receiving frequency f. Upon receiving the frequency data of the local oscillation frequency f output from the frequency data register 13, the local oscillator 14 oscillates at the local oscillation frequency fo. A display 16 is connected to the system controller 15, and the desired reception frequency f corresponding to the frequency data is displayed on the display 16.

Further, an intermediate frequency shift circuit 12 is connected to the frequency data register 13. This intermediate frequency shift circuit 12 calculates a frequency fo+fi or a frequency fo-fi based on the frequency data of the local oscillation frequency f given from the frequency data register 13, and calculates a frequency fo-fi to which the antenna tuning circuit 2 and the RF tuning circuit 4 should tune. This is a circuit for generating data at reception frequency f.

A data calculation circuit 11 is connected to the next stage of the intermediate frequency shift circuit 12. This data calculation circuit 1
1 is a circuit for calculating DC voltage data to be input to the antenna tuning circuit 2 and the RF tuning circuit 4 based on frequency data given from the intermediate frequency shift circuit 12.

A digital-to-analog converter (hereinafter abbreviated as a D/A converter) 10 is connected to the next stage of the data calculation circuit 11. This D/A converter 1
0 converts the DC voltage data given from the data calculation circuit 11 into DC voltage and sends it to the antenna tuning circuit 2 and the RF
This is a circuit that supplies the tuning circuit 4.

FIG. 2 shows the antenna tuning circuit 2 and R
4 is a circuit diagram showing an example of a specific configuration of the F tuning circuit 4. FIG. A temperature compensation capacitor C1 and a trimmer Ct are connected in parallel to the tuning coil L1, and a variable capacitance diode V
A bypass capacitor C2 is connected in parallel via C1. An input terminal 21 is connected to the connection point between the variable capacitance diode VC1 and the bypass capacitor C2 via a resistor R1.
is connected to the input terminal 21, and a DC voltage for tuning the antenna tuning circuit 2 and the RF tuning circuit 4 to the desired receiving frequency, that is, a DC voltage given from the D/A converter 10, is inputted to the input terminal 21. The output signal is the tuning coil L1
It is taken out from either of the output terminals 22, 23 connected to.

Variable capacitance diode VC shown in the circuit of FIG.
If the applied DC voltage is V, the capacitance C of 1 is as follows:

0
027]

[Math 1]

It can be expressed as follows. However, K1 and K2 are each constants.

FIG. 3 is a diagram showing an example of voltage-capacitance characteristics of a general variable capacitance diode. Capacity C in this case
The relational expression between and voltage V is:

[0030]

[Math 2]

It can be expressed as follows. However, K1, K2
, K3 are constants, and are determined by physical characteristics specific to the varicap.

In the tuned circuit of FIG. 2, the tuned coil L1
If the inductance of is L, the combined capacitance of capacitor C and trimmer Ct is Cφ, and the resonant frequency is f, then the DC voltage V that should be applied to the variable capacitance diode VC1 in order for this tuning circuit to resonate at the target resonant frequency f, that is, DC voltage V required for the tuning circuit to tune to the desired receiving frequency f
teeth,

[0033]

[Math 3]

It is expressed as follows. However, K1, K2, and K3 are constants.

FIG. 4 is a block diagram showing a specific configuration of local oscillator 14 in FIG. 1. Oscillator (OSC)
21 is an oscillator that can select each frequency of 10 MHz, 20 MHz, and 30 MHz, and oscillators 22 and 23 are 10
It is an oscillator that can select frequencies with steps of 1 MHz from MHz, 11 MHz, 12 MHz, ..., 19 MHz. Moreover, the oscillators 24 and 25 each have 64
This is an oscillator that oscillates at MHz and 10 MHz, and the frequencies of all these oscillators are generated by dividing and mixing the outputs from one or two crystal oscillation circuits. Although the oscillator is shown divided into five blocks here, there is only one signal source with the same frequency.

The adder 26 is a circuit that obtains a 74 MHz frequency signal by adding the output frequencies of the oscillators 24 and 25, and the adder 27 adds the output frequency from the adder 26 and the output frequency of the oscillator 23. 84MHz to 93
This is a circuit that arbitrarily selects and outputs a frequency signal every 1 MHz up to MHz.

The frequency divider 28 divides the output frequency of the adder 27 into 1/10, and divides the output frequency from 8.4 MHz to 9.3 MHz.
This circuit arbitrarily selects and outputs frequency signals of up to 100 KHz.

Further, the adder 29 adds the output frequency from the frequency divider 28 and the output frequency from the oscillator 24, which is 100KH from 72.4MHz to 73.3MHz.
This is a circuit that arbitrarily selects and outputs frequency signals every z.

The adder 30 adds the output frequency from the adder 29 and the output frequency selected by the oscillator 22, which is 100KH from 82.4MHz to 92.3MHz.
This is a circuit that outputs frequency signals every z.

Furthermore, the adder 31 adds the output frequency from the adder 30 and the output frequency from the oscillator 21, which is 100 MHz from 92.4 MHz to 122.3 MHz.
This circuit outputs a frequency signal every KHz, and this frequency signal is taken out from the output terminal 32.

Separately, based on the frequency data of the local oscillation frequency fo given from the frequency data register 13, the oscillation frequency of each oscillator 21, 22, 23 is adjusted so that the local oscillation frequency fo can be obtained from the output terminal 32. A frequency selection circuit 33 is provided to select the frequency at high speed.

FIG. 5 is a flowchart illustrating the operation of the super receiver. In step a1, when the frequency data of the local oscillation frequency fo corresponding to the desired receiving frequency f is given from the system controller 15 to the frequency data register 13 and held therein, in step a2, the local oscillator receives this frequency data from the frequency data register 13. 14 oscillates at a local oscillation frequency fo, and the local oscillation signal is input to the mixer 5.

On the other hand, in step a3, the intermediate frequency shift circuit 12 receives the frequency data of the local oscillation frequency fo from the frequency data register 13, and the intermediate frequency fi
The frequency fo+fi or fo-fi is calculated based on the calculation result, and in step a4, data of the desired reception frequency f corresponding to the frequency to which the antenna tuning circuit 2 and the RF tuning circuit 4 should be tuned, that is, the local oscillation frequency fo, is calculated from the calculation result. is output.

In step a5, the data calculation circuit 1
1 receives data output from the intermediate frequency shift circuit 12, performs the calculation shown in equation 3 based on this data, and outputs the calculation result as DC voltage data. In step a6, this DC voltage data is
/A converter 10 converts it into a DC voltage, and the DC voltage is input to antenna tuning circuit 2 and RF tuning circuit 4. As a result, in step a7, the antenna tuning circuit 2 and the RF tuning circuit 4 receive the desired frequency f.
The signal at that frequency is received.

[0045] The commonly used intermediate frequency is 10.7
MHz, and assuming that the local oscillation frequency fo is higher than the desired receiving frequency f, this super receiver has a frequency of 81.7
It is possible to receive frequencies from MHz to 111.6 MHz in 100 KHz steps.

This received signal f is input to the mixer 5, mixed with a local oscillator signal input from the local oscillator 14 to the mixer 5, and converted into a signal of intermediate frequency f. This intermediate frequency signal is amplified by an intermediate frequency amplifier 6, further demodulated into a low frequency signal by a demodulation circuit 7, amplified by a low frequency amplifier 8, and reproduced by a speaker 9.

Since the data calculation circuit 11, intermediate frequency shift circuit 12, and frequency data register 13 are composed of digital logic circuits, their response speed is as high as that of the local oscillation circuit 14.
It is possible to sufficiently follow the frequency switching speed of , and the D/A converter 10 can also sufficiently follow this change.

[0048] Therefore, the channel selection speed is high and the PL
This means that it can cover the same reception band as the L-synthesizer type super receiver.

In order to further improve the economical efficiency of the super receiver of the above embodiment, all or part of the functions of the data calculation circuit 11, intermediate frequency shift circuit 12, and frequency data register 13 may be implemented using a program-controlled microprocessor. A computer may be used instead, and the system controller 15 may also be included in one microcomputer.

Furthermore, in the program control described above, if the data calculation speed becomes an obstacle to high-speed channel selection, the following configuration may be used.

In other words, pre-calculated frequency vs. voltage data is stored in memory for all or part of the required reception frequencies, and when frequency data is input, memory data at an address corresponding to that frequency is immediately stored. , and calculate the D/A converter 1 directly or by obtaining an approximate value.
By giving this value to 0, the speed of channel selection is increased.

Further, in the above embodiment, the local oscillation frequency fo is specified at the beginning, and the corresponding reception frequency f is shifted by the intermediate frequency fi, but conversely, the reception frequency f is specified at the beginning. Alternatively, the local oscillation frequency fo shifted by the intermediate frequency fi may be obtained.

[0053]

As described above, according to the receiver of the present invention, the local oscillation means outputs a local oscillation signal of the frequency corresponding to the digital data designated by the frequency designation means,
The calculation means calculates DC voltage data corresponding to the desired reception frequency corresponding to the specified digital data, and the DC voltage generation means that receives the data outputs the DC voltage corresponding to the data to the desired reception frequency tuning means. As a result, the desired receiving frequency tuning means immediately tunes to the desired receiving frequency corresponding to the digital data specified by the frequency specifying means, and the signal of that frequency can be received, allowing tuning without the need for PLL. Operation time can be shortened and costs can also be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a receiver that is an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a tuning circuit in the receiver of the embodiment.

FIG. 3 is a diagram showing voltage-capacitance characteristics of a general voltage variable capacitance diode.

FIG. 4 is a block diagram showing a more specific configuration of a local oscillator in the receiver of the embodiment.

FIG. 5 is a flowchart illustrating the operation of the receiver according to the embodiment.

FIG. 6 is a block diagram showing a schematic configuration of a conventional PLL synthesizer type super receiver.

FIG. 7 is a block diagram showing a schematic configuration of a conventional direct synthesizer type super receiver.

[Explanation of symbols]

2 Antenna tuning circuit 4 RF tuning circuit 5 Mixer 10 D/A converter 11 Data calculation circuit 12 Intermediate frequency shift circuit 13 Frequency data register 14 Local oscillator 15 System controller

Claims (1)

[Claims] Claims 1: Desired reception frequency tuning means controllable by input DC voltage; Frequency specification means for specifying the desired reception frequency or a local oscillation frequency corresponding thereto as digital data; a local oscillation means that oscillates at a frequency corresponding to the digital data; a calculation means that calculates DC voltage data to be input to the desired reception frequency tuning means based on the digital data designated by the frequency designation means; A superheterodyne receiver comprising: DC voltage generation means for generating a DC voltage from the calculated data and applying it to the desired reception frequency tuning means.