JPH04358391A - Semiconductor memory and line buffer used therein - Google Patents

Abstract

PURPOSE:To constitute an FIFO memory device with simple circuit configuration without a cache memory and to simplify the circuit configuration of a line buffer for this FIFO memory device. CONSTITUTION:In the FIFO memory device, a read line buffer to output data from a memory array is constituted by two stages. That is, by using the master latching circuits 33, 34 of a first stage and the slave latching circuit 37 of a second stage, one side master latching circuit 33 is made a function equivalent to the cache memory to have. Further, the number of the line buffer is reduced by multiplexing the selection of the bit line BL of the memory array with transfer gates 11-14.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is directed to FIFO (First-
In First Out) It relates to semiconductor storage devices such as memory devices and line buffers used in these semiconductor storage devices, and is particularly used in FIFO memory devices that do not use cache memory and FIFO memory devices with a reduced number of circuits. Regarding line buffers.

0002

2. Description of the Related Art FIG. 9 shows the structure of a conventional FIFO memory device. This FIFO memory device includes an input buffer 1, a cache memory 8, a write pointer 2, a write line buffer 3, a memory array 4, a read line buffer 5,
It consists of a read pointer 6 and an output circuit 7. The memory array 4 is composed of a dynamic random access memory (DRAM) that stores a large amount of data, and temporarily stores data in FIFO operation. In this FIFO memory device, in addition to a memory array 4 made up of DRAM, a cache memory 8 is made up of a high-speed static random access memory (SRAM) with a storage capacity of several tens of bits in order to read data continuously. has been established. FIG. 10 shows the configuration of the read line buffer 5. The read line buffer 5 is provided with a 1-bit line buffer circuit (LINE BUF) for each bit line BL of the memory array 4. Similarly to FIG. 10, the write line buffer 3 is also provided with a 1-bit line buffer circuit for each bit line BL (not shown).

The first few ten bits of data from input buffer 1 are input to cache memory 8 and stored therein. Subsequent data is input from the input buffer 1 to the write line buffer 3 and stored in the memory array 4 via the write line buffer 3. When reading these data, the data is output from the cache memory 8 to the output circuit 7 in response to a read reset signal (not shown), and while this data is being output, the data is output from the memory array 4 to the read line buffer. 5, the data stored in the memory array 4 is transferred. When the data is output to the last address of the cache memory 8, the data is output from the read line buffer 5 to the output circuit 7. As described above, the FIFO operation is performed, and in particular, the cache memory 8 is provided for reading out the first data in the FIFO operation.

0004

[Problems to be Solved by the Invention] Since the above-mentioned FIFO memory device requires the SRAM cache memory 8 as described above, it is necessary to control both the DRAM memory array 4 and the SRAM cache memory 8 using different control methods. The problem is that the control becomes complicated and the switching timing of these controls becomes critical. Furthermore, since the cache memory 8 is provided separately, there is a problem in that the layout area becomes large. Furthermore, since a line buffer is provided for each bit line BL, there is a problem that as the capacity of the memory array 4 increases, the area of the FIFO memory device also increases. In view of the above, an object of the present invention is to provide a FIFO memory device that can realize a small area and a line buffer applied to this FIFO memory device.

[0005]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a memory array, a write line buffer for writing data to the memory array, and a write line buffer for writing data from the memory array in the order in which the data is stored. A semiconductor memory device having a read line buffer for outputting data, wherein the read line buffer is configured to hold initial stored data and output the held data in response to a read signal. A semiconductor memory comprising a first line buffer circuit and a second line buffer circuit configured to output data from a memory array after data output from the first line buffer circuit is completed. Equipment is provided. Further, according to the present invention,
It has a plurality of blocks of line buffer circuits arranged in parallel, each of which includes a first group of gate circuits for selecting a plurality of bit lines of a memory device, and at least two blocks connected to the gate circuits. a first latch circuit means provided in parallel and operating at different timings, and a first latch circuit means provided at the output of the first latch circuit means,
A line buffer is provided that includes a second group of gate circuits that selectively output the outputs of these latch circuits at different timings, and a second latch circuit provided at the output of the second gate circuit.

[0006]

[Operation] The read line buffer has the above-mentioned two-stage configuration, and the first read line buffer stores the first data in correspondence with a conventional cache memory, and outputs the stored data first when reading. As a result, FI can be used without using cache memory, which is a memory device with a different control method and manufacturing method than memory arrays, as in the past.
The function of FO can be realized. In particular, control becomes easier because different memory control methods are no longer required. Further, by providing a gate circuit for multiplexing the bit lines of the memory array and providing a first group of line circuit means and a second group of line circuit means, the number of line buffer circuits can be significantly reduced.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a line buffer of the present invention and a FIFO memory device using the same will be described with reference to FIGS. 1 to 8. FIG. 1 is a block diagram of a FIFO memory device according to an embodiment of the present invention. This FIFO memory device has a configuration in which the cache memory 8 is removed from the conventional FIFO memory device shown in FIG. cache memory 8
Instead, the read line buffer 5 is replaced with a two-stage line buffer structure to be described later. Also in this embodiment, the memory array 4 is composed of DRAM.

FIG. 2 shows a partial circuit configuration of a read line buffer 5A as a first embodiment of the read line buffer 5. The read line buffer 5A shown in FIG. 2 includes transfer gate groups 11 to 14 and 15 to 18 connected to each of the four bit lines BL of the memory array 4, and each transfer gate group provided at the rear stage of these transfer gate groups. 1-bit read line buffer circuit (RLB) 19,
It has 20. These 1 bit RLB19,20
is connected to the output circuit 7 shown in FIG. As is clear from this circuit configuration, four transfer gates 11 to 14 made of transistors with a simple circuit configuration are provided, and these transfer gates 11 to 14 are controlled by a control signal C.
By selectively driving based on TL1 to CTL4 to select one of the bit lines BL, it is only necessary to provide one RLB 19 for four bit lines BL. As a result, the area of the read line buffer 5A becomes smaller and the layout of the FIFO memory device becomes smaller.

FIG. 3 shows a partial circuit configuration of a read line buffer 5B as a second embodiment of the read line buffer 5. In order to continuously output data, this read line buffer 5B includes two first-stage master latch circuits 33, which are provided in place of the cache memory 8 shown in FIG.
34 and a second-stage slave latch circuit 37. Transfer gates 11 to 11 connected to the bit line BL
14 is the same as in FIG. That is, the control signal CTL1
~CTL4 selectively outputs the outputs of the four bit lines BL. Transfer gates 31 and 32 are provided for inputting data selectively output from memory array 4 by transfer gates 11 to 14 to either master latch circuits 33 or 34. Furthermore, transfer gates 35 and 36 are provided to selectively output the output of master latch circuit 33 or master latch circuit 34 to slave latch circuit 37. The master latch circuit 33 has a function equivalent to the conventional cache memory 8, and has a capacity to store the first several ten bits of data to be input to the cache memory 8. As in the conventional case, the master latch circuit 34 stores data transferred from the memory array 4 when reading data.

The control circuit (not shown) is the FI shown in FIG.
At the time of initial operation of the FO memory device, a control circuit (not shown) is activated in response to a write reset signal (not shown).
stores the first few ten bits of data in the write line buffer 3. When data is written to the last address in the write line buffer 3, a transfer request is output from the control circuit to the memory array 4. When an arbiter (not shown) within memory array 4 accepts the request, the data is transferred to memory array 4 and stored. When this transfer is completed, the control circuit outputs a request to transfer these data from the memory array 4 to the master latch circuit 33, and the first master latch circuit selection signal S
Transfer gate 31 is turned on by M1, and data in memory array 4 is transferred to master latch circuit 33 via bit line BL and stored therein. As a result, the master latch circuit 33 has the conventional cache memory 8.
, the equivalent initial data is stored. Data subsequently input to the write line buffer 3 is sequentially stored in the memory array 4. Data is sequentially output from the master latch circuit 33 in response to a read reset signal (not shown) that is a read command, and the data is sequentially output from the master latch circuit 33.
When the last data read out in step 3 is performed, the control circuit outputs a data transfer request to the master latch circuit 34 to the memory array 4, and when it is accepted, the second master latch circuit selection signal SM2 is output and the transfer gate 32 is turned on and the data in the memory array 4 is stored in the master latch circuit 34. When the last data from the master latch circuit 34 is read, the next data transfer request is outputted again from the control circuit. Output data from the first and second master latch circuits 33 and 34 are output to the output circuit 7.

As described above, by configuring the read line buffer 5 in two stages, FIFO processing equivalent to that of a conventional FIFO memory device can be performed without providing the cache memory 8. On the other hand, layout problems caused by providing the cache memory 8 and D
Since the complexity of controlling the memory array 4 made up of RAM and the cache memory 8 made up of SRAM, which have different control methods, is eliminated, the configuration of the control circuit is also simplified. Furthermore, since the SRAM cache memory 8 and the DRAM memory array 4 are not mixed together, a FIFO memory device can be formed in the manufacturing process for manufacturing the memory array 4, and one chip can be easily realized.

FIG. 4 shows a partial circuit configuration of the read line buffer 5C when the read line buffer 5 has a two-port configuration. Two second-stage latch circuits, that is, two slave latch circuits 51 and 52 are provided corresponding to the two ports. When the read line buffer 5 is provided with two ports, normally it is necessary to provide two read line buffers of the two-stage configuration described above with reference to FIG. 3 for four bits. Since the data stored in the master latch circuit 33 is data for the first few ten bits in terms of address, the first master latch circuit 33
It is not necessary to provide each port separately and it can be used commonly. Therefore, the master latch circuit is the master latch circuit 3 in Figure 3.
It is sufficient to provide master latch circuits 44 and 46 for two ports, respectively, corresponding to the master latch circuit 45 corresponding to No. 3 and the master latch circuit 34 of FIG. Two slave latch circuits 51 and 52 are provided corresponding to two ports. Transfer gates 41-43 after bit line BL
are gates that select data to be transferred to master latch circuits 44 to 46, and transfer gates 47 to 50 select data to be transferred from master latch circuits 44 to 46 to slave latch circuit 5.
This is a gate that selects data transfer to 1 and 52. Transfer gates 49 and 50 are master latch circuit 45
The transfer gates 47 and 48 are gates that transfer the data stored in the memory array 4. The same applies to the case where the read line buffer 5 has a port configuration of less than four or five or more.

FIG. 5 is a partial circuit diagram showing a read line buffer 5D which is a modification of the read line buffer 5C shown in FIG. This read line buffer 5D has transfer gates 11 to 11 for selecting the bit line BL shown in FIG. 2 or 3 in addition to the read line buffer 5C in FIG.
14, and further a precharging transistor 53
This is a circuit configuration with . This lead line buffer 5
The operation of D is a combination of the selection operation of the transfer gate in FIG. 2 or 3 and the operation of the two-port read line buffer in FIG. FIG. 6 shows the operation timing of the read line buffer 5D shown in FIG. 5. First, precharge PR is performed, and a control signal CTL for selecting one of transfer gates 11 to 14 is output. Subsequently, a master latch circuit selection signal SM is output that drives transfer gates 41-43 for selecting data to be transferred to master latch circuits 44-46. When the data transfer from the input buffer 1 or memory array 4 to the master latch circuit 45 or the master latch circuits 44 and 46 is completed and the read reset signal RESET is input, the data transfer from the master latch circuit corresponding to the read reset signal to the slave latch circuit 51 or A slave latch circuit selection signal SL1 or SL2 for data transfer to transfer gate 52 is output to transfer gates 47-50. The read line buffer 5B of FIGS. 3 and 4 described above
5C also operates at the same timing as shown in FIG.

FIG. 7 shows a specific circuit diagram of the read line buffer 5D of FIG. 5. Portions with the same reference numerals as in FIG. 5 indicate the same circuit elements as those in FIG. master latch circuits 44 to 46 and slave latch circuit 51,
Both of 52 are realized by a simple 1-bit static latch circuit in which inverters are connected in antiparallel. Note that the read line buffer 5D in FIG. 7 is provided with transfer gates 61 and 62 for transferring data from the slave latch circuits 51 and 52 to the output circuit 7.

FIG. 8 shows a partial circuit configuration of the write line buffer 3 of FIG. 1. Similar to the various circuit configurations of the read line buffer 5 described above, this write line buffer 3 also has a transfer gate 75 that serves as a latch buffer and selectively drives four bit lines BL of the memory array 4.
~78 are provided. Transfer gate 75~7
8 is a write selection control signal C from a control circuit (not shown)
It is selectively driven in response to TLW1 to CTLW4. By providing these transfer gates 75 to 78, it is only necessary to provide one write line buffer circuit 72, which is a static latch circuit configured by inverters arranged in antiparallel, for each of the four bit lines BL. Transfer gate 71 selects transfer of 1-bit input data DIN to write line buffer 72 .

When implementing the present invention, various modifications can be made in addition to the circuit configuration described above. for example,
Although the case where the bit lines BL are selectively driven every four has been described, a plurality of bit lines BL can be selectively driven as appropriate.

[0017]

[Effects of the Invention] As described above, according to the two-stage read line buffer according to the present invention, even if no cache memory is used, the same F/F as with a cache memory can be achieved.
An IFO memory device can be realized, and the area is smaller and control is easier than that of a FIFO memory device using cache memory. Further, by selectively driving a plurality of bit lines via transfer gates according to the present invention, the number of write buffer circuits is greatly reduced, the above-mentioned area is further reduced, and the circuit configuration is simplified. Furthermore, since no cache memory is used, only one FIFO memory device can be used in the manufacturing process to form the memory array.
Can be made into chips.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of a FIFO memory device of the present invention.

FIG. 2 is a circuit diagram of a first embodiment of a read line buffer of the present invention applied to the FIFO memory device of FIG. 1;

FIG. 3 is a circuit diagram of a second embodiment of the read line buffer of the present invention applied to the FIFO memory device of FIG. 1;

FIG. 4 is a circuit diagram of a third embodiment of the read line buffer of the present invention applied to the FIFO memory device of FIG. 1;

FIG. 5 is a circuit diagram of a fourth embodiment of the read line buffer of the present invention applied to the FIFO memory device of FIG. 1;

FIG. 6 is an operation timing diagram of the read line buffer of FIG. 5;

FIG. 7 is a detailed circuit diagram of the read line buffer shown in FIG. 5;

FIG. 8 is a detailed circuit diagram of a write write buffer according to an embodiment of the present invention.

FIG. 9 is a configuration diagram of a conventional FIFO memory device.

FIG. 10 is a circuit diagram of a conventional read line buffer used in FIG. 9;

[Explanation of symbols]

1...Input buffer, 3...Write line buffer, 4
・・Memory array, 5・・Read line buffer, 7・
・Output circuit.

Claims (2)

[Claims] 1. A semiconductor memory device comprising a memory array, a write line buffer for writing data to the memory array, and a read line buffer for outputting data from the memory array in accordance with the stored order, the semiconductor memory device comprising: The read line buffer includes a first line buffer circuit configured to hold first stored data and output the held data in response to a read signal, and a first line buffer circuit configured to hold first stored data and output the held data in response to a read signal; After the output is finished,
and a second line buffer circuit configured to output data from a memory array. 2. A plurality of blocks of line buffer circuits provided in parallel, each of which includes a first group of gate circuits for selecting a plurality of bit lines of a memory device, and a first group of gate circuits for selecting a plurality of bit lines of a memory device; at least two first latch circuit means connected in parallel and operating at different timings; A line buffer having a second group of gate circuits for output and a second latch circuit provided at the output of the second gate circuit.