JPH04357775A - Clamp circuit - Google Patents

Abstract

PURPOSE:To converge the clamp level accurately and stably. CONSTITUTION:The clamp circuit is provided with a capacitor 11 transferring the only AC component of the input signal, an analog switch 13 controlling the DC component to be added to the output of the capacitor 11, an A/D converter 14 adding each output of the analog switch 13 and the capacitor 13 so as to be converted into the digital data, a subtractor 16 subtracting the digital data of the A/D converter 14 for the prescribed amount, a buffer gate 20 outputting the digital data of the A/D converter 14 for a constant period, a buffer gate 19 outputting the digital data of the subtracter 16 for the constant period, integration circuits 17 and 18 integrating each output of the buffer gates 19 and 20, and an inversion buffer 15 inverting each output of the integration circuits 17 and 18 after addition and supplying the DC component to the analog switch 13. It is designed to suppress the level fluctuation of the sum of each output of the integration circuits 17 and 18 when the input signal is at the objective level.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a television signal processing device for displaying a high-quality television signal having a different aspect ratio from the current NTSC television signal on an NTSC image display device, and particularly relates to a television signal processing device for displaying a high-quality television signal having an aspect ratio different from that of the current NTSC television signal. Regarding the clamp circuit to be set.

0002

[Background Art] In recent years, in addition to conventional terrestrial broadcasting, television broadcasting has diversified, including cable CATV broadcasting and satellite broadcasting, and furthermore, there are great expectations for higher image quality through IDTV, EDTV, etc. has been done. Among them, high-definition broadcasting using satellites is the conventional broadcasting system NTSC.
It has more than twice the number of scanning lines as the signal. For this reason, it is attracting attention from various fields, including the broadcasting industry as well as the printing industry, as it will greatly change television broadcasting in the future.

[0003] This high-definition broadcasting is generally performed using MUSE (Mu
ltiple Sub-nyquist Sample
The video data is transferred using a video data compression transfer method called .ng). For this reason, it is not compatible with the NTSC signal that has traditionally been broadcast, and cannot be received by currently used television receivers as is. In order to receive high-definition broadcasts, a new receiver for high-definition broadcasts must be prepared. However, this receiver is still expensive and it seems that it will take a lot of time for it to become widespread in general households.

[0004] Therefore, it is essential to have a converter that can receive high-definition broadcasts with the currently used NTSC television receivers, and various manufacturers are currently working on developing a converter for commercialization.

The major difference between high-definition broadcasting and conventional broadcasting using the NTSC system is that NTSC has 525 scanning lines and an aspect ratio of 4:3, whereas high-definition broadcasting has 1 scanning line and an aspect ratio of 4:3.
It has 125 lines and an aspect ratio of 16:9. Therefore, with reference to Figure 2, the aspect ratio of high-definition broadcasting is 16:9.
Let us consider the case where a screen of 1 is displayed on a display device with an aspect ratio of 4:3.

FIG. 2A shows a case where the entire 16:9 screen in the vertical direction is displayed to fill the entire 4:3 screen in the vertical direction. In addition, in Fig. 2(b), the entire horizontal direction of the 16:9 screen is
:3 shows the case where the screen is displayed completely in the horizontal direction. When attempting to display image data having different aspect ratios in this manner, the image information is inevitably missing or insufficient for the screen to be displayed. Furthermore, the amount of information in the video is reduced to about 1/4. However, if high-definition broadcasting could be received simply by adding the aforementioned converter without changing the current receiving device, it would be of great significance from the perspective of video software compatibility. Below, MUSE
The transmission method will be explained.

[0007] In the MUSE method, when sampling one image, each image is sampled at different points and divided into narrow image data of a plurality of frequency bands. That is, in the MUSE encoder, one image is sampled into four images and transferred. This allows high-quality broadcasting to be performed using the transmission bandwidth of satellite broadcasting. The MUSE decoder overlays the four transferred images to restore one original image. However, this processing is limited to cases where the original image is a still image.

[0008] If this process is performed on a moving image, each of the four images is moving, so the images overlap and the screen is broken. Therefore, in the video portion, only one of the four images is used for restoration. That is, missing pixel data between sampling points is created using surrounding pixel data. The above restoration process is performed using MUSE
Digital processing is performed based on data included in the signal to restore the original image, such as motion information.

Differences in processing between the MUSE signal receiver and the above-mentioned converter will be described below. The MUSE signal receiver performs still image processing and moving image processing as described above. However, the converter only performs video processing. The reason for this is that still image processing requires a large-capacity memory to store image data, which increases the circuit scale and increases cost. Since the converter may be built into current television receivers, satellite broadcast receivers, etc., it is necessary to keep costs low. Furthermore, for these reasons, it is necessary to perform other signal processing simply. Therefore, even though the MUSE signal receiver performs digital processing, some parts of the converter perform processing using simple analog circuits. An example of this is a clamp circuit.

FIG. 2 shows the configuration of the clamp circuit. The clamp circuit clamps the MUSE signal to a certain level when converting the transmitted MUSE signal into a digital signal.

Reference numeral 31 is a capacitor that cuts the DC component of the transmitted MUSE signal. 33 is an analog switch that controls the DC component added to the MUSE signal. 34 is an A/D converter that converts analog data into digital data. 32 is M to which a DC component is added
This is a buffer amplifier for inputting the USE signal to the A/D converter 34. A buffer gate 37 controls the MSB (most significant bit) of the digital data output from the A/D converter 34. 36 is an integrating circuit that integrates the output of the buffer gate 37, and is composed of a resistor and a capacitor. 35 is an inverting amplifier that inverts and amplifies the change in the output of the integrating circuit 36.

[0012] The MUSE signal includes a clamp level signal. Assuming that the level of the period in which this signal is included is represented by 8 bits, the MUSE signal is clamped so that the clamp level is 128.

FIG. 4 shows the transmission format of the MUSE signal. The clamp level signal is on the 563rd line and the 112th line.
Each sample number is multiplexed from 107 to 480 in 5 lines. Also, one line is sampled at 480 points, 1 to 1
One sample is allocated to the horizontal synchronization (HD) period.

FIG. 5 shows an HD waveform. In the figure, the horizontal reference phase point is the 6th sample point of the HD waveform, and has 128 levels. In addition, the signal C becomes “H” level between 9 samples centered on the 6th sample.
There is MPP. The signal CMPP controls the analog switch 33 mentioned above. That is, the signal CMPP is “H”.
When the signal is at the "level", the analog switch 33 is turned on. As a result, the output level of the inverting amplifier 35 is supplied to the MUSE signal whose DC component has been cut by the capacitor 31.

On the other hand, the buffer gate 37 receives the signal CMP
Controlled by G. The signal CMPG is as shown in FIG.
It remains at "L" level only during the period when the clamp level signal is being transmitted. Therefore, the buffer gate 37 is connected to the A/D converter 3 only during the period when the clamp level signal is being transmitted.
Outputs the MSB of the output of 4.

The case where the clamp level is less than 128 will be described below. In this case, since the MSB is at the "L" level, the output of the integrating circuit 36 changes in the direction of decreasing the level. Moreover, the clamp level being less than 128 means that the DC level of the amplifier 32 is low. This is nothing but a low output level of the inverting amplifier 35. Therefore, when the output level of the integrating circuit 36 decreases, the output level of the inverting amplifier 35 increases and the output level of the amplifier 32 also increases. This controls the clamp level to be increased.

Next, a case where the clamp level is 128 or higher will be described. In this case, since the MSB becomes "H" level, the output of the integrating circuit 36 changes in the upward direction. Also, if the clamp level is 128 or higher,
This means that the DC level of the amplifier 32 is high. This is nothing but a high output level of the inverting amplifier 35. Therefore, when the output level of the integrating circuit 36 increases, the output level of the inverting amplifier 35 decreases and the output level of the amplifier 32 also decreases, thereby controlling the clamp level to decrease.

In this way, the clamp level converges to around 128. However, in reality, the capacitance of the capacitor 31 is small and the clamping period is 300ns to 400ns.
It is as short as ns. Therefore, if the leakage current of the DC component of the capacitor 31 is large, the clamp level may drop to around 127.

Furthermore, the charges supplied to the integrating circuit 36 are supplied once per vertical period, which is quite a gap. Therefore, the leakage current in the integrating circuit 36 is also large, which causes the clamp level to become low.

[0020]

[Problem to be Solved by the Invention] The clamp circuit using the analog processing described above has a clamp level of exactly 1.
It does not converge to 28. If the clamp level, which is the standard for the level of the MUSE signal, deviates, it will cause deterioration in image quality. That is, the brightness and hue shift, causing flicker or the image quality becoming greenish. In addition, when adjusting the reference voltage of the A/D converter, ALC (automatic level control)
If the circuit becomes unstable and the CN ratio is low, this may cause deterioration in the performance of the audio circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and it is an object of the present invention to provide a clamp circuit that can accurately and stably converge the clamp level.

[0022]

[Means for Solving the Problems] Transmission means for transmitting only the AC component of an input signal, DC component addition means for controlling the DC component added to the output of the transmission means, and the transmission means and the DC component addition means. a first adding means for adding the respective outputs of the first combining means, an analog/digital converting means for converting the analog data of the first synthesizing means into digital data, and a predetermined amount of addition or a calculation means for subtracting; a first gate means for outputting the digital data of the analog/digital conversion means for a certain period of time; a second gate means for outputting the digital data of the calculation means for the certain period; The first integrating the output of the gating means of
an integrating means, a second integrating means for integrating the output of the second gate means, a second adding means for adding each output of the first and second integrating means, and a second combining means. and inverting means for inverting the output of the means and supplying the DC component to the DC component addition means, and suppressing fluctuations in the output level of the second addition means when the input signal is at a target level. It is.

[0023]

[Operation] According to the above means, the fluctuation of the clamp level is reduced by 1
Paying attention to the bit position, set the clamp level to 128.
An integrating circuit is provided to converge between and 129. As a result, even if a leakage current of about 1 bit occurs in the integrating circuit, fluctuations in the output level can be suppressed, and the video level can be set accurately. This results in
Brightness and hue are accurately reproduced. Furthermore, since the ALC circuit operates stably, the performance of the audio circuit is also compensated.

[0024]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a clamp circuit according to the invention. The DC component of the transmitted MUSE signal is cut off via the capacitor 11. Also, signal CM
The analog switch 13 controlled by PP receives the signal CMP
A DC component is added to the MUSE signal only when P is at "H" level. The MUSE signal to which the DC component has been added is input to the buffer amplifier 12 and amplified, and then input to the A/D converter 14 and converted into digital data.

The output of the A/D converter 14 is input to a subtracter 16 and "1" is subtracted from it. Subtractor 16 and A/D
Each MSB output of converter 14 is input to buffer gates 19 and 20, respectively. Buffer gates 19 and 20 each control the output of the MSB according to signal CMPG. That is, the MSB is output only while the signal CMPG is at the "L" level, and at other times, the output is high impedance. The outputs of the buffer gates 19 and 20 are input to integration circuits 17 and 18, each composed of a resistor and a capacitor, and are integrated. Integrating circuit 17
, 18 are both input to an inverting amplifier 15, and the integration results are inverted and amplified.

As mentioned in the conventional example, the MUSE signal includes:
A clamp level signal is included, and the MUSE signal is clamped so that the clamp level is 128. As shown in FIG. 4, the clamp level signal is multiplexed on sample numbers 107 to 480 of the 563rd line and the 1125th line. Further, in the horizontal synchronization (HD) period of samples 1 to 11, the HD signal shown in FIG. 5 is multiplexed. The signal CMPP is a signal that becomes "H" level during nine samples centered on the horizontal reference phase point of the sixth sample.

In the clamp operation, the signal CMPP is “H”
It is done at the level. That is, during this period, the analog switch 13 is turned on, and the output level of the inverting amplifier 15 changes to M, where the DC component is cut by the capacitor 11.
Added to the USE signal.

Furthermore, the signal CMPG that controls the buffers 19 and 20 is a signal that is at the "L" level only during the period when the clamp level is being transmitted. Therefore, buffer 19
subtracter 1 only during the period when the clamp level is being transmitted.
Outputs the MSB output from 6. Similarly, the buffer 20 also receives A/
The MSB output from the D converter 14 is output.

Now, a case will be described in which the digital output of the A/D converter 14 is less than 128 during the clamp level period. This digital output is input to the subtracter 16 and "1" is subtracted from it, so the output of the subtracter 16 is 1.
It will be less than 27. In this case, since the MSB is at the "L" level, the output of the buffer 19 is also at the "L" level. As a result, the output level of the integrating circuit 17 changes in a downward direction. Furthermore, since the output of the buffer 20 also goes to the "L" level, the output level of the integrating circuit 18 also changes in a downward direction.

Next, the case where the digital output of the A/D converter 14 is 129 or more during the clamp level period will be described. This digital output is input to the subtracter 16 and "1" is subtracted from it, so the output of the subtracter 16 is 1.
28 or more. In this case, since the MSB becomes "H" level, the output of the buffer 19 also becomes "H" level. As a result, the output level of the integrating circuit 17 changes in an upward direction. Furthermore, since the output of the buffer 20 also goes to the "H" level, the output level of the integrating circuit 18 also changes in an upward direction.

As described above, when the output level of the A/D converter 14 is less than 128, the outputs of the integrating circuits 17 and 18 both decrease. Further, when the output level is 129 or more, the outputs of the integrating circuits 17 and 18 both change in the upward direction.

Furthermore, the output level of the A/D converter 14 is 1.
The case of 28 will be described. In this case, the output of the buffer 19 becomes "L" level, and the output of the buffer 20 becomes "H" level.
Therefore, the output level of the integrating circuit 17 changes in a downward direction, and the output level of the integrating circuit 18 changes in an upward direction.Here, if the time constants of the integrating circuits 17 and 18 are set approximately equal, , the sum of the amount of change in each output almost disappears.

As described above, when the outputs of the integrating circuits 17 and 18 both decrease, the output level of the inverting amplifier 15 increases. Also, the outputs of the integrating circuits 17 and 18 are
If both increase, the output level of the inverting amplifier 15 will decrease. The output of the analog switch 13 changes depending on the outputs of the integrating circuits 17 and 18. The output of the analog switch 13 is added to the MUSE signal with the DC component cut off by the capacitor 11. As a result, the clamp level changes, and the output of the buffer amplifier 12 also changes.

That is, when the clamp level is lower than 128, the output level of the buffer amplifier 12 is increased, and when the clamp level is higher than 128, the output level of the buffer amplifier 12 is decreased.

Conventionally, when the clamp level was 128, the output level of the integrating circuit only changed in the upward direction, so the clamp level was downward. However, in the present invention, an integrating circuit is provided whose output levels change in opposite directions when the clamp level is 128. Therefore, fluctuations in the clamp level are reduced.

Further, currents from two integrating circuits are input to the inverting amplifier 15. As a result, the leakage current of one integrating circuit is halved, and the clamp level can be stabilized.

[0038]

As explained above, conventionally, the clamp level of the MUSE signal oscillated between 127 and 128, but according to the clamp circuit according to the present invention, the clamp level can be adjusted accurately and stably to 128. can be converged to. As a result, since the video level does not shift, brightness and hue are accurately reproduced, the ALC circuit also operates stably, and the performance of the audio circuit is also compensated.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a clamp circuit according to the present invention.

FIG. 2 is a diagram showing a case where a screen with an aspect ratio of 16:9 is displayed on a display device with an aspect ratio of 4:3.

FIG. 3 is a configuration diagram showing a conventional clamp circuit.

FIG. 4 is a diagram showing the transmission format of the MUSE signal.

FIG. 5 is a diagram showing an HD waveform.

[Explanation of symbols]

11, 31... Capacitor, 12, 32... Buffer amplifier, 13, 33... Analog switch, 14, 34... A/D
Converter, 15, 35... Inverting amplifier, 16... Subtractor, 17
, 18, 36...integrator circuit, 19, 20, 37... buffer gate.

Claims (1)

[Claims] 1. A transmission means for transmitting only an AC component of an input signal, a DC component addition means for controlling a DC component to be added to the output of the transmission means, and an output of each of the transmission means and the DC component addition means. an analog/digital converting means that converts the analog data of the first synthesizing means into digital data;
calculation means for adding or subtracting a predetermined amount of digital data of the analog/digital conversion means;
a first gate means for outputting the digital data of the digital conversion means for a certain period; a second gate means for outputting the digital data of the arithmetic means for the certain period; and a first gate means for integrating the output of the first gate means. a second integrating means for integrating the output of the second gate means; a second adding means for adding each output of the first and second integrating means; and an inverting means for inverting the output of the combining means and supplying the DC component to the DC component addition means, and the function is to suppress fluctuations in the output level of the second addition means when the input signal is at a target level. A clamp circuit characterized by: