JPH04352541A - Decoder circuit - Google Patents

Abstract

PURPOSE:To improve error correcting ability in the case of decoding a four phase differential PSK signal. CONSTITUTION:The absolute value of I and Q signals obtained by demodulating the four phase PSK signal is passed through one time slot delay circuits 502 and 507, the absolute values before and behind these circuits 502 and 507 are added by adders 503 and 508 and afterwards averages by reducing by half at 1/2 circuits 504 and 509, and a flexible deciding signal is obtained. The error correcting ability is improved by using this flexible deciding signal together with severe decision.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a decoding circuit that generates a signal for a soft-decision error correction circuit for a four-phase differential PSK signal used in, for example, FM multiplex broadcasting, BS digital audio, TV audio multiplex facsimile broadcasting, etc. The present invention relates to a decoding circuit.

0002

[Summary of the Invention] This invention is applicable to, for example, FM multiplex broadcasting, BS
It is related to the decoding method of QPSK modulated waves used as a transmission method for digital audio broadcasting, TV audio multiplex facsimile broadcasting, etc. The soft decision of a differentially encoded 2-bit signal is a value that is an index of reliability. are averaged, and the sign bit is determined by GC conversion, differential operation, G
By performing C conversion, soft decisions can be easily made.

0003

[Prior Art] Regarding soft decision of 4-phase differential PSK signal,
This has never been considered in the past. This is because soft decisions can only be applied to very limited codes. Recently, the soft decision of (272,190) code has been discussed, but regarding the output of the 4-phase differential PSK signal demodulation circuit, which is the input signal to the soft decision circuit,
Nothing has been said about it, and no examples have ever been put into practical use.

0004

[Problem to be solved by the invention] Conventionally, four-phase differential PSK
Signal decoding has simply involved hard-decision demodulation of I and Q detected signals, GC conversion, differential decoding, and GC conversion. Therefore, the signals input to the error correction circuit are 0 and 1.
Therefore, it was not possible to expect improvement in the correction ability by soft decision.

Therefore, it is an object of the present invention to make soft decisions at the I and Q detection signals even for 4-phase differential PSK signals, and to
This makes it possible to obtain soft decision values after C conversion, differential decoding, and GC conversion.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a decoding circuit for a four-phase differential PSK signal, which includes demodulation means for demodulating an input signal, and code data is extracted from the demodulated signal from the demodulation means. The present invention is characterized by comprising: means for detecting the absolute value level of the demodulated signal from the demodulating means; and means for averaging the detected values from the detecting means to obtain a soft decision signal.

[0007]

According to the present invention, a soft decision output can be obtained in addition to a hard decision output, and error correction capability can be improved.

[0008]

Embodiment The flow of a four-phase differential PSK signal is as shown in FIG. Serial data 100 is serial/parallel (S
/P) I as a parallel signal by the conversion circuit 101
, Q signals 102, 103, and Gray code (G
C) converted into a Gray code by the conversion circuit 104,
The converted I and Q signals 105 and 106 are input to a modulo-4 2-bit adder 107. This adder 10
In step 7, 2 input bits are added to 2 output bits. 108
, 109 are the I and Q signals after the adder 107, which are converted into Gray codes by the Gray code conversion circuit 110, and the I and Q signals 111 and 112 after this conversion are sent to the 4-phase PSK digital modulator 113. Digitally modulated. Reference numeral 114 indicates a modulated wave output from the digital modulator 113.

Further, the received modulated wave 115 is demodulated by a 4-phase PSK digital demodulator 116, and the I, Q signals 117, 118 after digital demodulation are sent to the I, Q level detection circuit 13.
The level (absolute value) is detected at 0, and the Gray code conversion circuit 119 converts the I and Q signals 120 and 121 into the Gray code. The input and output I and Q signals 123 and 124 are converted into Gray codes by a Gray code conversion circuit 125, and the I and Q signals 126 and 127 after Gray code conversion are converted into parallel/serial (P
/S) is converted into a serial signal by a conversion circuit 128 and output as a decoded output serial data signal 129.

FIG. 2 shows a specific example of signal generation from serial data 100 to I and Q signals 111 and 112 after Gray code conversion, and FIG. 3 shows the carrier phase of each signal.

FIG. 4 is a signal waveform diagram for explaining soft decision signal detection of a four-phase differential PSK signal.
Assuming that the Q signal is received as shown in FIG. 4, the level of A is "1" in hard decision, and the absolute value indicating the reliability of the signal is expressed as 0.8. B's level is "0" in hard judgment
The absolute value indicating the reliability of the signal is expressed as 0.5. In other words, the hard decision "1" with an absolute value of 0.8 has higher reliability.

It is assumed that the GC conversion circuit converts only the hard decision part of the input data and outputs the absolute value part without any change. That is, assuming that FIG. 4 shows the I signal, similar processing is performed for the Q signal as well. For example, the I signal has a hard decision of "0" and has an absolute value of 0.5, and the Q signal has a hard decision of "1" and has an absolute value of 0.8. Then similarly,
If the I signal "1" is 0.6 and the Q signal "1" is 0.9, the absolute value of each is the I signal (0.5 + 0.6)
/2=0.55, Q signal (0.8+0.9)/2=0.
85 is performed and input to a soft decision circuit (not shown).

In FIG. 5, 501 and 506 indicate absolute value data of signals from the I and Q level detection circuits 130,
These pass through one time slot delay circuits 502 and 507, and the data before and after these circuits 502 and 507 are added by an adder circuit 503 and 508, and then 504 and 5
09's 1/2 circuit (that is, averages the previous data) to obtain new absolute values of I and Q of 505 and 510. Naturally, these values may be represented by multiple bits. Also, since the hard decision signal passes through Figure 1, the time delay is as shown in Figure 5.
Therefore, the delay circuits 502 and 507 are increased so that the output in FIG. 5 and the output in FIG. 1 are output at exactly the same timing.

In FIG. 5, the average of the absolute values with the previous signal is calculated, but as shown in FIG. The two circuits 603 may calculate the absolute value by averaging. FIG. 6 shows the circuit configuration of the I system (the same applies to the Q system). Similar to FIG. 5, this case also requires a delay circuit for timing alignment with FIG. 1. Furthermore, the simplest method is to use the current I and Q signal absolute values instead of calculating the average of the signal absolute values as shown in FIGS. 5 and 6.

[0015] Although the above explanation has been made using four-phase differential PSK as an example, the present invention is also applicable to all differential digital modulation systems such as MSK and BPSK.

[0016]

Effects of the Invention According to the present invention, hard decision outputs “0”, “
It is now possible to obtain the optimal soft-decision output signal by averaging the signal absolute values that indicate a reliability of 1" according to the hard-decision signal conversion rules. The circuit can be easily realized, and the I
C conversion is also easy.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the flow of a four-phase differential PSK signal.

FIG. 2 is a diagram showing an example of generation of a four-phase differential PSK signal.

FIG. 3 is a diagram showing the carrier phase of each signal.

FIG. 4 is a signal waveform diagram for explaining soft decision signal detection of a four-phase differential PSK signal.

FIG. 5 is a diagram showing an example of an absolute value level conversion circuit according to the present invention.

FIG. 6 is a diagram showing another example of the absolute value level conversion circuit according to the present invention.

[Explanation of symbols]

502, 507 Delay circuit 503, 508 Adder circuit 504,509 1/2 circuit

Claims (1)

[Claims] 1. A decoding circuit for a four-phase differential PSK signal, comprising demodulating means for demodulating an input signal, means for extracting code data from a demodulated signal from the demodulating means, and an absolute value of the demodulated signal from the demodulating means. 1. A decoding circuit comprising: detection means for detecting a level; and means for averaging detection values from the detection means to obtain a soft decision signal.