JPH04350962A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a capacitance element with a little leakage of currant to a substrate and has a small series resistance. CONSTITUTION:An NPN transistor is formed in an island region 15 and a second capacitance element is formed in an island region 17. A second capacitance element forms an N<+> type lower electrode region 27 which is formed at the surface of the island region 17 by removing a buried layer 18, an upper electrode 29 formed like comb-teeth on the lower electrode region 27 and a leadout electrode 30 which is also formed like comb teeth and is in contact with the lower electrode region 27.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit incorporating a plurality of types of capacitive elements.

0002

[Prior Art] Capacitive elements incorporated in bipolar integrated circuits include capacitors that utilize PN junctions and oxide films (Si).
There are known devices that utilize O2) and nitride film (SiN). The former has a feature of simple structure, and the latter has the advantage of being able to increase the capacitance value per unit area. For this reason, the latter is often used in semiconductor devices that have been miniaturized.

A typical structure of the latter is shown in FIG. That is,
An N+ type diffusion region is formed in an island region (2) separating an epitaxial layer on a semiconductor substrate (1), and a lower electrode (3) is formed on the semiconductor substrate (1).
) and a dielectric thin film (4) made of SiO2 or SiN.
An upper electrode (5) is formed on top using Al wiring (
For example, Japanese Patent Publication No. 61-24825). Furthermore, (6)
is N+ buried layer, (7) is P+ isolation region, (8) is A
The l electrode (9) is an oxide film. In addition, the lower electrode (
As for 3), emitter diffusion of an NPN transistor is used in order to reduce the series resistance and to share the process.

In recent years, attempts have been made to perform emitter diffusion after forming the dielectric thin film (4) in order to avoid rediffusion and variations in the emitter region due to heat treatment for forming the dielectric thin film (4). In addition, bipolar elements and MO
In Bi-CMOS integrated circuits containing S elements, MO
Since the structure of the S element and the latter of the above capacitive elements are similar, a gate oxide film is formed on the dielectric thin film (4), and a gate oxide film is formed on the dielectric thin film (4).
), and the NchMOS source/
Attempts have been made to form the drain region by emitter diffusion. Then, since the emitter diffusion is performed after forming the dielectric thin film (4) in both cases, a process before the emitter, for example, a low resistance region of the collector of an NPN transistor, is used as the lower electrode (3).

[0005]

However, the collector low resistance region described above is formed in the first half to the middle of the manufacturing process, and it is difficult to increase the surface concentration to the extent of emitter diffusion. Therefore, there is a drawback that the series resistance of the capacitive element increases and the frequency characteristics of Q deteriorate.

In order to improve this, N+ is placed at the bottom of the capacitive element.
The type buried layer (6) is placed, but this time the PN junction between the N+ type buried layer (6) and the substrate (1) is a junction in a region with a relatively high impurity concentration, so the lower electrode (3) and the substrate (
1), and especially when used in a high frequency circuit, leakage current to the substrate (1) becomes large, resulting in parasitic effects.

[0007]

[Means for Solving the Problems] The present invention has been made in view of the above problems, and provides an NPN transistor (10), a first capacitive element (11), and a second capacitive element on the same substrate (13). (12) and the first capacitive element (11).
is an island region (16) in which an N+ type buried layer (18) is formed.
), and a dielectric thin film (24) and an upper electrode (25) are formed on the lower electrode region (23).
) are uniformly formed, and the second capacitive element (12) is N+
N is applied to the island region (17) where the mold buried layer (18) is not formed.
A +-type lower electrode region (27) is formed, and a lower electrode region (27) is formed.
A dielectric thin film (28) and an upper electrode (29) are formed on 7), and the extraction electrode (30) is arranged in a comb-like shape.

[0008]

[Function] The first capacitive element (mainly used in low frequency circuits)
11) can reduce the extraction resistance of the lower electrode region (23) by providing the N+ type buried layer (18), and also has a small occupied area. The second capacitive element (12) mainly used in high frequency circuits has an N+ type buried layer (18
), the island region (17) becomes a low concentration junction between the epitaxial layer and the substrate (13), and parasitic capacitance can be reduced. On the other hand, the increase in the extraction resistance of the lower electrode region (27) due to the removal of the buried layer (18) can be offset by making the extraction electrode (30) comb-shaped.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. Figure 1 shows an NPN transistor (10)
, the first capacitive element (11), and the second capacitive element (1
2) is a cross-sectional view showing. In the same figure, (13) is P
type silicon semiconductor substrate, (14) is a P+ type isolation region penetrating the N type epitaxial layer formed on the substrate (11) to form a plurality of island regions (15), (16), and (17);
(18) is an N+ type buried layer buried between the substrate (11) and the epitaxial layer.

[0010] The NPN transistor (10) has an island region (
15) N+ type buried layer (1) on the bottom substrate (13) surface
8), a P type base region (19) formed on the surface of the island region (15), an N+ type emitter region (20) formed on the surface of the base region (19), and the island region (15).
formed on the surface of the N+ emitter region (20), which is deeper than the emitter region (20).
It consists of a type collector low resistance region (21), and an Al electrode (22) is in contact with each region. The collector low resistance region (21) is formed before the emitter is formed, and has an impurity concentration (1021
atoms. cm-2), but its outermost surface concentration is lower than that of the emitter region (20) due to subsequent various heat treatments. Desirably, the collector low resistance region (21) is formed deep enough to connect to the N+ type buried layer (18).

[0011] The first capacitive element (11) has an island region (16
) N+ type buried layer (18) on the bottom substrate (13) surface
N+ type lower electrode region (23) and lower electrode region (23) formed simultaneously with the collector low resistance region (21) of the NPN transistor (10) on the surface of the island region (16).
dielectric thin film (24) made of a silicon oxide film or silicon nitride film uniformly formed on ), dielectric thin film (24)
It consists of an upper electrode (25) made of Al wiring formed above, and an extraction electrode (26) that contacts a part of the lower electrode region (23). As mentioned earlier, the lower electrode region (23) formed simultaneously with the N+ type collector low resistance region (21) of the NPN transistor (10) has a slightly higher surface concentration than the emitter region (20) of the NPN transistor (10). It has a low sheet resistance of 40 to 60Ω/□. Therefore, an N+ type buried layer (18) is provided at the bottom to reduce the extraction resistance of the lower electrode region (23). Since the dielectric thin film (24) and the upper electrode (25) can be uniformly formed in a rectangular area, the occupied area is small.

[0012] The second capacitive element (12) has an island region (17
) without forming a buried layer (18) at the bottom of the substrate (13), an epitaxial layer, and an isolation region (14).
surrounded by a PN junction with a relatively low impurity concentration and an epitaxial layer. Then, an N+ type lower electrode region (27) is formed simultaneously with the collector low resistance region (21) of the NPN transistor (10) on the surface of the island region (17), and a plurality of N+ type lower electrode regions (27) are formed on the lower electrode region (27). A dielectric thin film (28) made of a silicon oxide film or a silicon nitride film formed separately, an upper electrode (29) made of an Al wiring formed on the dielectric thin film (28), and a lower electrode region (27). It consists of an Al extraction electrode (30) in contact with the surface of. The uppermost surface concentration of the lower electrode region (27) is the same as that of the first capacitive element (
It is the same as that of 11).

FIG. 2 is a plan view of the second capacitive element (12). For the uniformly formed lower electrode region (27),
The dielectric thin film (28) is divided into a plurality of parts, and an upper electrode (29) extends in a comb-like shape on the divided dielectric thin film (28). The extraction electrode (30) extends in a comb-teeth shape so as to face the upper electrode (29), and is in ohmic contact with the lower electrode region (27) over substantially its entire length.

Since the second capacitive element (12) does not have an N+ type buried layer (18), the PN junction with the substrate (13) becomes a low concentration junction, and the junction capacitance (31) is reduced so that it is not ground biased. The leakage current to the substrate (13) can be reduced. Therefore, it can be used in high frequency circuits. On the other hand, the lower electrode region (2) due to the removal of the buried layer (18)
The increase in the extraction resistance in 7) can be offset by making the extraction electrode (30) comb-shaped. Therefore, the frequency characteristics of the capacitance Q can be improved.

[0015] As described above, the present invention is suitable for use in high-frequency circuits, and can reduce leakage current to the substrate (13) and reduce series resistance.

[0016]

[Effects of the Invention] As explained above, according to the present invention,
By removing the buried layer (18) and making the extraction electrode (30) comb-shaped, it is possible to incorporate a capacitive element that can suppress leakage current to the substrate (13) and also suppress an increase in series resistance. . Therefore, by using the first capacitive element (11) for the low frequency circuit and the second capacitive element (12) for the high frequency circuit, it is possible to perform an optimal design while suppressing an increase in the occupied area.

[Brief explanation of the drawing]

FIG. 1 is a sectional view for explaining the present invention.

FIG. 2 is a plan view for explaining the present invention.

FIG. 3 is a sectional view for explaining a conventional example.

Claims (5)

[Claims] 1. An island-shaped semiconductor substrate comprising a semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type formed on the substrate, an isolation region of one conductivity type separating the epitaxial layer, and the isolation region. a plurality of island regions formed in each of the plurality of island regions, a bipolar transistor formed in each of the plurality of island regions, and a capacitive element; a base region of one conductivity type formed on the surface of the base region, an emitter region of the opposite conductivity type formed on the surface of the base region, and a collector low resistance region deeper than the emitter region formed on the surface of the island region, The capacitive element includes a lower electrode region of an opposite conductivity type formed simultaneously with the collector low resistance region of the bipolar transistor on the surface of the island region, and a dielectric thin film covering the surface of the lower electrode region.
The island region, which includes an upper electrode formed on the dielectric thin film and a comb-like extraction electrode that contacts the surface of the lower electrode, and in which the second capacitive element is formed, is connected to the epitaxial layer. A semiconductor integrated circuit characterized in that it is divided by a PN junction with the isolation region and a PN junction between the epitaxial layer and the substrate. 2. The semiconductor integrated circuit according to claim 1, wherein the capacitive element is used in a high frequency circuit. 3. An island-shaped semiconductor substrate formed of a semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type formed on the substrate, an isolation region of one conductivity type that separates the epitaxial layer, and the isolation region. a plurality of island regions, a bipolar transistor formed in each of the plurality of island regions, a first capacitor element, and a second capacitor element; a buried layer of the mold, a base region of one conductivity type formed on the surface of the island region, an emitter region of the opposite conductivity type formed on the surface of the base region, and the emitter region formed on the surface of the island region. and a deep collector low resistance region, and the first capacitive element is formed simultaneously with a buried layer of an opposite conductivity type buried in the surface of the substrate and a collector low resistance region of the bipolar transistor on the surface of the island region. a lower electrode region of opposite conductivity type, a dielectric thin film uniformly covering the surface of the lower electrode region, an upper electrode formed on the dielectric thin film, and an extraction contacting the surface of the lower electrode region. the second capacitive element has a lower electrode region of an opposite conductivity type formed simultaneously with the collector low resistance region of the bipolar transistor on the surface of the island region, and covers the surface of the lower electrode region. The island region includes a dielectric thin film, an upper electrode formed on the dielectric thin film, and a comb-like extraction electrode that contacts the surface of the lower electrode, and in which the second capacitive element is formed. , a PN junction between the epitaxial layer and the isolation region,
and a semiconductor integrated circuit, characterized in that the epitaxial layer is divided by a PN junction between the epitaxial layer and the substrate. 4. The first capacitive element is connected to a low frequency circuit,
4. The semiconductor integrated circuit according to claim 3, wherein the second capacitive element is used for a high frequency circuit. 5. The semiconductor integrated circuit according to claim 1, wherein the lower electrode region has a higher sheet resistance than the emitter region of the bipolar transistor.