JPH04349795A - On-screen display circuit for television receiver - Google Patents

Abstract

PURPOSE:To enhance legibleness of a video signal a little in an attenuated area and to improve the visibility of the character or the symbol of no-screen display and make the video signals in the attenuation region slightly legible by attenuating video signals to the left and right sides of the character or the symbol of on-screen display of a television receiver. CONSTITUTION:A switch signal 17 used to select a display signal 15 from an output video signal given to a display control section of on-screen display together with the display signal 15 is delayed by D flip-flops 19, 20 by using a clock signal 18 corresponding to a picture element of the said display signal 15, the switch signal 17 and a 2-clock period delay signal resulting from the above switch signal 17 are given to an OR circuit, its output OR signal 21a is used to select a signal resulting from an input video signal 10 via an attenuator 14, and a 1-clock period delay signal 19a resulting from the above signal 17 is used to select and output a 1-clock period delay signal resulting from the above display signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of Industrial Application The present invention relates to improving the visibility of characters or symbols by attenuating video signals around characters or symbols representing control or operating states superimposed on a video signal displayed by a television receiver.

0002

[Prior Art] A switch signal is output together with a display signal of a display control section of an on-screen display, and is used to switch an input video signal to the same display signal during a period when the same display signal is present, and to superimpose the same display signal on the input video signal. there were.

0003

[Problem to be solved by the invention] When the display size of the characters or symbols is reduced as the number of characters or symbols displayed on-screen increases, it becomes difficult to read depending on the image surrounding the displayed characters or symbols. . For this reason, if the character size is increased or the area of displayed characters is extracted in black or gray and the characters are displayed in the same area, the missing video area also increases, resulting in a screen that is difficult to see.

0004

[Means for Solving the Problem] A clock signal corresponding to a pixel of an on-screen display is used as a display signal output from a display control unit or a switch signal for switching an input video signal outputted together with the same display signal to the same display signal. The input video signal is attenuated to a predetermined level by outputting an OR with a signal or a switch signal delayed by 2 clock cycles, and the same display signal delayed by 1 clock cycle or a display signal delayed by 1 clock cycle by a switch signal is selected. Output.

[0005]

[Operation] In the block diagram of the television receiver shown in FIG.
Alternatively, the operation signal of the key input unit 35 is decoded by the control unit 34, and the tuner unit 32 receives a specified TV broadcast signal using the outputted channel selection signal, and the demodulated video signal or the video input to the external input terminal 30 is received. selector 33 for one of the signals
, and the signal synthesis unit 39 superimposes the display signal of the on-screen display. A synchronizing signal separated from the video signal selected by the selector 33 is supplied to the display control section 38 to synchronize the generated clock signal, and the control section 34 outputs a character or symbol indicating the control state or operating state of the television receiver. The code signal is converted into a display signal in a format to be displayed on a television screen, and is supplied to the signal synthesis section 39.

[0006] In the signal synthesis section 39 shown in FIG. 1, the input video signal 10 is outputted via switch circuits 11 and 12. The display control unit 38 outputs a switch signal 17 together with the display signal 15 to switch the output video signal to the display signal 15, and the clock signal 18 corresponding to the pixel of the display signal 15 is applied to the switch signal 17 through a D-type flip-flop 19. The switch circuit 1 uses a signal delayed by a clock cycle.
2, and the D type flip of the same display signal 15.
A signal delayed by one clock period is outputted via the flop 16. Therefore, the display signal 15 is the video signal 1
The display is shifted to the right by one clock cycle of the display signal 15 with respect to the predetermined position of 0.

The switch signal 17 and the flip-flops 19 and 20 of the switch signal 17
The switch circuit 11 is switched by the OR output of the signal delayed by the clock cycle, and the video signal 10 is branched to select the signal that is passed through the attenuator 14. Therefore, an attenuated input video signal of one clock cycle is output before and after the display signal delayed by one clock cycle, resulting in a display in which the left and right sides of the characters or symbols on the on-screen display are bordered with gray filters.

Display signal 1 outputted from the display control section 38
5 is a binary pulse signal, which is almost the same as the switch signal 17 output from the display control section 38, so the switch signal 17 in FIG. 1 can be replaced with the display signal 15. At this time, the circuit can be simplified by sharing a part of the delay circuit using flip-flops, and an example of this circuit is shown in FIG. In the same figure and in FIG. 4 described below,
Elements with the same function corresponding to those in FIG. 1 are given the same reference numerals or the same reference numerals with suffixes.

Furthermore, in a color display television receiver, as shown in FIG. 4, display signals 15a corresponding to red, green, and blue are used.
, 15b, 15c, respectively, with the corresponding flip-
The same display signals 15a, 15b,
The output of the logical OR synthesis of 15c is sent to the flip-flop 19.
and 20, outputs a display signal delayed by 1 clock period using the 1 clock cycle delay signal of the same OR composite output, and ORs the 2 clock cycle delay signal of the same OR composite output and the same OR composite output. Input video signal 10a with composite output
, 10b and 10c are output.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the main block diagram of a television receiver shown in FIG. 2, a television broadcast signal input to an antenna input terminal 31 is supplied to a tuner section 32. The input control unit 34 decodes the remote control signal output from the remote control unit 40 via the remote control signal receiving unit 36 or the operation signal output from the key input unit 35, and uses the output control signal to generate the broadcast signal of the designated channel. Select, demodulate and output. The tuner section 3
2 or the video signal input to the external input terminal 30 is selected via the selector 33, and is supplied to a signal synthesis section 39 that superimposes a display signal for on-screen display, and is also supplied to a synchronization separation section 37, Outputs horizontal and vertical synchronization signals separated from the same video signal.

The synchronizing signal is supplied to the deflection circuit and also to the display control section 38, and the control section also sends a code signal of characters or symbols indicating the control state or operating state of the television receiver to the display control section 38. The signal is supplied, converted into a display signal in a format to be displayed on a television screen, and supplied to the signal synthesis section 39. In the signal synthesis section 39, the display signal of characters or symbols to be displayed on-screen is superimposed on the input video signal, and the superimposed signal is supplied to the cathode ray tube via the video output section for display.

In the signal combining section 39 shown in FIG.
The input video signal 10 is output from the output terminal 13 via the switch circuits 11 and 12, and the same video signal 10 is branched to a predetermined level, for example, 6d.
The same switch circuit 11 via an attenuator 14 that attenuates B
feed the other inputs of. The display control unit 38 outputs the display signal 15 of characters or symbols displayed on the screen together with the switch signal 17 of the display signal 15 through the D-type flip-flop circuits 19 and 20 to the clock signal of the display control unit 38. The rising edge of signal 18 is sampled and delayed.

The outputs of the switch signal 17 and the switch signal 15 via the flip-flop circuits 19 and 20 are combined by an OR circuit 21,
1 output 21a switches the output of the switch circuit 11 to the output via the attenuator 14. Similar to the switch signal 17, the display signal 15 output from the display control section 38 is also transmitted to the switch circuit 11 via a D-type flip-flop circuit 16 driven by the clock signal 18.
is supplied to the other input of the switch circuit 12 that supplied the output. Flip-flop circuit 1 for the switch signal 17
The switch circuit 12 is driven by the branched output 19a of the switch 9, and the output of the flip-flop circuit 16 is selected and supplied to the output terminal 13 during the period when the flip-flop output 19a is "1".

The switch signal 17 output from the display control section 38 can also be replaced with a display signal 15 output from the display control section 38, as shown in FIG. That is, by substituting the switch signal 17 with the display signal 15, a part of the flip-flop which is a delay circuit for the switch signal 17 and the display signal 15 can be shared, and the circuit can be simplified. Figure 3 and Figure 4 described below
1, elements having the same functions as those in FIG. 1 are given the same reference numerals or the same reference numerals with suffixes.

[0015] Furthermore, in a television receiver that displays on-screen characters or symbols in color, as shown in FIG.
Display signals 15a, 15b, corresponding to red, green, and blue;
15c through flip-flop circuits 16a, 16b, 16c corresponding to the respective signals, red, green,
Input video signals 10a, 10b, 10 corresponding to blue
The output is supplied to the switch circuits 12a, 12b, 12c together with the outputs via the attenuators 14a, 14b, 14c and the switch circuits 11a, 11b, 11c, and is synthesized by the OR circuit 22 of each display signal 15a, 15b, 15c. Flip-flop circuit 1
The same switch circuits 12a, 12b,
12c, the output of the same OR circuit 22 and the same OR circuit 2
The same switch circuits 11a, 11b, 11c are outputted via the flip-flop circuits 19 and 20 with the outputs of the two outputs.
to drive.

[0016]

[Effects of the Invention] As described above, even if the size of the on-screen displayed characters or symbols superimposed on the displayed image is reduced, it will not become difficult to see due to the influence of the background, and the images of the left and right edges of the same characters or symbols will be Discrimination is possible to some extent.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a signal synthesis section of the present invention of an on-screen display circuit.

FIG. 2 is a block diagram of a television receiver.

FIG. 3 is a circuit diagram corresponding to claim 2 of the signal synthesis section of the present invention.

FIG. 4 is a circuit diagram corresponding to claim 3 of the signal synthesis section of the present invention.

[Explanation of symbols]

10 Input video signal 11 Switch circuit 12 Switch circuit 14 Attenuator 15 Display signal 16 Flip-flop circuit 17 Switch signal 18 Clock signal 19 Flip-flop circuit 20 Flip-flop circuit 21 Logical sum circuit 22 OR circuit 35 Key input section 36 Remote control signal receiving section 38 Display control section 39 Signal synthesis section

Claims (3)

[Claims] Claim 1: A code of characters or symbols corresponding to pixels of an on-screen display and corresponding to a designation from a remote control signal via a key input section or a remote control signal receiving section, using a clock signal synchronized with a synchronization signal of an input video signal. A display control unit that converts the signal into a display signal corresponding to the display pixel, counts the clock signal, and outputs the clock signal to be displayed at a predetermined position on the display screen, and a signal synthesis unit that superimposes the display signal on the input video signal. In the on-screen display circuit of a television receiver, the period of the display signal output from the display control section is delayed by two clock cycles according to a switch signal for switching the input video signal to the display signal and the clock signal. A television set that selects and outputs the same input video signal that has been attenuated by a predetermined amount by outputting a logical sum with the signal, and selectively outputs the same display signal that is delayed by one clock cycle using the same switch signal that is delayed by one clock cycle. Receiver on-screen display circuit. 2. The on-screen display circuit for a television receiver according to claim 1, wherein a display signal output from the display control section is used as the switch signal output from the display control section. 3. Attenuation by a predetermined amount is performed by a logical sum output of the display signals corresponding to each color of red, green, and blue outputted by the display control unit and the same logical sum output delayed by two clock cycles. In addition to selectively outputting input video signals corresponding to red, green, and blue, display signals for each color delayed by one clock cycle are output by OR outputting display signals corresponding to each color of red, green, and blue delayed by one clock cycle. 2. The on-screen display circuit for a television receiver according to claim 1, wherein the on-screen display circuit performs selective output.