JPH04346512A - Electronic timer - Google Patents

Abstract

PURPOSE:To easily and accurately set the timer time at zero. CONSTITUTION:A count pulse circuit 1 outputs a count pulse S1' having its production cycle shorten as the set timer time is shortened. A detecting circuit 2 detects and outputs S3 the production cycle of the pulse S1' when the timer time is set at zero. A zero setting circuit 3 outputs the zero set outputs S5 and S6 of the timer time in response to the input of the detection output S3 generated when the timer time is set at zero. Thus the timer time can be accurately set at zero.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic timers, and more particularly to zeroing a timer time.

0002

2. Description of the Related Art A conventional electronic timer will be explained with reference to FIG. 5. VDD is a power supply, VSS is a ground, and R1 is a variable resistor. The resistance value of the variable resistor R1 is varied in conjunction with a timer time setting volume (not shown). R2 is an overcurrent prevention resistor, and C1 is a capacitor. The variable resistor R1, overcurrent prevention resistor R2, and capacitor C1 are connected in series with each other.

[0003] The timer time is a charging/discharging time constant determined by the product of the total series resistance value of the variable resistor R1 and the overcurrent prevention resistor R2 and the capacitance value of the capacitor C1, that is, the change in the charging voltage V1 of the capacitor C1. Set by period. Therefore, since the capacitance value of capacitor C1 is fixed,
The timer time can be set by operating the resistance value of the variable resistor R1, that is, the timer time setting volume.

R3 and R4 are resistors for determining the discharge timing of the capacitor, which divide the power supply VDD and apply the divided voltage to the timer main body IC through the connection between the resistors R3 and R4. .

[0005] The IC is the main body of the timer, and the capacitor C
The timer operation is performed using the charging voltage V1 of 1 and the divided voltage V2 at the connection between the resistors R3 and R4.

That is, as shown in FIG. 6, the timer body IC discharges the capacitor all at once to the potential of VSS every time the charging voltage V1 to the capacitor C1 reaches the divided voltage V2. C1 charging voltage V
1 as shown in FIG.
The timer operation is performed in response to the change period T of 2.

[0007] The timer main body IC internally shapes the analog charging voltage V2 into a pulse waveform to make it suitable for digital processing, and uses this pulse as a count pulse to be counted by a timer counter to perform timer operation. Specifically, by operating the timer time setting volume so that the resistance value of the variable resistor R1 becomes large, the charging speed of the capacitor C1 is slowed down, and the output cycle of the count pulse is lengthened, thereby changing the timer time. In addition, by operating the timer time setting volume so that the resistance value of the variable resistor R1 becomes small, the charging speed of the capacitor C1 is increased, and the output period of the count pulse is shortened, so that the timer time can be shortened. It has become.

Since the timer operation using such pulses is well known, further detailed explanation will be omitted.

[0009]

[Problem to be Solved by the Invention] By the way, when the timer time is set to, for example, one hour by operating the timer time setting volume, if you want to instantly return the timer time to zero by operating this setting volume. There is.

In order to instantaneously set the timer time to zero, the charging/discharging time constant consisting of the variable resistor R1, overcurrent prevention resistor R2, and capacitor C1 is made as small as possible to increase the charging speed of the capacitor C1. Therefore, it is necessary to increase the output cycle of the count pulse to correspond to the zero setting. To this end, since the capacitance value of the capacitor C1 is fixed and cannot be reduced, it is conceivable to reduce the resistance values of each of the variable resistor R1 and the overcurrent prevention resistor R2.

However, even if the resistance value of the variable resistor R1 can be made small, if the resistance value of the overcurrent prevention resistor R2 is made extremely small, an overcurrent will flow into the timer main body IC and the operation of the timer main body IC will be affected. It was not possible to reduce the resistance value of the overcurrent prevention resistor R2 because it would have an adverse effect on the overcurrent prevention resistor R2.

As a result, even if you try to instantaneously set the timer time to zero by operating the timer time setting volume, it will not be possible to set the timer time to zero instantaneously, and the timer will have to count up until the counter counts up. If the value is large, there is a problem that even if the timer time is set to zero by operating the setting volume, the timer will reach zero after a considerable amount of time has elapsed.For this reason, it is difficult to check the sequence operation of equipment using this timer, for example. The problem was that it took a very long time to check the operation because the timer did not operate instantaneously.

Therefore, it is an object of the present invention to enable the timer time to be instantaneously set to zero easily and accurately.

[0014]

[Means for Solving the Problems] In order to achieve the above object, the electronic timer of the present invention includes a count pulse circuit, a count pulse generation period detection circuit, and a zero setting output circuit. The count pulse circuit outputs count pulses whose generation cycle becomes shorter as the timer time setting becomes shorter, and the count pulse generation cycle detection circuit outputs the count pulse generation cycle when the timer time is set to zero. The zero setting output circuit is characterized in that it outputs a zero setting output of the timer time in response to the input of the detection output when the timer time is set to zero.

[0015]

[Operation] The count pulse circuit outputs count pulses whose generation cycle becomes shorter as the timer time setting becomes shorter. The count pulse generation cycle detection circuit detects and outputs the count pulse generation cycle when the timer time is set to zero. The zero setting output circuit outputs a timer time zero setting output in response to the input of the detection output when the timer time is set to zero.

[0016]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a circuit diagram of an electronic timer according to Embodiment 1 of the present invention, and FIG. 2 is a timing chart for explaining its operation.

The electronic timer of the first embodiment includes a count pulse circuit 1 that outputs a count pulse S1, a detection circuit 2 that outputs a detection output S3 of the generation cycle of the count pulse S1, and an instantaneous zero setting output S5 of the timer time. , S6.

The count pulse circuit 1 includes first and second comparators CP1 and CP in order to output the count pulse S1.
2, an RS flip-flop FF1, a variable resistor R1, a plurality of resistors R2 to R6, and a capacitor C1.

The variable resistor R1 constitutes the timer time setting section 4 together with the overcurrent prevention resistor R2 and the capacitor C1, and corresponds to the same reference numeral in FIG.
The resistance value is varied in conjunction with a timer time setting volume (not shown). A charging voltage V1 having a charging/discharging change waveform corresponding to the timer setting time is output from the connection between the resistor R2 and the capacitor C1. Resistors R3 and R4 also correspond to those with the same symbols in FIG.
The first setting unit 5 outputs the divided voltage V2 at the connection between R4
It consists of The resistors R5 and R6 are similar to the first setting section 5, and the divided voltage V2 is applied at the connection between the two resistors R5 and R6.
' constitutes a second setting section 6 that outputs the value.

The charging voltage V1 and the divided voltages V2 and V2' are input to each input section of the first and second comparators CP1 and CP2, and the first comparator CP1 responds to these inputs to output the RS. Output the set input to the S terminal of flip-flop FF1,
Similarly, the second comparator CP2 outputs a reset input to the R terminal of the RS flip-flop FF1 in response to this input. The RS flip-flop FF1 outputs a count pulse S1 from the Q terminal in response to its set and reset inputs.
Generate and output. This count pulse S1 is given to a timer counter (not shown). This timer counter counts up at a predetermined count value and is the same as that explained in the section of the prior art, so its explanation will be omitted. In this way, the count pulse circuit 1 outputs the count pulse S1 to the timer counter via the Q terminal of the RS flip-flop FF1.
A count pulse S1' obtained by inverting the level of the count pulse S1 is output from the Q' terminal of the flip-flop FF1 to the detection circuit 2 via the buffer amplifier BF1. The generation cycle of the inverted count pulse S1' becomes shorter with the pulse width as the timer time is set from longer to shorter.

The detection circuit 2 receives an inverted count pulse S1'
consists of resistors R7 to R9, a capacitor C2, and a third comparator CP3.
and the capacitor C2 constitute a charging/discharging section 7, and the resistors R8 and R9 constitute a third setting section 8, respectively. This charging/discharging section 7
charges and discharges the inverted count pulse S1', and its charging/discharging output S2 (charging voltage V3) is input to one input (+) of the third comparator CP3, and the third setting unit 8 is connected to the divided voltage V4. are outputted to the other input section (-) of the third comparator CP3 via the connection section between the resistors R8 and R9. In this case, the divided voltage V4 is the charging/discharging unit 7 when the timer time is set to zero.
The charging voltage is set slightly higher than the maximum charging voltage of the charging/discharging output S2. The third comparator CP3 compares the magnitudes of the voltages V3 and V4 input to both input parts, and when the pulse width and generation period of the inverted count pulse S1' become longer due to a longer timer setting time, the Since the voltage V3 sometimes exceeds the divided voltage V4 and sometimes falls below it, a state of V3>V4 and a state of V3<V4 occur, and a detection output S3 whose level is inverted is output.

The zero setting circuit 3 has a timer time of 1, for example.
In order to instantaneously output zero setting outputs S5 and S6 when zero setting is performed from a state set at time, it is configured with a D flip-flop FF2. The D flip-flop FF2 has a CK terminal connected to the Q of the RS flip-flop FF1 of the count pulse circuit 1 via an inverter IV.
' terminal and the D terminal is the third comparator CP3 of the detection circuit 2.
are connected to each other.

To explain the operation with reference to FIG. 2, it is assumed that the timer time is set to, for example, one hour by operating a timer time setting volume (not shown). In this case, the timing chart in FIG. 2 is on the ■ side. The resistance value of the variable resistor R1 is varied in conjunction with this setting volume. By varying this resistance value, the count pulse circuit 1 is sent from the Q' terminal of the RS flip-flop FF1 to the detection circuit 2 via the buffer amplifier BF1 to generate an inverted count having a pulse width and generation cycle as shown in the side (■) of FIG. Output pulse S1'.

In the detection circuit 2, the charging/discharging section 7 charges and discharges the inverted count pulse S1' and outputs the charging output S2 shown in FIG.
The charging voltage V3 is compared with the divided voltage V4 from the third setting section 8, and when the charging voltage V3 increases and V3>V4, it becomes a high level, and when the charging voltage V3 decreases, it becomes a high level. When V3<V4, the detection output S3 shown in FIG. 2, which changes to low level, is output. This comparison output S
3 is the D of the D flip-flop FF2 in the zero setting circuit 3.
given to the terminal. The D flip-flop FF2 responds to the count pulse S4 shown in FIG. S6 in FIG. 2 is outputted from the S5 and Q' terminals in (2), respectively. In this case, the fact that the levels of the outputs S5 and S6 are inverted at time t1 indicates the point in time when the zero setting is canceled when the timer time is set from zero to one hour.

After the timer time is set to one hour in this way, the timing chart in FIG. 2 shows the case where the timer time is reset to zero. First, when the timer time setting volume is operated to set the timer time to zero, the resistance value of the variable resistor R1 is varied to, for example, zero. By adjusting the resistance value to zero, the count pulse circuit 1 is connected to the detection circuit 2 via the buffer amplifier BF1.
The pulse width and generation period of the inverted count pulse S1' change rapidly as shown in FIG. In the detection circuit 2, the charging/discharging output S2 of the charging/discharging section 7 becomes as shown in FIG. With respect to the divided voltage V4 of the zero setting circuit 3, V3<V4, and the detection output S3 from the third comparator CP3 remains at a low level as shown in FIG. In FF2, the S shown in Figure 2■ is connected to its CK terminal.
Even if the count pulse S4 of 4 is given as a clock, the Q terminal changes from high level to low level at time t2, and the Q' terminal changes from low level to high level at the same time t2. Zero setting output S5, S
It will be output as 6.

Embodiment 2 FIG. 3 is a circuit diagram of an electronic timer according to Embodiment 2 of the present invention, and FIG. 4 is a timing chart for explaining the operation of Embodiment 2. Components corresponding to those in FIGS. 1 and 2 are designated by the same reference numerals, and descriptions of the components corresponding to the same reference numerals will be omitted.

In the electronic timer of the second embodiment, the charging/discharging section 7 of the detection circuit 2 includes, in addition to the resistor R7 and the capacitor C2, a diode D1 in series with the resistor R7 and a resistor in parallel with the capacitor C2. It is characterized by a configuration in which R10 are connected to each other.

In this second embodiment, this detection circuit 2
When the third comparator CP3 sets the timer time to zero, the charging voltage V3 of the charging/discharging output S2 of the charging/discharging section 7 compares with the divided voltage V4 of the third setting section 8 and becomes V3>V4. , As a result, the third comparator CP3 outputs a high-level detection output S3 as shown in FIG. therefore,
The D flip-flop FF2 of the zero setting circuit 3 changes from a low level to a high level at time t2 from the Q terminal as shown in S5 in FIG. It outputs zero setting outputs S5 and S6 that change from low level to low level.

[0030] Note that the explanation of ① and ② in Fig. 4 showing a timing chart for explaining the operation of the second embodiment is omitted because it is basically the same as ② and ② in Fig. 2 .

In this manner, in each of the embodiments described above, when the generation period of the count pulse is shortened by the zero setting operation of the timer time, the outputs S5 and S6 can be outputted to instantaneously set the timer time to zero. .

[0032]

[Effect of the invention] As is clear from the above explanation,
According to the present invention, the count pulse circuit outputs count pulses whose pulse width and generation cycle become shorter as the timer time setting becomes shorter, and the detection circuit outputs count pulses whose pulse width and generation cycle become shorter as the timer time setting becomes shorter. In the zero setting output circuit that detects and outputs the generation cycle,
Since the timer time zero setting output is output in response to the input of the detection output when the timer time is set to zero, the timer time can be instantaneously and easily set to zero. Therefore, even if the count value until the counter counts up is large for a timer with long-duration specifications, the timer time can be instantly set to zero by operating the setting volume, and, for example, the sequence of equipment using this timer can be set to zero by operating the setting volume. Operation checks can be performed in a short time.

[Brief explanation of the drawing]

FIG. 1 is an electrical circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is an electric circuit diagram according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the second embodiment.

FIG. 5 is an electric circuit diagram according to a conventional example.

FIG. 6 is a timing chart for explaining the operation of a conventional example.

[Explanation of symbols]

1 Count pulse circuit 2 Count pulse output cycle detection circuit 3
Zero setting output circuit

Claims (1)

[Claims] Claim 1: A count pulse circuit (1) and a detection circuit (
2) and a zero setting circuit (3), the count pulse circuit (1) outputs count pulses whose generation cycle becomes shorter as the timer time setting becomes shorter; The detection circuit (2) detects and outputs the generation cycle of count pulses when the timer time is set to zero, and the zero setting circuit (3) detects and outputs the generation cycle of the count pulse when the timer time is set to zero. An electronic timer characterized in that it outputs a timer time zero setting output in response.