JPH04346465A - Output circuit of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable an output circuit to operate at a high speed and output signals free from ringing noises. CONSTITUTION:An NMOS transistor 9 large in gm and Vth, an NMOS transistor 10 small in gm and Vth, a PMOS transistor 12 large in gm and Vth, an NMOS transistor 13 small in gm and Vth, and an NMOS transistor 14 large in gm and small in Vth are provided.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applicable to semiconductor storage devices, etc.
The present invention relates to an output circuit of a semiconductor integrated circuit device (hereinafter referred to as LSI).

0002

2. Description of the Related Art Conventionally, an LSI whose main part is shown in FIG. 3 has been known. In the figure, 1 is the LSI main body,
2 is an internal circuit, D1 and D2 are signals output from the internal circuit 2, 3 is an output circuit, and in this output circuit 3, 4 and 5 are nMOS transistors, and 6 is a power supply voltage V.
7 is an output terminal, and DOUT is the output of the output circuit 3.

In the output circuit 3 of this LSI, when the signals D1 and D2 are both at the L level, the nMOS transistors 4 and 5 are both turned off, and the output state becomes a high impedance (Hi-Z) state. Further, when the signal D1 is at the H level and the signal D2 is at the L level, the nMOS transistor 4 is turned on, the nMOS transistor 5 is turned off, and the output DOUT is at the H level. In addition, the signal D1
is at L level and signal D2 is at H level, nMO
The S transistor 4 is turned off, the nMOS transistor 5 is turned on, and the output DOUT becomes L level.

Here, conventionally, an nMOS transistor 4,
5 has a high mutual conductance (hereinafter referred to as gm), and is able to achieve high-speed operation even under the worst usage conditions of high load, high temperature, and low voltage.

[0005]

However, such an output circuit 3 has a problem in that noise is generated under conditions of light load, low temperature, and high voltage. That is, when the output DOUT is changed from a high impedance state to an H level, and when the output DOUT is changed from a high impedance state to an L level, as shown in FIG.
There is a problem in that ringing occurs and this becomes noise.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide an LSI output circuit which is capable of increasing the speed and obtaining an output signal that does not include noise due to ringing.

[0007]

[Means for Solving the Problems] An LSI output circuit according to the present invention includes a pull-up circuit between one power supply and an output terminal, and a pull-up circuit between the output terminal and the other power supply having a lower voltage than the one power supply. However, in the present invention, the pull-up circuit includes at least a first MOS transistor with a relatively large gm and a first MOS transistor with a relatively small gm and a Vth. the first M
When a second MOS transistor smaller than the OS transistor is provided and the output is set from the L level or high impedance state to the H level, the output first becomes exclusively g.
The characteristic is that m rises steeply depending on the rise characteristics of the first MOS transistor where gm is relatively large, and then gradually rises depending on the rise characteristics of the second MOS transistor where gm is relatively small. Ru. Also,
The pull-down circuit includes at least a third MOS transistor with a relatively large gm and a third MOS transistor with a relatively small gm;
and a fourth MOS transistor whose Vth is smaller than that of the third MOS transistor, and when setting the output from the H level or high impedance state to the L level, the output is first limited to the fourth MOS transistor whose gm is relatively large. Third
It is assumed that gm falls sharply depending on the falling characteristic of the fourth MOS transistor, and then gradually falls depending on the falling characteristic of the fourth MOS transistor whose gm is relatively small.

[0008]

[Operation] In the present invention, when setting the output from an L level or a high impedance state to an H level, the output first rises steeply depending solely on the rise characteristics of the first MOS transistor, which has a relatively large gm. After that, gm gradually rises depending on the rising characteristics of the second MOS transistor, which is relatively small, so that ringing can be suppressed. When setting the Vth of the first MOS transistor so that the value of "Vth" becomes approximately the H compare level, the time required to reach the H level can be shortened. That is, it is possible to speed up the setting of the output from the L level or high impedance state to the H level.

[0009] Furthermore, when setting the output from an H level or a high impedance state to an L level, the output first drops steeply depending solely on the falling characteristic of the third MOS transistor, which has a relatively large gm. and then g
Since m falls slowly depending on the falling characteristic of the fourth MOS transistor, which is relatively small, the occurrence of ringing can be suppressed, and the Vth of the third MOS transistor can be set to approximately the L compare level. In this case, the time required to reach the L level can be shortened. That is, it is possible to speed up the setting of the output from the H level or high impedance state to the L level.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and redundant explanation thereof will be omitted.

FIG. 1 is a diagram showing a main part of an LSI provided with an output circuit according to an embodiment of the present invention. In the figure, numeral 8 indicates an output circuit according to the present embodiment. The circuit 8 is n
Pull-up circuit 1 consisting of MOS transistors 9 and 10
1, and a pull-down circuit 15 consisting of a pMOS transistor 12 and nMOS transistors 13 and 14.

Here, the nMOS transistor 9 has gm
is large, and Vth is also large. Specifically, it is formed so as to exhibit a rise characteristic as shown by a solid line 16 in FIG. That is, the nMOS transistor 9 has a Vcc-Vth of H compare level 2.4[
Vth is set to a level slightly higher than V], and the size is such that it rises steeply until it reaches Vcc-Vth.

[0013] Furthermore, the nMOS transistor 10 has gm
is small, and Vth is also small. Specifically, it is formed so as to exhibit a rise characteristic as shown by a solid line 17 in FIG. That is, the nMOS transistor 10 has Vth set so that Vcc-Vth is a level slightly lower than Vcc, and Vcc-Vth.
The size is such that it rises slowly until it reaches th.

Therefore, the pull-up circuit 11 shown in FIG.
As shown by the solid line 18, there is a steep rise up to "Vcc-Vth of the nMOS transistor 9", and after that,
The characteristic is that the voltage gradually rises until it reaches "Vcc-Vth of the nMOS transistor 10".

Furthermore, the pMOS transistor 12 has gm
is large, and Vth is also large. Specifically, it is formed so as to exhibit a falling characteristic as shown by a solid line 19 in FIG. That is, the pMOS transistor 12 is set so that Vth is a little higher than the L compare level 0.4 [V], and the Vt
The size is such that it falls sharply until it reaches h.

Furthermore, the nMOS transistor 13 has gm
is small, and Vth is also small. Specifically, it is formed to exhibit a falling characteristic as shown by a solid line 20 in FIG. That is, the nMOS transistor 13 is set so that Vth is approximately 0 [V], and is sized so that it gradually falls until it reaches 0 [V].

Furthermore, the nMOS transistor 14 is a pMOS transistor.
It is provided as a load to prevent the S transistor 12 from latch-up and to set a high impedance state, and gm is set so as not to affect the falling characteristics of the pull-down circuit 15. It is formed so that Vth is large and Vth is small.

Therefore, the pull-up circuit 15 shown in FIG.
As shown by a solid line 21 in FIG. 1, the voltage falls sharply up to the Vth of the pMOS transistor 12, and then falls slowly down to 0 [V].

In the output circuit 8 of this embodiment configured as described above, when both the signals D1 and D2 are at L level,
The nMOS transistors 9, 10, 13, and 14 are turned off, and the output DOUT becomes a high impedance state. Furthermore, when the signal D1 is at the H level and the signal D2 is at the L level, the nMOS transistors 9 and 10 are turned on, and the pMOS transistors are turned on.
S transistor 12 and nMOS transistor 13, 1
4 is turned off, and the output DOUT becomes H level. Furthermore, when the signal D1 is at the L level and the signal D2 is at the H level, the nMOS transistors 9 and 10 are turned off, and the pMOS transistors are turned off.
S transistor 12 and nMOS transistor 13, 1
4 is turned ON, and the output DOUT becomes L level.

Here, when the output DOUT is set from the high impedance state to the H level, that is, when the pull-up circuit 11 is turned on, the output DOUT rises according to the characteristic shown by the solid line 18 in FIG. That is, from the high impedance state to "Vcc-Vth of the nMOS transistor 9", it depends solely on the nMOS transistor 9 and rises steeply to the H level value, and after that, the nMOS transistor 9
It rises gradually depending on the S transistor 10. Therefore, by increasing the gm of the nMOS transistor 9, H
Even if the rise time until reaching the level value is shortened, ringing will not occur.

Further, when setting the output DOUT from the high impedance state to the L level, that is, when turning on the pull-down circuit 15, the output DOUT falls according to the characteristic shown by the solid line 21 in FIG. That is, the Vth of the pMOS transistor 12 changes from the high impedance state to
Until then, it depends solely on the pMOS transistor 12 and steeply drops to the L level value, and after that it depends on the nMOS transistor 13 and gradually drops. Therefore, even if the gm of the pMOS transistor 12 is increased and the fall time until reaching the L level value is shortened, ringing will not occur.

As described above, according to this embodiment, it is possible to suppress the occurrence of ringing when pulling up, and to shorten the time required to reach the H level value, and also to reduce ringing when pulling down. Since it is possible to suppress the occurrence of the noise and to shorten the time required to reach the L level value, it is possible to increase the speed and obtain an output signal that does not include noise due to ringing.

[0023]

[Effects of the Invention] According to the present invention, it is possible to suppress the occurrence of ringing when pulling up, shorten the time required to reach the H level value, and also reduce the occurrence of ringing when pulling down. Since it is possible to suppress the noise and to shorten the time required to reach the L level value, it is possible to increase the speed and obtain an output signal that does not include noise due to ringing.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a main part of an LSI provided with an output circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of an output circuit according to an embodiment of the present invention.

FIG. 3 is a diagram showing a main part of an LSI using a conventional output circuit.

FIG. 4 is a time chart for explaining problems with a conventional output circuit.

[Explanation of symbols]

11 Pull-up circuit 15 Pull-down circuit

Claims (1)

[Claims] 1. A semiconductor comprising a pull-up circuit provided between one power supply and an output terminal, and a pull-down circuit provided between the output terminal and another power supply having a lower voltage than the one power supply. In the output circuit of the integrated circuit device, the pull-up circuit includes at least a first MOS transistor having a relatively large transconductance, and a first MOS transistor having a relatively small transconductance and a threshold voltage lower than that of the first MOS transistor. When a second MOS transistor is provided and the output is set from an L level or a high impedance state to an H level, the output is first set exclusively from the first MOS transistor having a relatively large mutual conductance.
The pull-down circuit has a characteristic in which the voltage rises steeply depending on the rising characteristics of the OS transistor, and then gradually rises depending on the rising characteristics of the second MOS transistor whose mutual conductance is relatively small.
At least a third MOS transistor having a relatively large mutual conductance and a fourth MOS transistor having a relatively small mutual conductance and a threshold voltage lower than that of the third MOS transistor are provided, and the output is set to an H level or When setting from a high impedance state to an L level, the output first drops steeply depending solely on the falling characteristic of the third MOS transistor having a relatively large mutual conductance, and then,
An output circuit for a semiconductor integrated circuit device, wherein the mutual conductance has a characteristic that gradually decreases depending on the falling characteristic of a fourth MOS transistor having a relatively small value.