JP2611500B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to an output circuit of a semiconductor integrated circuit device.

[Prior Art] In recent years, with regard to semiconductor integrated circuit devices, large-capacity and high-density devices have been remarkably advanced, and high-speed operation has been strongly demanded.

As the operation speeds up, it becomes necessary to solve various problems in circuit design. Above all, the problem of the noise of the ground potential due to the inductance of the package, the bonding wire, and the like hinders the increase in speed. This will be described for a conventional high-speed semiconductor integrated circuit device with reference to the drawings.

FIG. 5 is a circuit diagram of an output circuit of a conventional semiconductor integrated circuit device, FIG. 6 (a) is the voltage of the output terminal of the circuit of FIG. 5, and FIG. 6 (b) is the circuit of the circuit of FIG. FIG. 4 is a waveform diagram of noise applied to a ground potential.

In FIG. 5, 1 is a data input terminal to which data δ is input, 2 is an output enable signal input terminal to which an output enable signal φ is input, 3 is an output terminal to which an output signal θ is output, and NR1 is Noah gate, ND1 is a NAND gate,
I1, I4, and I5 are inverters, Qp is a p-channel MOSFET (hereinafter, referred to as pMOS), and Qn is an n-channel MOSFET (hereinafter, nMOS).
Is written). In this circuit, when the output enable signal φ is at a high level, the pMOS Qp and the nMOS Qn are both turned off regardless of the value of the data δ, and the output terminal 3 is set to a high impedance state. When φ is at a low level, if data δ is “1”, pMOSQp is turned off, nMOSQn is turned on, and output signal θ is at a low level.
If the data δ is “0”, the pMOS Qp is turned on, the nMOS Qn is turned off, and the output signal θ becomes high level.

[Problems to be Solved by the Invention] Here, when the input / output level is the TTL level, the standard of the potential of the output terminal and the standard of the current flowing through the output terminal when the output signal is at the high level are 2.4 V and −, respectively. The specifications of the potential of the output terminal when the output signal is at a low level and the current flowing through the output terminal are 0.4 V and 8 mA, respectively.
In other words, the DC characteristic required for nMOSQn is that when the drain-source voltage is 0.4 V, the drain current is 8 mA, and for pMOSQp, the drain-source voltage is -2.6 V It can be said that the drain current is -4 mA. Therefore, assuming that the drain current / drain-source voltage ratio of each transistor is the capacity βQp and βQn of each transistor, the capacity ratio βQp / βQ
n may be βQp / βQn << 1. However, considering the difference in the data read time depending on the data, in the above setting, the read when the output is at the low level is fast, and the read when the output is at the high level is slow. For this reason, the capacity ratio is often set to approximately 1.
Therefore, the case of βQp / βQn = 1 is referred to as Conventional Example 1. However, under this condition, the output voltage and the output current when the output is at a high level become unnecessarily high, so that the noise of the ground potential becomes large and a malfunction easily occurs. The reason will be described below.

The output voltage waveform when the output voltage of the output circuit of Conventional Example 1 changes from high to low to high is as shown by a solid line in FIG. 6 (a). In the figure, Voh indicates the lowest voltage of the high-level output (standard value), and Vol indicates the highest value of the low-level output (standard value). Here, the current flowing through the nMOSQn and the pMOSQp causes a back electromotive voltage determined by the product of the time change rate of the current and the self-inductance due to the self-inductance component of the current path. The noise of the ground potential due to the back electromotive voltage is a maximum of | V1 | and | V2 | as shown by the solid line in FIG. 6 (b). It can be considered that the reference of the potential (ground level) is changing as shown in the figure.
The change in the ground potential at the time of the low-to-high transition of the output voltage is mainly a change in the power supply potential that appears on the ground side due to capacitive coupling.

By the way, the high level of the logic level standard of the input signal of the semiconductor integrated circuit device is VH, the low level is VL, the minimum potential at which the internal circuit can be detected as high is Vih, and the maximum potential at which the internal circuit can be detected as low is Is Vil, the relationship of VL ≦ Vil ≦ Vih ≦ VH holds. Here, since Vih and Vil are relative voltages inside the semiconductor, when the ground potential changes as described above, the noise shown in FIG. Vih minimum value Vi
The maximum value Vil 'of h' and Vil is Vih '= Vih- | V1 | Vil' = Vil- | V2 |. At this time, assuming that the level of the input signal is as specified, if | V1 | and | V2 | are large, the following relationship may hold.

Vih'≤VL Vil'≥VH This means that when the input signal is low level, the internal circuit is sensitive to high level, and when the input signal is high level, the internal circuit is sensitive to low level. And malfunction.

Next, as Conventional Example 2, the transistor capability ratio βQp
Consider the case where / βQn is less than one. In this case, since the high-level output decreases as indicated by the broken line in FIG. 6A, the amount of charge to be extracted by the nMOS Qn decreases, and the current change rate during the period when the output voltage transitions from high to low decreases. Therefore, the noise at the ground potential can be suppressed to be lower than in the case of Conventional Example 1 as shown by the broken line in FIG. 6 (b). However, in this case, the low-to-high transition time of the output voltage increases due to the decrease in the current supply capability of the pMOS Qp, and the access time increases.

Instead of the above-mentioned means, there is also a method in which the waveform of the gate voltage of the output transistor is blunted, the rate of change in the output current is reduced, and the noises | V1 | and | V2 | are reduced. Increase is inevitable.

That is, in a conventional semiconductor integrated circuit device, when a transistor having a high ability is used in pursuit of high speed,
If the noise of the ground potential increases and there is a risk of malfunction, if the performance of the output transistor is reduced or the signal input to the gate of the output transistor is blunted to suppress this noise, high speed performance will be sacrificed. became.

Accordingly, it is an object of the present invention to reduce the noise level of an output circuit of an integrated circuit device without sacrificing high speed.

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention includes an output circuit whose output state is controlled by a data input signal or a data input signal and an output enable signal. First and second p-channel MOS transistors each having a drain connected to an output terminal;
An n-channel MOS transistor having a source grounded and a drain connected to the output terminal, and wherein the first p-channel MOS transistor can raise the voltage of the output terminal to a prescribed high potential. And the performance of the second p is reduced.
The channel MOS transistor is the first p-channel MOS transistor.
The gate voltage is controlled so that the transistor is turned on at the same time as the transistor and turned off after a certain time.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In this figure, the same parts as those of the conventional example shown in FIG. 5 are denoted by the same reference symbols, and the duplicate description will be omitted. In this embodiment, between the power supply and the output terminal 3,
The first pMOSQp1 and the second pMOSQp2 are connected in parallel. Among them, the first pMOSQp1 is a circuit connected at the same position as the pMOSQp in FIG. 5, and is an element having the same performance as the pMOSQp in the conventional example 2. That is, for the first pMOS Qp1, an element having an ability to allow the output level to slightly exceed the minimum voltage (standard value) Voh of the high-level output when conducting is used.

To the gate of the second pMOS Qp2, the output of the control signal generation circuit, which is composed of the NOR gate NR2, the inverters I2 and I3, the capacitor C1, and the NAND gate ND2, to which the data δ and the output enable signal φ are input is input.

Next, the operation of the circuit of FIG. 1 will be described with reference to FIG. 2, which is a waveform diagram of each part of the circuit of FIG.

Now, the output enable signal φ is at a low level. When the data δ is “1”, the nodes C, D, and E shown in FIG. 1 are each at a high level, Qn is on, and Qp1, Qp2 are off. At this time, the node A is at a low level and the node B is at a high level.

Here, when the data δ starts to change to “0”, the nodes C,
The potentials of D and E begin to fall with a delay of the delay time due to the NOR gate NR1, the inverter I4, and the like. At this time, since the potential of the node A gradually rises due to the action of the capacitor C1,
The potential at the node B remains high for a certain period of time. When the potentials of the nodes C, D, and E decrease to a certain level, the first and second pMOSs Qp1 and Qp2 start conducting, the on-current of the nMOS Qn starts to decrease, and the output signal θ starts to rise. Also,
When the potential of the node A reaches a certain potential, the potential of the node B starts to decrease. When the potential of the contact B drops to a certain point,
The potential at the node D starts to rise again. When the potential at the node D reaches a certain value, the second pMOS Qp2 is turned off. pMO
The capacitance of the capacitor C1 and the characteristics of the pMOS Qp2 are determined so that the SQp2 is turned off when the output signal exceeds the standard value (lowest value) Voh of the high-level output. After that, the output signal θ slightly increases, but eventually the output becomes
It settles down to a level lower than the power supply voltage V _DD determined by the capability of pMOSQp1.

Next, when the data δ changes to “1”, the potentials of the nodes C and E rise with a slight delay, and the output signal θ starts to fall. The potential at the node B rises with a delay of the delay time determined by the inverter 12 and the capacitor C1, but when the potential at the node B goes high, the output of the NOR gate NR2 is already at the low level. Remains at the high level. That is, the data δ changes from “0” to “1”
Even if it changes, the second pMOS Qp2 does not conduct.

The above operation will be summarized with reference to the output waveform diagram shown in FIG. At the time of the high-to-low transition of the output signal θ, the operation is faster than that of the conventional example 1 in order to extract a small amount of charge by the nMOS having a high capability.
Since the amount of charge to be extracted itself is reduced, the fluctuation of the ground potential at this time is suppressed accordingly.
Also, when the output signal θ transitions from low to high, the first and second pMOSs Qp1 and Qp2 are initially turned on, so that the output signal θ quickly rises in the same manner as in the conventional example 1. When it exceeds Voh, the second pMOS is cut off,
Since the battery is charged only by the first pMOS having a low capacity, the rise becomes gentle. And at that time the second
In this case, the pMOS is turned on for a short time, and the final value of the high level is kept lower than that of the first conventional example, so that the ground noise is also suppressed in this case.

FIG. 4 is a circuit diagram showing another embodiment of the present invention.
The difference between this embodiment and the previous embodiment is that the second pMOSQ2
In the control signal generation circuit for forming a control signal to the gate of the above, a NOR gate N3 to which an output enable signal φ and data δ are input is used instead of the inverter I2. With this configuration, in the present embodiment, the second pMOS Qp conducts for a certain time even when the data δ is at the high level and the output enable signal φ changes from high to low level.

[Effects of the Invention] As described above, in the present invention, in a CMOS type output circuit, a pMOS section is formed by a parallel circuit of two pMOSs, and one of the pMOSs is made to conduct constantly only at the time of output rise. Therefore, the following effects can be obtained.

When the output transitions to the high level, the two pMOSs are turned on, so that the output rising speed can be increased.

When the output transitions to the high level, the two pMOSs are turned on for a short period of time, and the maximum value of the high level is reduced, so that the ground potential noise at this time is suppressed.

The transition of the output to low level is made by a high-capacity nMOS, and the amount of charge to be extracted by this transistor is reduced, so that the output rises faster and the ground potential noise at this time is reduced. Is done.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG.
FIG. 3 is a waveform diagram of each part of the circuit of FIG. 1, FIG. 3 is an output waveform diagram of the embodiment of FIG. 1 in comparison with a conventional output waveform diagram, and FIG. 4 is a circuit diagram of another embodiment of the present invention. FIG. 5 is a circuit diagram of a conventional example, FIG. 6 (a) is an output waveform diagram of the conventional example, and FIG. 6 (b) is a noise waveform diagram of the ground potential in the conventional example. 1 ... data input terminal, 2 ... output enable signal input terminal, 3 ... output terminal, Qp1, Qp2, Qp ... p-channel MO
S transistor (pMOS), Qn: n-channel MOS transistor (nMOS), A to E: nodes, I1 to I5 ... inverter, C1 ... capacitor, ND1, ND2 ... NAND gate, NR
1 to NR3: NOR gate, Voh: Highest output minimum voltage (standard value), δ: Data, φ: Output enable signal, θ: Output signal.

Claims (2)

(57) [Claims] 1. An output circuit whose output state is controlled by a data input signal, the output circuit comprising: an n-channel MOS transistor having a source grounded and a drain connected to an output terminal; Are connected to the output terminal, a first p-channel MOS transistor having a drain current / (drain voltage-source voltage) lower than that of the n-channel MOS transistor,
Connected in parallel with the p-channel MOS transistor of
A p-channel MOS transistor, wherein the n-channel MOS transistor and the first p-channel MOS transistor each receive the data input signal or an output signal of a logic circuit to which the data input signal is input. The second p-channel MOS transistor receives the data input signal and a signal of the data input signal via a delay circuit that delays the signal by a predetermined time. The first p channel according to the output signal of the logic circuit
A semiconductor integrated circuit device wherein the MOS transistor is turned on at the same time as the MOS transistor being turned on, and is controlled so as to be turned on at the same time and to be turned on for a certain period of time determined by the delay circuit. 2. An output circuit whose output state is controlled by a data input signal and an output enable signal, the output circuit comprising: an n-channel MOS transistor having a source grounded and a drain connected to an output terminal; And the drain is connected to the output terminal, and the drain current / (drain voltage−source voltage) is equal to the n-channel.
A semiconductor integrated circuit device comprising: a first p-channel MOS transistor lower than that of a MOS transistor; and a second p-channel MOS transistor connected in parallel with the first p-channel MOS transistor. The n-channel MOS transistor and the first p-channel MOS transistor are driven by an output signal of a logic circuit to which the data input signal and the output enable signal are input, respectively, when the output enable signal is at a high level. When the output enable signal is at a low level, only one of the transistors is controlled to be conductive, and the second p-channel MOS transistor holds the data input signal of the data input signal for a predetermined time. A signal passed through a delay circuit for delaying, the data input signal, and the output enable signal Is turned off when the output enable signal is at a high level, and is turned on simultaneously when the first p-channel MOS transistor is turned on when the output enable signal is at a low level. The semiconductor integrated circuit device is controlled so that the conduction is continued for a predetermined time determined by the delay circuit.