JPH04345369A - Picture data encoder - Google Patents

Abstract

PURPOSE:To obtain a picture data encoder which operates an optimal bit assignment to make a quantization error minimum under decided information amounts. CONSTITUTION:One screen picture data are divided into plural blocks by a block circuit 102, an orthogonal transformation is operated by an orthogonal transformation circuit 103, the number of bits is assigned so that the picture data amounts for one frame can be constant by a bit assigning circuit 104, the bit is assigned to the conversion factor of each block according to a variance within the range by a bit assigning circuit 105, a quantization index is prepared according to this by a quantizing circuit 106, and the data are encoded by an encoding circuit 107. The received code is decoded by a decoding circuit 109, the quantization index is inverse quantized by an inverse quantizing circuit 111 in order to restore the conversion factor from the prescribed additional information of a bit assigning circuit 110 and the assigned number of bits of the conversion factor based on this, an inverse orthogonal transformation is operated by an inverse orthogonal transformation circuit 112 in order to restore the picture data, and the blocks are decomposed by a block decomposing circuit 113 in order to reproduce the original picture data for one screen.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data encoding apparatus for encoding image data and transmitting and receiving the encoded image data via a transmission medium.

0002

[Background Art] Conventionally, in order to keep the transmission rate of image data constant, image data is quantized at a predetermined quantization step, the amount of information is calculated, and quantization is performed so that this becomes a target value. A so-called feedback method is used in which the step is changed and the quantization is re-performed. However, with this method, it is difficult to accurately control the amount of information in the case of moving images that require real-time processing, and is particularly unsuitable for package media devices such as digital VTRs.

[0003] Therefore, a feedforward encoding method has been proposed, which makes it relatively easy to keep the amount of information constant within a certain range of image data. Examples include an ADRC method and a method using transform coding. The ADRC method is
This is a block-adaptive encoding method in which the average number of bits allocated to each block is adaptively allocated to each block while keeping the bit rate constant, depending on the dynamic range of each block of divided image data. In addition, in a method using transform coding, the bit allocation for each coefficient is generally determined for the transform coefficients obtained by orthogonally transforming image data so as to keep the bit rate constant and minimize the quantization error. Coefficient adaptive encoding methods are known.

0004

[Problem to be Solved by the Invention] However, since the ADRC method uses the dynamic range of blocks as described above, the accuracy of bit allocation to each block is lower than when using statistics such as variance. is low, and optimal bit allocation is not performed for transform coefficients within the block. On the other hand, in the method using transform coding, although adaptive bit allocation is performed for transform coefficients, bit allocation to each block is not considered. Therefore, it cannot be said that optimal bit allocation is necessarily performed in either method.

An object of the present invention is to solve such problems and provide an image data encoding device capable of optimal bit allocation that minimizes quantization errors under a predetermined amount of information. be.

[0006]

[Means for Solving the Problems] The above objects of the present invention are as follows:
A blocking unit divides image data for a screen into a plurality of blocks, an orthogonal transformation unit performs orthogonal transformation on the image data for each block to obtain transformation coefficients, and a block unit divides the image data for each block into a plurality of blocks. a first bit allocation means that allocates the number of bits to each block according to the statistics of the transform coefficients of each block so as to be constant; and a second bit allocator that allocates bits to each transform coefficient within the range of the number of bits allocated for each block; 2 bit allocation means, quantization means that quantizes the transform coefficient in a quantization step according to the number of allocated bits and creates a quantization index, and encodes the created quantization index and quantizes it along with additional information. an encoding means for transmitting at a bit rate; a decoding means for decoding the code received from the encoding means to restore a quantization index; and assignment of each transform coefficient based on the restored quantization index and the additional information. a third bit allocation means for determining the number of bits; and a dequantization means for dequantizing the quantization index and restoring the transform coefficient based on the decoded quantization index, the additional information, and the allocated number of bits. , an inverse orthogonal transform means for restoring image data block by block by performing inverse orthogonal transform on the restored transform coefficients, and a block for decomposing the blocks and reproducing one screen's worth of image data from the restored image data. This is achieved by an image data encoding device characterized by comprising decomposition means.

[0007]

[Operation] When image data is input, the blocking means first divides the input image data for one screen into multiple blocks, and the orthogonal transformation means performs orthogonal transformation on the image data for each block. Find orthogonal transformation coefficients. Based on the transform coefficient, the first bit allocation means assigns bits according to statistics such as the variance of each block so that the amount of information of the image data in a predetermined size area (for example, one frame) is constant. Assign a number to each block. Further, the second bit allocation means allocates bits to each transform coefficient for each block within the range of the number of bits allocated by the first bit allocation means. The quantization means quantizes the transform coefficient at a quantization level corresponding to the number of bits allocated by the second bit allocation means, and creates a quantization index. The quantization index is encoded by the encoding means and sent to the transmission medium at a constant bit rate.

The code received via the transmission medium is decoded by the decoding means, and the third bit allocation means first determines the number of bits to be allocated to the transform coefficient based on the quantization index and predetermined additional information. The dequantization means dequantizes the quantization index based on the additional information and the number of allocated bits determined by the third bit allocation means. The inverse orthogonal transform means performs inverse orthogonal transform on the result to restore image data. The block decomposition means decomposes the blocks and reproduces image data for one screen.

[0009]

[Example] Next, an example of the present invention will be described. Figure 1
1 is a block diagram of an embodiment of an image data encoding device according to the present invention. For example, digital data of a video image with 8 bits per sample is input to the input terminal 101 . When the blocking circuit 102 receives this digital image data, it divides it into a plurality of blocks each having a size of, for example, 8 pixels x 8 pixels.

The orthogonal transform circuit 103 receives the image data thus divided into blocks, and performs two-dimensional orthogonal transform on each block. The resulting transform coefficients are then supplied to a bit allocation circuit 104 that allocates bits to each block and a delay circuit 115. The orthogonal transform method used in the orthogonal transform circuit 103 is DCT (discrete cosine transform), DST (discrete sine transform), Hadamard transform, etc. However, when the bit allocation circuit 104 uses block-by-block variance,
A method such as DCT that can calculate the variance of image data from transform coefficients is used. If that is not possible,
The bit allocation circuit 104 is placed before the orthogonal conversion circuit 103 instead of after the conversion circuit 103, or before the conversion circuit 103.
placed in parallel with However, in this case, the circuit scale of the bit allocation circuit 104 becomes a little larger because an additional task of calculating the average value for each block is added to the part that calculates the variance.

[0011] When the bit allocation circuit 104 receives the transform coefficients from the transform circuit 103, it first calculates the average value for each block, and when the variance values of the blocks within a certain range (for example, one frame) are totaled, the above-mentioned The average number of bits (average bit length) to be allocated to each block is determined according to the variance value so that the amount of information of image data within a certain range becomes a predetermined value. Note that the value of the amount of information is determined in advance by calculating backward from the required bit rate. Bit allocation circuit 104 supplies the number of bits to be allocated to each block to bit allocation circuit 105 and delay circuit 117, which allocate bits to each transform coefficient. In this embodiment, the variance of image data is used as a criterion for allocating bits to blocks, but it is also possible to use the dynamic range of image data. In that case, the allocation circuit 1
04 does not necessarily need to be placed after the conversion circuit 103, nor does it need to supply conversion coefficients.

Bit allocation circuit 105 receives the average number of bits allocated to each block from bit allocation circuit 104, while receiving transform coefficients from delay circuit 115. The bit allocation circuit 105 first extracts transform coefficients for each frequency component from each block, calculates their average and variance, and according to the calculated variance, within the range of the average number of bits allocated to each block, Calculate the number of bits to allocate to each transform coefficient. The bit allocation circuit 105 converts the average and variance of the calculated orthogonal transform coefficients into the quantization circuit 10.
6 and the delay circuit 118, and also supplies the number of bits to be assigned to each coefficient to the quantization circuit 106.

The quantization circuit 106 includes the bit allocation circuit 10
The transform coefficients supplied from the transform circuit 103 via the delay circuits 115 and 116 are quantized based on the average, variance, and number of allocated bits sent from the transform circuit 103. The quantization circuit 106 first calculates the quantization step size of each transform coefficient using the number of bits allocated to each transform coefficient and the variance. At this time, for example, the quantization step size for the input of the Laplace distribution with variance 1 is set as the standard step size, and the step size is determined by multiplying this by the variance. Thereafter, the transform coefficients are quantized using the determined quantization step size, a quantization index is created, and the generated quantization index is supplied to the encoding circuit 107. Note that it is also possible to use different quantization methods for the AC component and the DC component of the transform coefficient.

The encoding circuit 107 receives the quantization index output from the quantization circuit 106, the number of bits allocated to each block output from the delay circuit 117 as additional information, and each transform coefficient output from the delay circuit 118. The mean and variance of are encoded and the results are supplied to the transmission medium (or recording medium) 108. Various encoding methods can be used, but the required conditions are that the encoding is reversible and that the bit rate can be kept constant. Note that, in reality, a transmission path encoding circuit (not shown) is provided between the encoding circuit 107 and the transmission medium 108 for the purpose of error correction and the like.

Data from the transmission medium 108 is supplied to a decoding circuit 109 via a transmission path decoding circuit (not shown). The decoding circuit 109 restores the quantization index, the number of bits allocated to each block, and the average and variance of each transform coefficient from the encoded data by performing an operation opposite to that of the encoding circuit 107, and converts the blocks and transform coefficients into The signal is supplied to a bit allocation circuit 110 and a delay circuit 119 which allocate bits to each other. Note that the encoding circuit 107 and the decoding circuit 109 can also be omitted.

The bit allocation circuit 110 is connected to the decoding circuit 109.
The number of bits allocated to each transform coefficient is calculated based on the number of bits allocated to each block from , and the variance of each transform coefficient, and is supplied to the inverse quantization circuit 111 .

The inverse quantization circuit 111 is a bit allocation circuit 1
Dequantize the quantization index from the delay circuit 119 using the number of bits assigned to each transform coefficient from 10 and the average and variance of the transform coefficient from the delay circuit 119,
The orthogonal transform coefficients are restored and supplied to the inverse orthogonal transform circuit 112.

The inverse orthogonal transform circuit 112 is the orthogonal transform circuit 1
03, the inverse quantization circuit 11
The block decomposition circuit 113 restores the blocked image data from the transform coefficients starting from 1, converts it back into normal image data before blocking, and outputs it to the output terminal 114.

Note that the delay circuits 115 to 119 are specifically constituted by frame memories or the like.

Next, each bit allocation circuit 104, 105,
110 will be explained in more detail.

First, the bit allocation performed by these circuits will be theoretically explained. When allocating bits to transform coefficients, for example, a large number of bits are assigned to transform coefficients with a large variance, and a small number of bits are assigned to transform coefficients with a small variance, so that the overall amount of data is encoded using a small amount. A bit allocation theory such as is used.

[0022]

[Math 1]

Here, b(i) is the number of bits allocated to the i-th transform coefficient, σ(i) is the variance of the i-th transform coefficient, bavr is the average number of bits, N is the total number of transform coefficients, and a is a constant. It is.

By the way, although equation (1) is an equation that holds true regarding bit allocation of transform coefficients, it is also possible to use this equation for bit allocation of blocks. In that case, b(i) is the number of bits allocated to the i-th block, σ(i) is the variance of the i-th block, and bavr is 1
The average number of bits per block (the total amount of information divided by N), where N is the total number of blocks.

Equation (1) can be rewritten as follows, and as a result, bit allocation can be performed more easily.

[0026]

[Math 2]

Here, f(i) indicates the number of allocated bits before adding the condition of equation (2c), and b(i) indicates f(i)
is converted into an integer. Q(x) is an integerization function as shown in the graph of FIG.

The feature of bit allocation based on formulas (2a) to (2c) is that the total number of bits is expressed as a function of A, so the number of bits can be easily controlled by changing the value of A, and the value of A can be easily controlled by changing the value of A. After that, b(i) can be easily obtained according to equations (2a) and (2b).

FIG. 2 shows an example of a circuit that allocates bits based on this method. This circuit will be explained below.

A dispersion value is input to the input terminal 201. The value of this variance is calculated by the activity of the alternating current component of the orthogonal transform coefficient in the bit assignment circuit 104 that allocates bits to blocks, and the bit assignment circuit 105 that allocates bits to the transform coefficient assigns the orthogonal transform coefficient from each block to the same frequency component. It is calculated after taking out each time and finding an average value, and is also given as an input to the bit allocation circuit 110.

The A(i,j) calculation circuit 202 first calculates g(i) using the above equation (2a) from the value of the variance from the input terminal 201, and then calculates A(i,j) using the following equation. demand.

[0032]

[Math 3]

Here, A(i,j) is, as shown in FIG. 4, when the value of b(i) is 1 when b(i) is a function of A.
The maximum and minimum bit numbers bmax and bmin to be allocated and the total number N of transform coefficients (or blocks) are set in advance. Note that when calculating g(i), the scale of the hardware can be reduced by performing the following conversion and then linearly approximating log2X.

[0034]

[Math 4]

After the above calculation, the calculation circuit 202 calculates A(i
, j) are supplied to the frequency distribution circuit 203, and the value of g(i) is supplied to the delay circuit 207.

The frequency distribution circuit 203 classifies the value of A(i,j) calculated by the calculation circuit 202 into several levels according to its size, calculates the frequency for each level, and finally calculates the cumulative frequency. Create a distribution. Strictly speaking,
Although A(i,j) should be sorted in order from smallest to largest, this is not practical when considering real-time processing by hardware. Therefore, for example, a simple method using frequency distribution is used.

The A determining circuit 204 is a frequency distribution circuit 203
Find the value of A using the cumulative frequency distribution created by If the total number of bits set is B, then it is necessary to increase the number of bits by n=BN-Nxbmin from the minimum number of bits, Nxbmin. Therefore, the value of A is determined by checking the point where the cumulative frequency is n in the cumulative frequency distribution.

[0038] Frequency distribution circuit 203 and A determination circuit 20
4 is realized using a RAM or the like. For example, the value of A is 25
When classifying into 6 levels, a RAM with an 8-bit address is used, and the value of A is associated with each RAM address. Then, a cumulative frequency distribution is created using this RAM, the address that includes the value of n is checked, and finally the value of A is calculated backward from that address.

The b(i) calculation circuit 205 is the A determination circuit 2
Using the value of A supplied from 04 and the value of g(i) supplied from the delay circuit 207, first f(
The value of i) is calculated, and then the value of b(i) is calculated from equation (2b). Then, the calculation result is outputted from the output terminal 206.

FIG. 5 shows a specific configuration of the circuit shown in FIG. 2. When timing pulse EN1 is input, register R1
takes in and holds the value bmin+1/2 output by the bit number circuit 501, and register R2 stores the value of bmin+1/2 output by the bit number circuit 501.
holds the value of j output by . Further, the register R4 holds the value of log2 (σ(i)2) outputted by the function circuit 504, and the register R5 holds the value of 1/a·1/log2e outputted by the constant circuit 505. adder 50
3 adds the values held in registers R1 and R2, and multiplier 506 calculates the product of the values held in registers R4 and R5. When timing pulse EN2 is input, registers R3 and R6 take in the outputs of adder 503 and multiplier 506, respectively. As a result, register R3 is
Holds the value of bmin+1/2+j, and register R6 holds g.
The value of (i) will be retained.

The subtracter 508 receives the b output from the register R3.
A(i,j) is obtained by subtracting the value of g(i) output from register R6 from the value of min+1/2+j (formula (3)). When timing pulse EN3 is input, this A(i, j) is taken into register R8, while the address conversion constant output from constant circuit 507 is taken into register R7. Multiplier 509 then performs address conversion by multiplying A(i,j) output from register R8 by the address conversion constant output from register R7, and obtains the address of the RAM. The result is held in register R9 when timing pulse EN4 is input, and is further provided to RAM 510. The frequency output by the RAM 510 at this time is held in the register R11 at the timing of the timing pulse EN4. The adder 513 receives the output from the constant circuit 512 and the register R.
14 is added to the frequency held in register R11, and the result is sent to R through register R12.
It is output to AM510 to update the value of the frequency distribution. still,
R10 is for clearing the contents of the RAM 510 and registers R11 and R13, and when the clear signal CLR is input, the value “0” received from the constant circuit 511 is sent to R10.
Input to AM510 and registers R11 and R13.

By performing the above operations for all i's, the frequency distribution is completed. Thereafter, a cumulative frequency distribution is created based on the frequency distribution, and in the process, the address of the RAM 510 that stores the cumulative frequency that matches the reference level n is detected. That is, the register R13 holds the value (cumulative frequency) output by the RAM 510 every time the timing pulse EN5 is input, and the comparator 515 stores that value and the constant circuit 514 held by the register R15.
The value of the reference level n from . If the comparison results do not match, the cumulative frequency counter 517 sets the value to 1.
register R16 provides it to RAM 510 as the next address. And comparator 51
If the comparison result of 5 is a match, the address output by the counter 517 is held in the register R17 by the timing pulse EN6. This address becomes the address of the RAM 510 that stores the cumulative frequency that matches the reference level n.

When timing pulse EN6 is input,
The address conversion constant from constant circuit 518 is stored in register R1.
8, and the multiplier 519 uses this constant and register R
The address is inversely converted by multiplying it by the address held by No. 17, and the value A is obtained. The value A is
When timing pulse EN7 is input, register R1
9 and the adder 520 receives the value A and the delay circuit 516
f(i) is obtained by adding g(i) given through (formula (2a)). Finally, the integerization circuit 521 converts this f
(i) is converted into an integer to obtain b(i) (formula (2b)).

[0044]

[Effects of the Invention] As explained above, in the image data encoding device of the present invention, block adaptive type and coefficient adaptive type bit allocation is performed, so that the quantization error can be minimized under a predetermined amount of information. Optimal bit allocation is possible. Furthermore, since feed-forward information compression using transform coding is performed, the amount of information can be accurately controlled even in the case of moving images that require real-time processing. Furthermore, since it can handle any transmission rate and keep the transmission rate constant within a fairly small range, it can be applied to any device that requires compression of image data, regardless of the type of transmission or recording medium. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of an image data encoding device of the present invention.

FIG. 2 is a block diagram of a bit allocation circuit of the image data encoding device of FIG. 1;

3 is a graph for explaining an integerization function Q(x) used in processing in the bit allocation circuit of FIG. 2; FIG.

FIG. 4 is a graph for explaining the (Ai, j) calculation circuit of FIG. 2;

FIG. 5 is a block diagram showing a specific configuration of the bit allocation circuit in FIG. 2;

[Explanation of symbols]

101, 201 Input terminal 102 Blocking circuit 103 Orthogonal transform circuit 104 Bit allocation circuit for blocks 105 Bit allocation circuit for coefficients 106 Quantization circuit 107 Encoding circuit 108 Transmission medium (recording medium) 109 Decoding circuit 110 To blocks and coefficients bit allocation circuit 11
1 Inverse quantization circuit 112 Inverse orthogonal transform circuit 113 Block decomposition circuits 114, 206 Output terminals 115 to 119, 207, 516 Delay circuit 202
A(i,j) calculation circuit 203 Frequency distribution circuit 204 A determination circuit 205 b(i) calculation circuit 501 Bit number circuits 505, 507, 511, 512, 514, 518
Constant circuit 502 J counter 503, 513, 520 Adder 504, 521 Function circuit 506, 509, 519 Multiplier 508 Subtractor 510 RAM 515 Comparator 517 Cumulative frequency counter R1 to R19 Register

Claims (1)

[Claims] 1. Blocking means for dividing image data for one screen into a plurality of blocks; orthogonal transformation means for orthogonally transforming the image data for each block to obtain transformation coefficients; a first bit allocation means that allocates the number of bits to each block according to the statistics of the transform coefficients of each block so that the number of bits is constant for each area of size; a second bit allocation means for allocating bits to coefficients; a quantization means for quantizing the transform coefficients in a quantization step according to the number of allocated bits to create a quantization index; a decoding means for decoding the code received from the encoding means and restoring a quantization index; a third bit allocation means for determining the number of allocated bits for each transform coefficient; and a third bit allocation means for dequantizing the quantization index to obtain a transform coefficient based on the decoded quantization index, the additional information, and the number of allocated bits. an inverse quantization means for restoring; an inverse orthogonal transform means for restoring image data block by block by performing inverse orthogonal transform on the restored transform coefficients; An image data encoding device comprising block decomposition means for reproducing image data.