JPH04344734A - Frame pattern detection circuit - Google Patents

Abstract

PURPOSE:To realize the frame pattern detection circuit operated at a high speed bit rate with high reliability independently of a frame pattern bit number by limiting a bit number inputted to the pattern detection circuit to a prescribed bit number. CONSTITUTION:The detection circuit is provided with a conversion means 101 converting a serial data into a parallel data, a 1st pattern detection means 102 detecting a 1st frame pattern from an output data from the conversion means 101, a frequency divider 105 whose phase is controlled by the detection means 102, a latch means 106 latching an output data of the conversion means 101, a 2nd pattern detection means 107 detecting a 2nd frame pattern, a 1st protection means 104 detecting that a 1st frame pattern is consecutive, and a 2nd protection means 108 detecting the consecutiveness of the 1st frame pattern and of the 2nd frame pattern in succession to the 1st frame pattern.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame pattern detection circuit, and more specifically to a frame pattern detection circuit advantageously applied to, for example, an octet multiplex frame synchronization circuit of a transmission device.

0002

2. Description of the Related Art FIG. 4 shows a conventional frame pattern detection circuit which receives an octet multiplexed serial signal and detects the frame pattern thereof. As shown in the figure, the conventional frame pattern detection circuit includes an n-bit shift register 401 composed of n-stage flip-flops, an n-bit pattern detection circuit 402, and a pattern matching signal output from the pattern detection circuit 402. It is composed of a flip-flop 403 that latches the . The pattern detection circuit 402 is an n-input, 1-output decoder, and is composed of a logic gate such as an OR gate or a NOR gate.

FIG. 5 shows an example of the structure of a frame pattern used for an octet multiplex frame. As shown in the figure, the frame pattern input to the frame pattern detection circuit includes an A pattern and a B pattern in units of 8 bits, each of which is arranged consecutively for m.

FIG. 10 shows a waveform diagram illustrating an example of the operation of the conventional technique shown in FIG. The operation when the value of m shown in FIG. 5 is set to 1 will be explained using the same figure and FIG. 4.

[0005] Serial data Di is stored in shift register 4
01, this register 401 shifts one bit at a time using the input clock Ci. The data flow at this time shifts from data Dn to D1, and the 16-bit frame pattern from A1 to B8 shown in FIG. 5 is input to the pattern detection circuit 402, which is a decoder. When the frame patterns A1 to B8 are input to the pattern detection circuit 402, the output “H” of the detection circuit 402 is sent to the flip-flop 403. Flip-flop 403 latches this output "H" using clock Ci, and outputs the result as a frame pattern matching signal.

[0006]

However, in such a conventional frame pattern detection circuit, since all bit frame patterns are detected simultaneously, the gate delay of the pattern detection circuit 402 increases in proportion to the number of bits of the frame pattern. . As a result, there is a problem in that the flip-flop 403 cannot correctly latch the pattern detection result outputted from the pattern detection circuit 402 using the clock Ci.

In order to solve the problem of the conventional technology that the gate delay of the pattern detection circuit increases in proportion to the number of frame pattern bits, the present invention reduces the number of bits input to the pattern detection circuit to a predetermined number of bits. It is an object of the present invention to provide a highly reliable frame pattern detection circuit that is independent of the number of frame pattern bits and can operate at a high bit rate.

[0008]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a frame pattern detection circuit which receives an octet multiplexed frame pattern and detects the frame pattern. The pattern detection means is divided and arranged for each octet pattern,
It has a protection means for detecting that the respective octet frame patterns are consecutive and that different patterns are consecutively lined up based on a detection signal from the pattern detection means.

[0009]

According to the present invention, the pattern detection means is divided into octets, and the protection means detects the continuity of each octet pattern and the juxtaposition of two consecutive patterns.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a frame pattern detection circuit according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, a circuit diagram showing one embodiment of a frame pattern detection circuit according to the present invention is shown. The frame pattern detection circuit 1 is a frame pattern detection circuit in an octet multiple frame synchronization circuit such as a transmission device, and includes a shift register 101, an A pattern detection circuit 102, a flip-flop 103, and a first protection circuit 10.
It is composed of a 4.1/8 frequency divider 105, a latch circuit 106, a B pattern detection circuit 107, and a second protection circuit 108.

The shift register 101 is a shift register that converts serial data into octet parallel data. That is, the shift register 101 receives input serial data Di, and latches and shifts this in accordance with the clock Ci. The shift register 101 includes a latch,
The shifted data is sent to A pattern detection circuit 102 and latch circuit 106.

The A pattern detection circuit 102 is a decoder composed of logic gates, and detects the A pattern among the frame patterns shown in FIG. The A pattern detection circuit 102 is connected to the flip-flop 103 and the 1/8 frequency divider via the signal line 110, and when the A1 pattern appears in the most significant bit MSB of the A pattern, the output 1
10 from "L" to "H".

The flip-flop 103 is a flip-flop that latches the output 110 from the A pattern detection circuit 102 using the input clock Ci (clock signal A). The flip-flop 103 has its output terminal Q
The latched signal C is output from this terminal Q.

The first protection circuit 104 detects the continuation of the A pattern matching signal using the output signal C from the flip-flop 103 and the clock F from the 1/8 frequency divider 105. The protection circuit 104 is connected to the second protection circuit 1 via the signal line G.
Connected to 08.

The 1/8 frequency divider 105 is a frequency divider controlled by the output 110 of the A pattern detection circuit 102 and the control signal Ei. The frequency divider 105 is connected to a latch circuit 106 via a signal line D, to a protection circuit 104 via a signal line F, and to a protection circuit 108 via a signal line G.

The latch circuit 106 includes the shift register 10
1/8 frequency divider 105
It is latched by the clock D outputted from. The latch circuit 106 is connected to the B pattern detection circuit 107 and also to the terminals D1 to D8.

The B pattern detection circuit 107 is a decoder composed of logic gates, and detects the B pattern. B pattern detection circuit 107 is connected to second protection circuit 108 via signal line H.

The second protection circuit 108 is a circuit that detects the output of the first protection circuit 104 indicating the continuation of the A pattern match signal and the subsequent continuation of the B pattern match signal. When the protection circuit 108 detects the continuous pattern of the A pattern and the B pattern, it outputs a match signal J.

FIG. 5 is a diagram showing an example of the structure of a frame pattern used in an octet multiplex frame. This figure shows a frame pattern configuration diagram when m A patterns and m B patterns each in 8-bit units are consecutively arranged. As shown in the figure, the above embodiment can be applied even when there are m A patterns and m B patterns in succession, but here, for ease of understanding, the value of m is assumed to be 1. The operation of the frame pattern detection circuit 1 in this case will be explained using the waveform diagram of FIG. It is assumed that the control signal Ei at this time is enabled.

A signal Di shifted and latched by the shift register 101 in response to the clock A input from the input clock terminal Ci is input to the latch circuit 106 and the A pattern detection circuit 102. The input data Di is from the least significant bit LSB to the most significant bit MS of the shift register 106.
shifted to B. When the A1 pattern shown in FIG. 6 of the most significant bit MSB appears in the signal B, the output 110 of the A pattern detection circuit 102 changes from "L" to "H" and is latched by the flip-flop 103. This latched signal C is output from the flip-flop 103.

The 1/8th period 105 is preset by the output 110 of the A pattern detection circuit 102, and the A pattern detection signal C is sampled at the rising edge of the clock signal D and the clock signal F, and is determined to be one time. Since the 1/8 period 105 runs free, a clock signal F having a rising edge every 8 bits is obtained after reset. If the A pattern continues, the protection circuit 104 detects that the A pattern detection signal continues m times. Here, since the value of m is 1, the A×m pattern detection signal G is output to the second protection circuit 106 in response to the next clock signal F.

The phase-controlled clock signal D has a rising edge every 8 bits and is input to the latch circuit 106. Since the latch circuit 106 latches the output signal of the shift register 101 for each octet, the B pattern that follows the A pattern is a pattern in which octets are aligned.

When the B pattern output from the latch circuit 106 is input to the B pattern detection circuit 107, the detection signal H of the B pattern detection circuit 107 changes from "L" to "H". In the second protection circuit 108, the B pattern detection signal H
When it is detected that the A×m detection signal G and the A×m detection signal G are both “H” at the same time, it is determined that the A pattern and the B pattern are continuous patterns, and a coincidence signal J is outputted in the same phase as the octet signal E.

Next, another embodiment of the frame pattern detection circuit according to the present invention will be described. FIG. 2 shows a circuit diagram of a frame pattern detection circuit 2 showing another embodiment of the present invention. In addition, in the same figure, signals A to J that overlap with those in FIG.
does not particularly show the same signal as in FIG. Shift registers 201a and 201b receive serial data C.
This is a shift register that inputs i (data A) and converts it into parallel data. That is, each shift register 201 is connected to a 1/2 frequency divider 205a that divides the frequency of the input clock Ci by 2, and this frequency divider 205a
The serial data Di is latched and shifted by the clock input from the input clock.

A pattern detection circuits 202a and 202b
are decoders each consisting of logic gates that detect a predetermined A-bit pattern. A pattern detection circuit 20
The input side of 2a is connected to the output side of the latch circuit 209a and shift register 201a, and the A pattern detection circuit 202b.
The input side of the latch circuit 209b and the shift register 2
01b, respectively. The output side of the A-pattern detection circuit 202a is connected to a flip-flop 203a, and the output side of the A-pattern detection circuit 202b is connected to a flip-flop 203b.

Each of the flip-flops 203 is a circuit that latches the output from the A pattern detection circuit 202 using the output clock from the 1/2 frequency divider 205. That is, the flip-flop 203a is connected to the A pattern detection circuit 20.
2a is latched by the output clock C from the 1/2 frequency divider 205, and the flip-flop 203b latches the output J from the A pattern detection circuit 202b by the output clock D from the 1/2 frequency divider 205. do. Flip-flops 203a and 203b transfer the latched signals to selection circuit 210, first protection circuit 204 and first protection circuit 203a and 203b.
/4 frequency divider 205b.

The first protection circuit 204 is a detection circuit that detects a succession of A pattern matching signals. The protection circuit 204 is connected at its output side to a second protection circuit 208 .

In this embodiment, the 1/2 frequency divider 205a and the 1/4 frequency divider 205b constitute a 1/8 frequency divider. The 1/4 frequency divider 205b is a flip-flop 20
It is controlled by the output of each A pattern detection circuit 202 which is latched at 3 and the control permission signal Ei. 1/4 frequency divider 20
The output side of 5b is the latch circuit 206a, 206b, the first
protection circuit 204 and a second protection circuit 208.

[0030] The latch circuits 206a and 206b receive the 8 output from the shift registers 201a and 201b.
The bit signal is latched by a clock M output from a ⅛ frequency divider formed by frequency dividers 205a and 205b.

The B pattern detection circuit 207 is a decoder composed of logic gates that detect a B pattern with aligned bits. The B pattern detection circuit 207 has its input side connected to the output sides of the selectors 213a and 213b, and its output side connected to the second protection circuit 208.

The second protection circuit 208 is a detection circuit that detects the output of the first protection circuit 204 indicating the continuation of the A pattern match signal and the subsequent continuation of the B pattern match signal. When the second protection circuit 208 detects the continuity of the A pattern and the B pattern, it outputs a match signal S.

The latch circuit 209a is the shift register 2
This circuit is connected to the output side of 01b and latches the output from this register. Further, the latch circuit 209b is
This circuit is connected to the output side of the shift register 201a and latches the output from this register. Latch circuit 2
The output sides of the latch circuit 209a and the shift register 201b are connected to the selector 212a, and the output sides of the latch circuit 209b and the shift register 201a are connected to the selector 212b.

The selector 212a is a latch circuit 209a.
This is a selector that selects the output of the shift register 201b. In addition, the selector 212b has a latch circuit 209b.
This is a selector that selects the output of the shift register 201a. The output side of the selector 212a is a latch circuit 206a.
Furthermore, the output side of the selector 212b is connected to the latch circuit 206b. Latch circuits 206a and 2
Selectors 213a and 213b connected to 06b are selectors that select the output of one of these latch circuits 206. These selectors 212 and 213 and latch circuit 206 are controlled by selection circuit 210.

The selection circuit 210 is a selection circuit controlled by the control permission signal Ei. The selector 211 selects the 1/2 frequency divider 20 according to the control output from the selection circuit 210.
This is a selector that selects one of the two clocks output from 5a and outputs it to the 1/4 frequency divider.

The frame pattern detection circuit 2, like the frame pattern detection circuit 1, can arbitrarily select the value of m in FIG. Explain the operation. In explaining the operation, it is assumed that the control permission signal Ei is in an enabled state, and signal waveform diagrams appearing in each circuit are shown in FIGS. 7 and 8. Further, FIG. 9 is a layout diagram showing the arrangement of FIGS. 7 and 8.

The 1/2 frequency divider 205a receives the input clock C
i(A) is frequency-divided and two phase-shifted clocks C and D are output. The shift register 201a latches input data Di(B) every two bits using a clock C, and outputs data E shifted from the least significant bit LSB to the most significant bit MSB. Furthermore, the shift register 201b latches input data B every two bits using a clock D, and outputs data F shifted from the least significant bit LSB to the most significant bit MSB.

The latch circuit 209a is the shift register 2
The output of 01b is latched with clock C having the same phase as the clock input to shift register 201a. The latch circuit 209b latches the output of the shift register 201a with a clock D having the same phase as the clock input to the shift register 201b. As a result, shift register 2
Even number bits are entered into the latch circuit 209b, and odd number bits are entered into the latch circuit 209b.

[0039] In the shift register 201b, "A2, A4,
A6, A8", and the latch circuit 209b has "A1, A3, A
5, A7” bit patterns are aligned, A pattern detection circuit 20
2b, the A pattern detection signal J changes from "L" to "H". The A pattern detection signal J is latched at the rising edge of the clock D in the flip-flop 203b. The latched A pattern detection signal J is input to the selection circuit 210 and the first protection circuit 204. The selection circuit 210 is controlled by the A pattern detection signal J latched by the clock D, and this signal J changes from "L" to "H".
When the output selection signal K changes to "H", the output selection signal K is set to "H".

When the selector 211 receives the selection signal K at "H", it selects the clock C and outputs it as the clock L. The 1/4 frequency divider 205b is the selector 211
The clock L output from the flip-flop 203
The A pattern detection signal J latched at b is input to control the phase of the counter.

Selectors 212a and 212b receive selection signal K at "H" and select output signals (including signals F and G) of shift register 201b and latch circuit 209b. The clock O outputted after phase control in the 1/4 frequency divider 205b is input to the first protection circuit 204. The protection circuit 204 includes a flip-flop 203
The OR of the A-pattern detection signal J latched at b and the A-pattern detection signal I latched at the flip-flop 203a is latched at the first rising edge of the clock O, and it is determined that the A-pattern has been detected once. The protection circuit 204 outputs the A pattern detection result to the second protection circuit 208 as an A×m pattern detection signal P at the next rising edge of the clock O.

[0042] The clock M output after being phase-controlled by the 1/4 frequency divider 205b is input to latch circuits 206a and 206b. In these latch circuits 206, the signal (including signals F and G) selected by the selector 212a or 212b is output at the rising edge of the clock M.
Latch. The octets of the signal latched by the latch circuit 206a or 206b are aligned after the A pattern is detected. Therefore, when the B pattern comes after the A pattern, the B pattern with aligned octets is latched in the latch circuits 206a and 206b. Latch circuit 2
The B pattern latched by 06a and 206b has the bit sequence “B2, B4, B6, B8, B1, B3, B5, B
7", selectors 213a and 213
Sort by b, "B1, B3, B5, B7,
B2, B4, B6, B8''.

Output signals of selectors 213a and 213b (
(including signal N) is input to the B pattern detection circuit 207 as a B pattern with aligned bits, the B pattern detection signal R changes from "L" to "H". Second protection circuit 20
8, the B pattern detection signal R and the A×m pattern detection signal P
are detected simultaneously by clock Q, and both of these detection signals are “
If the pattern is "H", it is determined that the pattern is a continuous pattern of pattern A and pattern B, and a match signal S is output in phase with the octet signal (including signal N).

As described above, according to these embodiments, by setting the number of bits input to the pattern detection circuit to 8 bits, it is possible to operate at a high bit rate regardless of the number of frame pattern bits.

FIG. 3 is a circuit diagram showing an example of the structure of the protection circuit in this embodiment. FIG. 3A shows an example where the number of protection stages is one (m=1). Figure 3(a)
The first protection circuit shown in FIG. 1 is equivalent to the first protection circuit 104 of the frame pattern detection circuit 1 shown in FIG. Furthermore, the first protection circuit shown in FIG. 3(a) can be configured by adding an OR gate before the D input terminal of the flip-flop 301.
This is equivalent to the first protection circuit 204 shown in FIG. Furthermore, the second protection circuit shown in FIG.
The protection circuit 108 is equivalent to the second protection circuit 208 shown in FIG. In addition, each symbol of the signal line in the same figure is as shown in Figure 1.
It is matched with

As shown in FIG. 3, the first protection circuit includes a flip-flop 301 and a flip-flop 302. The flip-flop 301 receives the A pattern detection signal C
This is a flip-flop to latch and adjust the phase. The flip-flop 302 is a flip-flop for outputting the A pattern detection signal C as an A×m pattern detection signal G to the protection circuit 2.

The second protection circuit includes a flip-flop 30
3, 304, an AND gate 305, and an inversion circuit 306. The AND gate 305 is an AND gate for detecting that the B pattern detection signal H and the A×m pattern detection signal G are generated simultaneously. Flip-flop 303 is a flip-flop for latching the output of AND gate 305 using clock I. The inversion circuit 306 is a gate circuit for inverting the clock I and adjusting the clock phase. flip flop 3
04 is a flip-flop that adjusts the phase of the output signal of the flip-flop 303 and outputs a coincidence signal J.

In FIG. 3(b), the number of protection stages is two (m=2).
An example of the circuit is shown. When the number of protection stages is two, the first protection circuit includes three flip-flops 307 to 3.
09 and an AND gate 313. Further, the second protection circuit includes three flip-flops 310 to 310.
312, OR gate 314, AND gate 315, 31
6 and an inversion circuit 317.

The flip-flop 307 is a flip-flop for latching the A pattern detection signal C and adjusting the phase thereof. Flip-flops 308 and 309 are flip-flops for latching the continuous A pattern detection signal C. The AND gate 313 is a gate circuit for detecting that the A pattern detection signal C is received twice in succession.

The OR gate 314 receives the A pattern detection signal C
This is a gate circuit for detecting a state in which the B pattern detection signal H is detected once after the A pattern detection signal C has been detected twice or the A pattern detection signal C has been detected twice. AND gate 315 is OR
This is a gate circuit for detecting the condition of the gate 314 and the simultaneous occurrence of the second B pattern detection signal H. The flip-flop 310 has an A pattern detection signal C of 2
This is a flip-flop for maintaining a state in which the B pattern detection signal H is applied twice in succession. The flip-flop 311 detects that the A pattern detection signal C is connected to the B pattern twice in succession.
This is a flip-flop for maintaining a state in which the pattern detection signal H has been detected once. The AND gate 316 is a gate circuit for detecting that the A pattern detection signal C occurs twice in a row and the B pattern detection signal H occurs twice in a row. The inversion circuit 317 is a gate circuit for inverting the clock I and adjusting the clock phase. The flip-flop 312 is a flip-flop for adjusting the phase of the output signal of the AND gate 316 and outputting it as a coincidence signal J.

Although the above-mentioned protection circuit shows the circuit configuration when m=1 or 2, the present invention is not particularly limited to this, and the circuit configuration when m=n (n is a natural number) is shown. It may be.

[0052]

As described above, according to the frame pattern detection circuit of the present invention, the frame pattern detection circuit is distributed for each octet, and the first pattern detection means detects a pattern for each octet, and both patterns are continuous. Since the second detection means for detecting that the present invention is applied is provided, it is possible to operate even at a high bit rate, and the transmission processing capacity of the transmission apparatus to which the present invention is applied can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a frame pattern detection circuit according to the present invention;

FIG. 2 is a circuit diagram showing another embodiment of the frame pattern detection circuit according to the present invention;

FIG. 3 is a circuit diagram showing an embodiment of a protection circuit in a frame pattern detection circuit according to the present invention;

[Fig. 4] Frame pattern detection circuit in conventional technology,

[
Figure 5: Structure of frame pattern,

FIG. 6 is a waveform diagram illustrating the operation of the embodiment shown in FIG. 1;

7 is a waveform diagram illustrating the operation of the embodiment shown in FIG. 2,

FIG. 8 is a waveform diagram illustrating the operation of the embodiment shown in FIG. 2;

FIG. 9: Arrangement of waveform diagrams shown in FIGS. 7 and 8;

[Figure 1
0 is a waveform diagram illustrating the operation of the prior art.

[Explanation of symbols]

101, 201a, 201b shift register 102
, 202a, 202b A pattern detection circuit 103, 2
03a, 203b Flip-flop 104, 204
First protection circuit 105
1/8 frequency divider 106, 206a, 206b, 209a, 209b
Latch circuit 107, 207 B pattern detection circuit 108, 208
Second protection circuit 205a
1/2 frequency divider 205b
1/4 frequency divider 210
selection circuit 211,
212a, 212b, 213a, 213b selector

Claims (3)

[Claims] Claim 1. A frame pattern detection circuit that receives an octet multiplexed frame pattern and detects the frame pattern, wherein the circuit has pattern detection means for detecting the octet frame pattern divided and arranged for each octet pattern. and a protection means for detecting, based on a detection signal from the pattern detection means, that each of the octet frame patterns is continuous and that different patterns are consecutively arranged. detection circuit. 2. A frame pattern detection circuit that receives an octet multiplexed frame pattern and detects the frame pattern, the circuit receives the octet multiplexed serial data and converts the serial data into parallel data. a converting means for converting, a first pattern detecting means for inputting output data from the converting means and detecting a first octet frame pattern, and a frequency division whose phase is controlled by the output of the first pattern detecting means. a latch means for latching the output data of the converting means using the output clock of the frequency divider, and a second pattern detecting means for inputting the output data of the latch means and detecting a second octet frame pattern. and the first octet is determined by the output of the first pattern detection means and the output clock of the frequency divider.
A first protection means for detecting that the frame pattern is continuous, a second pattern detection means, the output of the first protection means, and the output clock of the frequency divider, the first octet frame pattern is detected. and a second protection means for detecting a second octet frame pattern following the second octet frame pattern. 3. The frame pattern detection circuit according to claim 2, wherein the frequency divider is a ⅛ frequency divider.