JPH04344710A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To quicken a level change at an output side and to quicken the operation of the integrated circuit having an ECL circuit by selecting a resistance of an output resistor of one collector of the ECL circuit in capacitive coupling with a 2nd output transistor(TR) of the output section larger than the resistance of the other collector. CONSTITUTION:The other terminal of one resistive element R2 is connected to a base of a 1st output TR Q3 and the other terminal of the other resistive element R1 is connected to a base of a 2nd output TR Q4 via a capacitor C. Then the resistance of the resistive element Rl connecting to a 2nd output TR Q4 is selected larger than the resistance of the resistive element R2 connecting to the 1st output TR Q3. Since a level change in a base input of the 2nd output TR Q4 is larger and a large base current flows, a collector current of the 2nd output TR is larger, a stored charge on an output wiring is quickly discharged and a level change in an output node is quickened.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor logic integrated circuit having an ECL circuit that operates at high speed.

[0002] In semiconductor logic integrated circuits having ECL circuits, bipolar transistors are used in the non-saturation region of current, so there is no carrier accumulation effect and extremely fast switching operation is possible. It is used in large quantities in various fields such as computers, communication devices, and measuring instruments.

Conventionally, an emitter follower having a constant current circuit or a pull-down resistor on the emitter side has generally been used as an output section that receives differential output from an ECL circuit, amplifies it, and transmits it. However, in such an emitter follower, if the load capacitance is large, for example because the parasitic capacitance of the output side wiring is large, the time constant determined by this large load capacitance and the high resistance of the constant current circuit or the like becomes large. Therefore, when the output signal level of the output section shifts from H level to L level, it takes time for the charge accumulated in the load capacitance to discharge via the constant current circuit, etc., resulting in a delay in signal transmission. Time arises. To solve this problem, other circuits have been proposed in place of the constant current circuit, for example, a circuit in which an active pull-down circuit or the like is combined with an emitter follower.

0004

2. Description of the Related Art Referring to FIG. 3, a conventional ECL circuit of a semiconductor integrated circuit and its output section is shown in FIG.
An ECL circuit having a pull-down circuit in its output section will be described. In the same figure, input transistors 21 to 23 to which input signals A, B, and C are inputted to their bases, and a reference voltage transistor 24 whose base is maintained at a reference potential VR, have their emitters connected in common and form an ECL circuit. Configure.

The respective collectors of the input transistors 21 to 23 are connected together and connected to a high potential power source via a first resistor 19, and the reference voltage transistor 24 is connected to a high potential power source via a second resistor 20. Connected to power. The resistance values of both resistors 19 and 20 are set to be the same value.

The collector output of the ECL circuit is input to the bases of the transistors in the NOR output section on the left side and the OR output section on the right side of the figure. That is, the input transistor 21
The collector output of 23 is connected to the base of the first output transistor 14 of the NOR output section, and is also input to the base of the second output transistor 11 of the OR output section via the capacitor C1, and the reference voltage transistor The collector output of 24 is the first output transistor 15 of the OR output section.
, and is also input to the base of the second output transistor 10 of the NOR output section via a capacitor C2. The capacitors C1 and C2 respectively insulate the base level of the second output transistors 10 and 11 from the respective collector outputs in a direct current manner, and provide the output changes to the second output transistors.

[0007] The first and second output transistors 14, 15, 10, 11 constituting each of the NOR and OR output sections form a so-called totem pole at their respective output sections, and the first transistor 14 , 15 pull up their respective output nodes 30, 31, and the second transistors 10, 11 pull down their respective output nodes 30, 31.

With the above configuration, an EC whose output section is an emitter follower having this active pull-down circuit.
The L circuit receives base inputs A, B, and C of input transistors 21 to 23, forms NOR and OR signals, and sends them out from output nodes 30 and 31. At that time, especially when the logic levels of the output nodes 30 and 31 decrease from "H" to "L", respectively, 17 and 1 in the figure, respectively.
The charge accumulated on the wiring due to the parasitic capacitance CL of the output side wiring indicated as 8 is transferred to the second output transistors 10 and 11.
The output is quickly discharged via the , thereby quickly shifting the output to the L level, thereby increasing the speed of signal transmission.

[0009]

[Problems to be Solved by the Invention] The demand for higher speed semiconductor integrated circuits is increasing, and the active
Even in ECL circuits that include a pull-down circuit on the output side, there is still a strong demand for higher speeds.

The present invention improves a semiconductor integrated circuit equipped with an ECL circuit whose output section is an emitter follower (totem pole) having an active pull-down circuit.
Furthermore, it is an object of the present invention to provide a semiconductor integrated circuit capable of high-speed operation by increasing the speed.

[0011]

[Means for Accomplishing the Object] FIG. 1 is a diagram showing the principle of the present invention. In the figure, Q1 and Q2 are transistors forming an ECL circuit or a differential pair, Q3 and Q4 are first and second output transistors, respectively, R1 and R2 are first and second resistance elements, respectively, and C is a capacitor. (capacitor), S is a current source, VCC is a high potential power supply, and VEE is a low potential power supply.

In order to achieve the above object, the semiconductor integrated circuit of the present invention has, from a first aspect, first and second resistive elements each having one end connected to a high potential power source, as shown in FIG. (R1, R2), at least one input transistor (Q1) whose base receives an input signal (IN) and whose collector is connected to the other end of the first resistance element (R1), and whose base is at a reference potential (VR ) and a reference voltage transistor (Q2) whose collector is connected to the other end of the second resistive element (R2);
Q1) and a reference voltage transistor (Q2), each emitter of which is connected in common and connected to a low potential power supply via a current source; ) is connected to the other end of the first output transistor (Q
3), and the base is the other of the first and second resistance elements (
A first transistor (R1) is connected to the other end of the first output transistor (Q3) via a capacitor (C), has an emitter connected to a low potential power supply, and has a collector connected to the emitter of the first output transistor (Q3) to form an output end (OUT). In a semiconductor integrated circuit including an output section consisting of a two-output transistor (Q4),
the resistive element connected to the second output transistor (
The resistance value of R1) is larger than the resistance value of the resistance element (R2) connected to the first output transistor.

Further, from a second viewpoint, the semiconductor integrated circuit of the present invention includes first and second resistance elements (R1, R2) each having one end connected to a high potential power supply, and an input to at least one base. In response to the signal (IN), the collectors are connected to the other ends of the first and second resistance elements (R1, R2), and the emitters are connected in common and connected to a low potential power source via a current source. a differential pair (Q1, Q2), and a first output transistor (Q3) whose base is connected to the other end of one of the first and second resistance elements (R2) and whose collector is connected to a high potential power supply. , the base is connected to the other end of the first and second resistance elements (R1) via a capacitor (C), the emitter is connected to a low potential power supply, and the collector is connected to the first output transistor (Q3). and a second output transistor (Q4) connected to an emitter of the resistor element (R1) to form an output terminal (OUT), the resistor element (R1) connected to the second output transistor.
The resistance value of the resistance element (R2) is larger than the resistance value of the resistance element (R2) connected to the first output transistor.

[0014]

[Operation] The other end of one resistance element R2 is connected to the base of the first output transistor Q3, and the other end of the resistance element R2 is connected to the base of the first output transistor Q3.
The other end is input to the base of the second output transistor Q4 via a capacitor C, and the resistance value of the resistance element R1 connected to the second output transistor Q4 is equal to the resistance value of the resistance element connected to the first output transistor Q3. Due to the configuration in which the resistance value is greater than the resistance value of R2, the level change of the base input of the second output transistor Q4 becomes larger compared to the conventional circuit.
Since a large base current flows, the collector current of the second output transistor becomes large, and the accumulated charge on the output side wiring is quickly discharged, so that the level of the output node changes quickly. Further explanation will be given with reference to the drawings.

In FIG. 1, generally in an ECL circuit,
When one transistor Q1 is turned off, the potential of node n1 rises relatively quickly to the potential of VCC, and therefore the potential of node n2, which is connected to node n1 through capacitor C, also rises transiently, causing a large collector current to flow. It is something. In the present invention, the resistance value of the resistance element R1, which determines the potential level of the node n1, is made particularly larger than the other resistance element R2 to increase the change in the potential level of the node n1, so that the transient potential change of the node n2 also grows larger,
Since the base potential of the second output transistor Q4 can be greatly raised transiently, a large collector current can flow. This allows high-speed pulldown.

In an ECL circuit, the resistance values of the respective collector output resistors are usually set to be the same value. However, in the case of an ECL circuit whose output section is an emitter follower with an active pull-down circuit, the potential level of the output node OUT is determined by the potential of VCC, one resistance element R2, and the VBE of the first output transistor Q3. , is not affected by the resistance value of the other resistance element R1. Therefore, this resistance element R1 is connected to a transistor Q1 whose collector is connected to this resistance element R1.
The resistance value can be arbitrarily determined within a range in which is not saturated, and can be determined to have a large resistance value exclusively from the viewpoint of the output level of the collector output of this transistor Q1.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a circuit diagram of an ECL circuit and its output section of a semiconductor integrated circuit according to an embodiment of the present invention suitable as, for example, a signal level conversion circuit. In this circuit, the ECL circuit includes one input transistor Q1 and a reference voltage transistor Q2.
When configured as a circuit, an arbitrary number of input transistors of two or more are provided, or when the circuit shown in the figure is used as a sense amplifier of a memory circuit, complementary signals are applied to both transistors Q1 and Q2.

The circuit diagram in FIG. 2 differs from the principle diagram in FIG. 1 in that the current source S in FIG. 1 is replaced by the transistor Q in FIG.
In addition, in FIG. 2, resistors R4, R5 and a diode D are provided to determine the base potential of the second output transistor Q4, and one end of the resistor R4 is connected to the output node OUT. However, the other end is connected to the base of the second output transistor Q4 via a resistor R5, and is also connected to the low potential power supply VEE via a diode D.

The circuit that connects to the VEE power source via the base and emitter of the second output transistor Q4 and the circuit that connects to the VEE power source via the diode D form a current mirror circuit, so that no level change occurs in the input signal IN. When not present, the base current value of the second output transistor Q4 is approximately the same value as the current flowing through the diode D in the forward direction. Note that the resistor R4 is set based on the required current value of the diode D, that is, the base current value of the second output transistor, and the resistor R5 is determined to have a larger resistance value than the resistor R4.

In FIG. 2, the input signal IN is compared with the base potential VR of the reference voltage transistor Q2, and when the logic level of the input signal IN is "H", the collector output (node n3) becomes H by turning off the reference voltage transistor Q2. level, and the first output transistor Q3 of the output section turns on, so the output node OUT goes to logic level "H".
is set to The potential V of the output node OUT at this time is V=VC, where the base-emitter voltage of the first output transistor Q3 is VBE, and the potential drop across the resistor R2 is V2.
It is expressed as C-(V2+VBE).

The logic level of the input signal IN changes from “H” to “
When the voltage changes to "L", the first output transistor Q3 of the output section is turned off via the reference voltage transistor Q2 turned on, and on the other hand, the collector output of the node n1 rises to the H level through the input transistor Q1 turned off. As a result, node n2 rises transiently via capacitor C,
The second output transistor Q4 is turned on, and the output node OU
The charge accumulated in the parasitic capacitance CL of the output side wiring is rapidly discharged via T to the low potential power supply VEE side as the collector current of the second output transistor Q4.

Therefore, the potential of the output node OUT rapidly decreases, and the output node is set to the logic level "L". Specifically, if the ratio of R1 and R2 is set to 2:1, the time during which the output node is set to L will be shortened by about 20 to 30%. At this logic level "L", the output node OUT
The potential is maintained at a potential higher than VEE by the on-voltage of the second output transistor Q4 determined by the base current during steady state. Although the circuit of FIG. 2 obtains an output that is in phase with the input, it can also be used as an inverter by reversing the connections between nodes n1 and n3 in the figure.

In the above embodiment, for the purpose of illustration, a single-input signal level conversion circuit with the simplest configuration was shown. NOR circuit with O
It can be applied to a logic circuit such as an R circuit or a sense amplifier of a memory circuit by providing a complementary signal to a differential pair. It can also be used as an output buffer circuit.

Furthermore, as is well known, the current source, resistance element, etc. shown in the above embodiments can be modified in various ways, and any modification or modification of these from the above embodiments is included within the scope of the present invention. It will be done.

[0025]

[Effects of the Invention] As explained above, according to the present invention,
ECL capacitively coupled to the second output transistor of the output section
Due to the configuration in which the resistance value of the output resistor of one collector of the circuit is larger than the resistance value of the output resistor of the other collector, when the level of the input signal changes, the level change of the base of the second output transistor increases, and its collector current increases. As a result, the charge accumulated in the load capacitance on the output side can be quickly discharged, resulting in faster level changes on the output side, which is a remarkable feature that has made it possible to speed up the operation of semiconductor integrated circuits with ECL circuits. be effective.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a circuit diagram of an embodiment of the present invention.

FIG. 3 is a conventional circuit diagram.

[Explanation of symbols]

Q1, Q2 ECL circuit transistor Q3
First output transistor Q4
Second output transistor R1, R
2 Resistance element C Capacity

Claims (2)

[Claims] 1. First and second resistance elements (R1, R2) each having one end connected to a high potential power supply, and the first resistance element (R1) having a base receiving an input signal (IN) and a collector thereof.
at least one input transistor (Q1) connected to the other end, and a reference voltage transistor (Q2) whose base is maintained at a reference potential (VR) and whose collector is connected to the other end of said second resistive element (R2). ), the emitters of the input transistor (Q1) and the reference voltage transistor (Q2) are connected in common and connected to a low potential power supply via a current source, and the base is connected to the first and a first output transistor (Q3) connected to the other end of one of the first and second resistance elements (R2), the collector of which is connected to the high potential power supply; A first transistor (R1) is connected to the other end of the first output transistor (Q3) via a capacitor (C), has an emitter connected to a low potential power supply, and has a collector connected to the emitter of the first output transistor (Q3) to form an output end (OUT). Two-output transistor (
Q4), the resistance value of the resistance element (R1) connected to the second output transistor is equal to the resistance value of the resistance element (R2) connected to the first output transistor. ) A semiconductor integrated circuit characterized by a resistance value greater than that of the semiconductor integrated circuit. 2. First and second resistive elements (R1, R2) each having one end connected to a high potential power supply, at least one base receiving an input signal (IN), and a collector having the first and second resistive elements, respectively. a differential pair (Q1, Q2) connected to the other ends of the second resistive elements (R1, R2), whose emitters are connected in common and connected to a low potential power supply via a current source; A first output transistor (Q3) connected to the other end of one of the first and second resistance elements (R2) and having a collector connected to a high potential power supply, and a base of which is connected to the other end of the first and second resistance elements. (R1) is connected to the other end via a capacitor (C), and its emitter is connected to a low potential power supply, and its collector is connected to the emitter of the first output transistor (Q3), forming an output terminal (OUT). In a semiconductor integrated circuit comprising a two-output transistor (Q4), the resistance value of the resistance element (R1) connected to the second output transistor is equal to the resistance value of the resistance element (R2) connected to the first output transistor. A semiconductor integrated circuit characterized by a value greater than its resistance.