JPH04344480A - Device for performing logic simulation and test - Google Patents

Abstract

PURPOSE:To facilitate debugging by using test data in common to logic simulation and a test so as to shorten working time, and also enabling the result of the test to be analyzed under the same environment as the logic simulation. CONSTITUTION:A simulation portion 3 performs logic simulation using input- output waveform 2 input from a waveform input display portion 1 and the result of the simulation including the input-output waveform 2 is stored in a database 6. Data stored in the database 6 are converted into test data and a testing portion 7 apples the test data to a physical circuit and operates the circuit so that defective ICs are sorted. The result of the test is stored in the database 6 and displayed under the same operational environment as the simulation and then an operator analyzes the result of the test in interactive fashion.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention provides logic simulation that allows logic simulation of ICs, LSIs, etc. and testing of actual circuits to be performed using the same test vector, and that allows the test results to be analyzed interactively in the operating environment of the logic simulation. Regarding simulation test equipment.

0002

2. Description of the Related Art FIG. 3 is a flowchart showing a conventional procedure from logic simulation to actual circuit testing of an IC. When the logic simulator is activated and test vectors such as input waveform patterns and output expected value patterns are input for simulation (S11), the logic simulator performs simulation based on the circuit diagram (S12).
, output the signal value data of the simulation results (S
13).

[0003] When an actual circuit of an IC is created based on a circuit diagram that has been simulated, and when testing whether or not this actual circuit is functionally correct, a test program containing test vectors for testing is generated (S14). ). The tester is started, a test program is loaded, a test vector is applied to the actual circuit of the IC, and the IC is actually operated. Defective ICs are selected by comparing the output signal pattern obtained from the IC to be tested with the expected output value pattern.

0004

[Problems to be Solved by the Invention] By the way, conventional logic simulators and testers are activated independently to perform simulations and tests, so each time a logic simulation or actual circuit test is performed, test vectors are input to each. There is a problem in that it takes a long time to complete the process from simulation to testing. Furthermore, when a defect is detected through testing and requires analysis, it is not possible to proceed in an interactive manner as in the operating environment of a logic simulation, and the efficiency of debugging the test results is low.

[0005] The present invention has been made to solve these problems, and it is possible to use test vectors used in logic simulation for testing actual circuits, and to display test results in the operating environment of logic simulation. The purpose of the present invention is to provide a logic simulation/testing device that can shorten the time required for work from simulation to testing and facilitate the analysis of test results.

[0006]

[Means for Solving the Problems] A logic simulation/testing device according to the present invention is characterized in that test data for logic simulation is used for testing, and test results are displayed in an operating environment for logic simulation.

[0007]

[Operation] The logic simulation/test device according to the present invention simulates circuit operation by inputting test data for logic simulation, stores simulation-related data including test data, and stores stored test data. Convert it to test the actual circuit, operate the actual circuit, and test. In addition, when analyzing test results, the test results are displayed in the simulation operating environment. Therefore, the operator can analyze the test results in an interactive manner similar to that used during simulation.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on drawings showing embodiments thereof. FIG. 1 is a block diagram showing the configuration of a logic simulation/testing device according to the present invention (hereinafter referred to as the device of the present invention). In the figure, reference numeral 1 denotes a waveform input display section, which inputs an input/output waveform 2 consisting of an input waveform pattern for simulation and an expected output value pattern, and displays it on the display 4. The simulation unit 3 performs a logic simulation using the input input/output waveform 2, and the data management unit 5 stores the input/output waveform 2 and the simulation results in the database 6.

[0009] The database 6 stores circuit diagram data such as the characteristics of the elements constituting the circuit diagram and the connection relationships of the elements for each IC, and the data management section 5 uses the data stored in the database 6 for test purposes. It is converted into a test vector and given to the test section 7. The test section 7 applies the test vector to the actual circuit of the IC to be tested, causes the IC to actually operate, and obtains a test result. The data management unit 5 stores the obtained test results in the database 6. The timing analyzer 8 displays the input/output waveform 2 stored in the database 6 on the display 4, and also stores the input waveform pattern input in the database 6.

The procedure from logic simulation to actual circuit test of an IC using the apparatus of the present invention having the above configuration will be explained based on the flowchart shown in FIG. When a test vector consisting of an input waveform pattern and an output expected value pattern is input (S1), a logic simulator is started and a simulation is performed (S2). The progress of the simulation is shown on display 4 along with the circuit diagram, internal signal status, etc.
is displayed, and the operator proceeds through the logical simulation interactively. The data management unit 5 connects the simulation result and the test vector (S3), and stores the result in the database 6 as the simulation result (S4).

When testing an actual circuit, the test vectors stored in the database 6 are converted into test vectors by data linking (S5), and the tester is started to apply the converted test vectors to the actual circuit. and actually operates it (S6). The data management unit 5 stores the test results in the database 6 (S7).

When there is a problem in the actual circuit and the test results are to be analyzed, the data management section 5 displays the test results in the same operating environment as in the simulation, that is, in an environment where the circuit operation can be simulated in an interactive manner. Therefore, the operator can analyze the test results interactively, similar to a logic simulation. Also, timing analyzer 8
As a result, the circuit diagram and input/output waveforms stored in the database 6 are displayed on the display 4.

[0013]

Effects of the Invention As described above, the device of the present invention shortens the time required for the work from simulation to test by sharing the test data used for logic simulation and testing, and also allows the test results to be combined with the simulation. By displaying the data in the same operating environment and allowing interactive analysis, it has the excellent effect of increasing analysis efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an apparatus according to the present invention.

[Figure 2] I from logic simulation using the device of the present invention
3 is a flowchart showing the procedure up to an actual circuit test of C.

FIG. 3 is a flowchart showing a procedure from conventional logic simulation to actual IC circuit testing.

[Explanation of symbols]

1 Waveform input display section 2 Input/output waveform 3 Simulation Department 4 Display 5 Data management department 6 Database 7 Test department 8 Timing analyzer

Claims (1)

[Claims] 1. An apparatus for simulating the operation of a logic circuit at the circuit diagram stage and for testing the operation of an actual circuit produced based on the circuit diagram, comprising an input section for inputting test data for simulation. a simulator that performs simulation using input test data; a storage unit that stores simulation-related data including input test data; A test section that tests the operation of the actual circuit using the converted test data, and a display section that displays the test results of the actual circuit so that they can be analyzed in the same operating environment as the simulation. A logic simulation test device characterized by: