JPH04343244A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To make it possible to make a BT test on semiconductor memory ICs in the state of a wafer. CONSTITUTION:Each Vcc terminal 2 of memory ICs 1 is connected to a wafer 10 with a plurality of the memory ICs 1 with a full-bit automatic write circuit mounted thereon by a wiring 11, each GND terminal 3 of the memory ICs 1 is connected to the wafer 10 by a wiring 12 and each control signal input terminal 4 of full-bit write circuits of the ICs 1 is connected to the wafer by a wiring 13. By making a BT test on the memory ICs in the state of a wafer, a deteriorative failure in the memory ICs can be found before the assembly process of the memory ICs and a defective cell substitutable by a substitute circuit can be relieved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that requires accelerated operation testing during product inspection during the manufacturing process.

0002

[Prior Art] In general, semiconductor memory devices (hereinafter referred to as memory ICs) are subjected to high temperature and high voltage stress during the inspection process to confirm that the electrical characteristics of the memory IC satisfy standards after assembly is completed during the manufacturing process. An accelerated test (hereinafter referred to as a BT test) is performed by applying the following: to remove initial defects. This BT test uses a BT test equipment to perform the memory I
The circuit inside the memory IC is operated by inputting an operation control signal from the outside to the memory IC while applying voltage stress by applying high temperature stress and high power supply voltage to C within a specified time. This was achieved by applying voltage stress to the circuit elements.

Recently, a memory IC having an all-bit automatic write circuit has been considered for the purpose of simplifying the accelerated test environment for memory ICs. In this memory IC, by applying a constant voltage higher than the absolute rating to operate the automatic write circuit for all bits inside the memory IC to a certain pin (hereinafter referred to as SV pin), memory IC control signals and data input can be input. A signal (hereinafter referred to as DIN) and an address signal are generated inside the memory IC to enable writing of data to all bits.

Memory I with this all-bit automatic write circuit
As shown in FIG. 3, the BT test equipment for C applies temperature stress to a memory IC 1 having an all-bit automatic writing circuit, an applied voltage generator 7 for operating the all-bit automatic writing circuit, and an IC chip 1. It consists of a constant temperature bath 5 and a power supply voltage generator 6.

The BT operation of this memory IC will be explained below. The BT test device applies high temperature stress to the sealed IC after assembly is completed using a constant temperature bath 5, and while applying voltage stress by applying a high power supply voltage to the IC using a power supply voltage generator 6, This is done by applying an applied voltage of 1 to the SV pin to operate the automatic write circuit and apply voltage stress to the circuit elements. At this time, circuit elements with low withstand voltages are destroyed by high temperature and high voltage stress, and the memory IC having an all-bit automatic write circuit becomes defective.

[0006] Generally, a memory IC has a redundancy circuit that switches a defective memory cell on the circuit with a spare memory cell. Since replacement work is required, replacement is not possible with the memory IC after assembly is completed. Therefore, in the BT test equipment, B
Even if a defective memory cell generated by the T test can be repaired on the circuit by using a redundancy circuit, it is not possible to use a laser or the like on a memory IC that has been assembled, and replacement work cannot be performed. It was impossible.

[0007]

[Problems to be Solved by the Invention] Conventional memory ICs are in a wafer state when the diffusion process is completed, and many minute pellets exist on the wafer, so it is difficult to perform a BT test on a wafer basis. In this case, it was necessary to input signals to each pellet, which resulted in a large number of pins for input signals, which was not practical. Therefore, in conventional memory ICs, a BT test is performed after assembly is completed, and defective memory cells on the circuit are replaced with spare memory cells.

Furthermore, since the redundancy circuit uses a laser or the like to cut the fuse on the pellet and replace it, it is possible to repair the memory IC only when it is in the wafer state. Therefore, even if a memory cell that becomes defective in the BT test performed after assembly is completed can be repaired by using a redundancy circuit, replacement work cannot be performed, and it is impossible to repair a defective memory IC whose memory cell has been destroyed. Met.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device which solves these problems, enables a BT test in a wafer state, and eliminates initial defects caused by the BT test.

0010

[Means for Solving the Problem] The structure of the present invention is a memory IC having an automatic write circuit for all bits on a semiconductor substrate.
In a semiconductor memory device in which a plurality of pellets are mounted, a first wiring connects a first power terminal of each memory IC on the semiconductor substrate, and a second wiring connects a second power terminal of each memory IC. a third wire connecting the control signal input terminal of the all-bit automatic write circuit of each memory IC, and a first wire connected to each of the first, second, and third wires, respectively. It is characterized by comprising second and third input terminals.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram using an IC with an all-bit automatic write circuit according to an embodiment of the present invention. A memory IC having an all-bit automatic write circuit has a common Vcc terminal 2, which connects the power supply voltage (Vcc) terminals of these memory ICs with a wiring 11, and a ground voltage (hereinafter referred to as GND) of each memory IC.
It is connected to a GND common terminal 3 whose terminals are connected by a wiring 12 and a common terminal 4 which is connected to the SV pin of each memory IC by a wiring 13.

In the memory IC 1 with an all-bit automatic write circuit, IC control signals, DIN, and address signals are controlled by applying a constant voltage higher than the absolute rating of the IC to the SV pin.
It is generated internally in C to enable automatic and repeated write operations to all bits.

[0013] In the conventional wafer, wiring was provided only within the independent memory IC, but in this embodiment, a parallel wiring layer and a common terminal are further provided to connect the terminals of the individual ICs.

Next, the operation of this embodiment during the BT test will be explained with reference to the block diagram of the BT test apparatus shown in FIG.

While keeping the inside of the constant temperature chamber 5 at a high temperature for a specified time and applying temperature stress to the wafer 10, a higher power supply voltage is applied from the power supply voltage generator 6 to the Vcc and GN of the wafer 10.
When applied to the common terminal 12 of D, a high power supply voltage is applied to all the ICs on the wafer 10 connected in parallel, and voltage stress is applied to all the ICs.

Furthermore, when the applied voltage generator 7 applies an applied voltage to the common terminal 4 of the SV pins of the wafer, this means that voltage is applied to the SV pins 4 of all ICs on the wafer 10, and all bits are automatically written. The write circuit operates, a control signal, DIN, and address signal are generated inside the IC, data is written to the memory cell, and voltage stress can be applied to the memory cell.

At this time, circuit elements with low breakdown voltages in the memory IC 1 are destroyed by the high temperature and high voltage stress, and the memory IC having an all-bit automatic write circuit becomes defective. In this way, a BT test in a wafer state can be realized. After this BT test, individual memory IC
In order to perform a test to confirm the function as 1, the parallel wiring layer and common terminals are removed.

As a second embodiment of the present invention, the wirings 11 and 13 connecting the Vcc terminal 2 of each memory IC 1 and the SV pin 4 of each memory IC 1 explained in the first embodiment are connected by the same wiring. By applying a constant voltage higher than the absolute rating of the IC to the voltage input terminal 2 connected to this wiring, it becomes possible to implement a BT test similar to that of the first embodiment.

[0019]

As explained above, the present invention makes it possible to perform a BT test depending on the wafer state by wiring the power supply and signal electrodes of a plurality of memory ICs on a wafer in parallel.
Initial defects due to deterioration caused by the BT test can be removed before the assembly process, making it possible to reduce assembly costs. Furthermore, a memory IC having a replacement circuit can replace a defective memory cell with a non-defective memory cell, thereby relieving a deteriorated initial failure and making it a non-defective product. Furthermore, in conventional assembly, the package size is large and the number of BT tests that can be performed is limited, but by performing the BT test in the wafer state, it is possible to increase the number of BT tests that can be performed at one time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram when performing a BT test on the wafer 10 having parallel wiring shown in FIG. 1;

FIG. 3 is a block diagram of a conventional BT test device that performs a fully assembled memory IC.

[Explanation of symbols]

1 Memory IC2 with all-bit automatic writing circuit
Vcc common terminal 3 GND common terminal 4 SV pin common terminal 5 Constant temperature chamber 6 Power supply voltage generator 7 Applied voltage generator 10 Wafers 11 to 13 Wiring

Claims (2)

[Claims] 1. In a semiconductor memory device in which a plurality of memory IC pellets each having an automatic write circuit for all bits are mounted on a semiconductor substrate, a first power terminal of each memory IC is mounted on the semiconductor substrate. A first wiring to connect, a second wiring to connect the second power supply terminal of each of the memory ICs, and a third wiring to connect the control signal input terminal of the automatic all-bit write circuit of each of the memory ICs. and the first and second
and first, second, and third input terminals connected to each of the third wirings. 2. The semiconductor memory device according to claim 1, wherein the third wiring is the same wiring as the first wiring, and the third input terminal and the first input terminal are the same input terminal.