JPH04341924A - Error testing system for magnetic disk - Google Patents

Abstract

PURPOSE:To retry only the bit pulse of low probability to be an error by detecting every bit pluse of test format written and read to/from a magnetic disk, and deciding separately its probability to be the error, and omitting the retrial of the bit pulse of high probability to be the error. CONSTITUTION:An inspecting device is provided with a first and a second comparators 461, 462 and a first and a second error deciding parts 471, 472 respectively. First reference voltage Vs1 small compared with the average value of the peak values of every bit pulse to one round of a track and second reference voltage Vs2 close to the average value are set to the first and the second comparators respectively, and the peak values of these bit pulses are compared at a time. These compared results are decided by both the error deciding parts respectively, and the bit pulse decided to be the error by the second error deciding part is made the second error bit of the low probability to be the error, and error test is retried by the second comparator by necessary number of times so as to settle whether the second error bit is made the error bit or not.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic disk error test method, and more particularly to a method for efficiently performing an error test on read bit pulses of a test format.

0002

2. Description of the Related Art Hard magnetic disks (hereinafter simply referred to as magnetic disks or disks) used in computer systems are inspected during the manufacturing stage. There are various types of inspections, including a medium inspection in which a test format (ETF) is written to and read from a disk using a single-board inspection device.

[0003] Medium inspection will be explained with reference to FIG. (a)
1 shows a single disk (single disk) 1 to be inspected and its rotation mechanism 2, and the disk is mounted on a spindle 21 and rotates. (b) shows a basic configuration diagram of the single plate inspection device (SDT) 4, and (c) shows an example of an ETF. For writing, microprocessor (MPU)
ETF data from 49 is input to the write circuit 43 through the bus 48, adjusted to an appropriate level by the write amplifier 421, passed through the switch 41, and is sent between the indexes (IND) of one round of the track 11 by the magnetic head 3. written. During reading, the switch 41 is switched, and each bit pulse of the read ETF is input to the average value calculation circuit via the read amplifier 422, where the average value Vm of the peak values of each pulse for one revolution of the track is calculated. and is taken into the MPU. The average value Vm is transferred to a reference voltage setting circuit 45, multiplied by an appropriate coefficient to create a reference voltage Vs, and applied to the negative terminal of a comparator 46. With the subsequent rotation of the disk, the ETF is read out again, each bit pulse is applied to the + terminal of the comparator 46, and the peak value is compared with the reference voltage Vs. (
d) shows this, and the peak value of each read bit pulse changes as shown in the figure, for example,
A voltage smaller than the reference voltage Vs as shown in (a) is not detected. The error determination unit 47 counts the order of sequentially detected or undetected bit pulses from the index, compares them with bits of the written ETF that are in the same order, and determines what (a) originally exists. If so, it is considered a missing error. Next, figure (d)
In , when a bit pulse (indicated by a dotted line) is detected even though it is not supposed to be in position (b),
This is still an error and is called an extra error. Next is the pulse (c), which is detected just below the reference voltage Vs. If the reference voltage Vs and the peak value of the pulse change relative to each other due to some reason, such as noise, amplification of the read amplifier, or variation in the operating point of the comparator, the detection of the pulse (c) will be uncertain and unreliable. low. In contrast, a method is used in which error tests are performed multiple times on the same track (retries), and the ratio of the number of times it is determined to be an error to the number of times that it is not determined to be an error is determined. There is.

0004

[Problem to be Solved by the Invention] Now, the field of use of computer systems is expanding more and more, the production volume has increased in response to the increasing demand for magnetic disks, and the recording density has improved, so media inspection has become more difficult. There is a need to shorten the time required. On the other hand, in the above-mentioned medium inspection, the reliability of the inspection is ensured or improved by retrying, but since each bit is compared in the same way as above, retrying requires a surprisingly long time. The reality is that testing efficiency is low, which is a bottleneck. In response to the above, we will consider ways to shorten the inspection time. Looking at FIG. 2(d) above, the pulse (A) has a considerably small peak value compared to the reference voltage Vs, so it is not detected reliably by the comparator 46, so the error determination unit 47 reliably detects an error. It is determined that Since a pulse having a small peak value compared to the reference voltage Vs has a high probability of being an error, that is, a high error accuracy, it may be considered that there is no need to retry the pulse. However, (b)
The peak value of the pulse (c) is close to the reference voltage Vs, and as described above, the detection is uncertain, so it is necessary to retry. Therefore, by distinguishing between those that require retry and those that do not, and excluding those that are unnecessary, the retry time can be reduced by that amount, and the inspection time can be shortened. This invention is based on the above idea, and the read E
The object of this invention is to provide a method for shortening the retry time by distinguishing each bit pulse of a TF into those that require retry and those that do not, and exclude the unnecessary ones.

[0005]

[Means for Solving the Problems] This invention writes a test format on a track of a magnetic disk, calculates the average value of the peak value of each read bit pulse over one revolution of the track, and adds an appropriate coefficient to the average value. This is an error test method in an inspection device in which an error is determined by comparing the bit pulse detected by multiplying the signal to a reference voltage by a comparator and comparing the peak value with the reference voltage in an error determination section with the writing format. a first comparator and a first error determination section, and a second comparator and a second
An error determination section is provided. For the first comparator and the second comparator, set a first reference voltage that is smaller than the average value, for example, 60%, and a second reference voltage that is close to the average value, for example, 95%. , the peak values of each bit pulse are compared simultaneously by both comparators. Based on this comparison result, the bit pulse determined as an error by the first error determination section is determined as a first error bit with a high error accuracy, and the bit pulse determined as an error in the second error determination section is determined as a second error bit with a low error accuracy. Bit. The second comparator retries the error test a necessary number of times to determine whether or not the second error bit is to be an error bit.

[0006]

[Operation] In the error test method with the above configuration, the peak value of each bit pulse read out by the first comparator and the second comparator provided in the inspection device is
A first reference voltage that is smaller than the average value, for example, 60%, and a second reference voltage that is close to the average value, for example, 95%, are simultaneously compared by both comparators, and the comparison results are Processed by the error determination section, the first
The bit pulse determined to be an error by the error determination section is treated as a first error bit with high error accuracy. Further, the bit pulse determined as an error by the second error determination unit is treated as a second error bit with low error accuracy, and the second comparator retries the error test as many times as necessary to determine whether or not the second error bit is determined to be an error bit. will be finally determined. As a result of the above, the first error bit is not retried, so
This shortens the inspection time.

[0007]

[Embodiment] FIG. 1 shows an embodiment of this invention, (a)
1 is a schematic block diagram of a veneer inspection apparatus to which the present invention is applied; (b) is an explanatory diagram of first and second reference voltages for read bit pulses; and (c) is a flowchart of an inspection procedure. In FIG. 1(a), the writing of the ETF is performed by the MPU 49 using E as in FIG. 2(b).
The data of the TF is applied to the write circuit 43, and the magnetic head 3 writes on the track via the write amplifier 421 and the switch 41. The reading section is shown in Figure 1 (
As in b), a read amplifier 422 and an average value calculation circuit 44 are provided, and in addition, a first comparator 461 and a first error determination section 471 connected thereto are provided.
Reference voltage setting circuit and second comparator 462
and a second error determination section 472 and a second reference voltage setting circuit 452 connected thereto, each connected to an MPU 49 and a memory (MEM) 491 via a bus 48.
connected to. In the error test, as described above, the disk is rotated and the average value Vm of the peak values of each bit pulse of the read ETF is calculated. The average value is transferred in parallel to the first and second reference voltage setting circuits 451 and 452 via the bus under the control of the MPU, and is multiplied by coefficients of 60% and 95%, respectively, to set the first and second reference voltages. Reference voltages Vs1 and Vs2 are created and supplied to the - terminals of the first and second comparators 461 and 462, respectively. Each bit pulse obtained by the rotation of the disk is then input in parallel to the first and second comparators and compared with reference voltages Vs1 and Vs2, and the bit pulse is detected or not detected according to the respective peak values. To explain this using (b), it is assumed that the peak value of each bit pulse changes as shown in the diagram, and on the other hand, the first reference voltage Vs1 is considerably smaller than the average value Vm, and for example, the wave of pulse (A) The high value is not detected because it is even smaller than Vs1. This comparison result is compared with the corresponding bit of the write ETF in the first error determination section, and since anything that is not detected even with such a small reference voltage Vs1 is definitely an error, the first error determination section has a high error accuracy. It is determined to be the first error bit. Note that this bit is a missing error. Next, pulses (a)', (b), and (c) are all detected by the first reference voltage Vs1, but the detection is uncertain with the second reference voltage Vs2, and the second error determination unit detects an error. This is determined to be the second error bit with low accuracy. Note that the pulse (b) is generated by noise or the like. After the first and second error bits are recorded in memory,
The operation of the first comparator is stopped, and the error test is retried as many times as necessary using only the second comparator. Whether the bit is an error bit or not is finally determined based on the number of errors obtained by retrying. In the above, the coefficients for the average value Vm of the first and second reference voltages Vs1 and Vs2 were set to 60% and 95%, respectively, but it goes without saying that these need to be set to appropriate percentages depending on the actual situation. .

[0008] To summarize and explain the above error test procedure using the flowchart of FIG. 461,4
62, the first and second reference voltages Vs1, respectively.
, Vs2, and the comparison results are processed and the first and second error determination units 471 and 472 output the first error bit and the second error bit, respectively.
■ Included in M491. Next, the second comparator retries the error test as many times as necessary.
It is determined whether or not the error bit of
■ The recording of M is rewritten. The data of the first and second error bits are appropriately edited and output.

[0009]

As explained above, in the error test method according to the present invention, each bit pulse of the read ETF is compared with the average value of the peak value of each bit pulse by two comparators. After simultaneously comparing one reference voltage and a second reference voltage close to the average value,
The two error determination units each determine and distinguish between a first error bit with high error accuracy and a second error bit with low error accuracy, and the second comparator retries the error test as many times as necessary. It determines whether the second error bit is an error or not, and the retry for the first error bit is omitted, shortening the inspection time and contributing to improving the efficiency of magnetic disk medium inspection by the veneer inspection device. The effects are significant.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention; (a) is a schematic block configuration diagram of a veneer inspection apparatus to which the present invention is applied; (b) is an explanatory diagram of a read bit pulse and two reference voltages; (c) is a flowchart of the inspection procedure.

[Fig. 2] An explanatory diagram of a magnetic disk medium inspection method using a veneer inspection device, (a) is a relationship diagram between the veneer disk and the veneer inspection device, and (b) is a conventional block configuration diagram of the veneer inspection device. , (c) is an example of a test format (ETF), and (d) is an explanatory diagram of a method of comparing each read bit pulse with the reference voltage Vs.

[Explanation of symbols]

1...Hard magnetic disk (magnetic disk, disk),
11... Track, 2... Rotation mechanism, 21... Spindle, 3
...Magnetic head, 4...Single board inspection device (SDT), 41...Switch, 421...Write amplifier, 422...Read amplifier, 43...Write circuit, 44...Average value calculation circuit, 45
...Reference voltage setting circuit, 451...First reference voltage setting circuit, 452...Second reference voltage setting circuit, 46...Comparator, 461...First comparator, 462...Second comparator, 47...Error determination unit, 471...First Error determination unit, 472...Second error determination unit, 48...Bus, 4
9...Microprocessor (MPU), 491...Memory (MEM), Vs1...First reference voltage, Vs2...Second reference voltage, ■~■...Step numbers of the flowchart.

Claims (1)

[Claims] 1. A test format is written on a track of a magnetic disk, the average value of the peak value of each read bit pulse for one revolution of the track is determined, the average value is multiplied by an appropriate coefficient to obtain a reference voltage, and a comparator In the inspection device, a bit pulse detected by comparing the reference voltage and the peak value is compared with a write format by an error determining section to determine an error. A comparator and a second error determination unit are provided, and a first reference voltage that is smaller than the average value, for example, 60%, and a first reference voltage that is close to the average value, for example, 95%, is provided for the first comparator and the second comparator. % of the second reference voltage, the two comparators simultaneously compare the peak values of each bit pulse, and based on the comparison results, the bit pulse determined as an error by the first error determination section is determined by the error accuracy. The bit pulse determined as an error by the second error determination unit is determined to be a first error bit with a high error accuracy, and the error test is retried as many times as necessary by the second comparator, and the second error bit is determined to be an error. An error test method for a magnetic disk, which is characterized by determining whether or not the error occurs.