JPH04341011A - Dynamic frequency divider circuit - Google Patents

Abstract

PURPOSE:To enhance the maximum operating frequency of a frequency divider by shortening a delay time caused in the inverter of a GaAs dynamic frequency divider circuit. CONSTITUTION:The input signal of the inverter 1 is inputted to the gate of a current source FET 41 of a 1st stage source follower buffer 2 via a speedup capacitor 12. The gate is connected to a source via a bias resistor 13. Thus, the switching speed of a 1st stage source follower buffer 2 is improved to enhance the maximum operating frequency of the frequency divider.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic frequency divider circuit, and more particularly to a GaAS dynamic frequency divider circuit whose basic element is a Schottky barrier field effect transistor (hereinafter referred to as FET).

0002

2. Description of the Related Art Conventionally, this type of GaAS dynamic frequency divider circuit, as shown in FIG. The output of the source follower type buffer 7 is connected only to the input of the inverter 1, and the current source FET 41 of the source follower type buffer 2 is connected to the input of the inverter 1.
The gate of FET 41 was directly connected to the source of current source FET 41 itself.

A dynamic frequency divider circuit having such a configuration is as follows:
It functions as a ring oscillator via one stage of inverter 1. That is, transfer gates 4 and 6 each have
By adding clock input 8 and complementary clock input 9,
By causing the transfer gates 4 and 6 to perform switching operations and delaying the transmission time of the signal from the ring oscillator, an oscillation frequency that is half (f/2) of the clock frequency (f) is obtained. From this, the maximum operating frequency (fmax) is when the transfer gates 4 and 6 are completely turned on, that is, the original self-oscillation frequency (fosc) of the ring oscillator.
The self-oscillation frequency (fosc) is determined by the delay time (tpd) of the ring oscillation circuit, and specifically, f
osc=1/tpd, fmax=2fosc.

0004

[Problems to be Solved by the Invention] In this conventional GaAS dynamic frequency divider circuit, the delay time (t'pd) of the inverter circuit 1 occupies about half of the delay time (tpd) of the entire circuit, and The difficulty in increasing the speed of the circuit 1 has been an obstacle to high-speed operation of the frequency divider.

[0005]

[Means for Solving the Problems] The gist of the present invention is to connect an inverter circuit, a plurality of source follower type buffer circuits, and a plurality of source follower type buffer circuits connected in parallel between a first power source and a second power source. A ring oscillator is configured with transfer gate transistors, the transistors constituting the ring oscillator are Schottky barrier field effect transistors formed of compound semiconductors, and the output of the final stage of the plurality of source follower type buffer circuits is connected to the inverter circuit. a dynamic frequency divider circuit, which is supplied to the input, and the first stage of the plurality of source follower type buffer circuits is constituted by a first transistor to which the output of the inverter circuit is supplied, and a second transistor connected in series to the first transistor; The output of the final stage is supplied to the second transistor via the speed-up capacitor, and a bias resistance element is connected between the gate of the second transistor and the second power supply.

[0006]

In the dynamic frequency divider circuit having the above structure, when switching the inverter circuit, the output of the final stage switches the buffer current of the first stage via the speed-up capacitor. Therefore, both the rise time and fall time of the first stage are fast.

[0007]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In FIG. 1, the output of an inverter 1 is passed through a source follower type buffer 2 to a transfer gate F.
The source of the transfer gate FET 4 is connected to the drain of the transfer gate FET 6 via a source follower type buffer 5 . The source of the transfer gate FET 6 is connected to the input of the inverter 1 via a source follower type buffer 7.

The output of the source follower type buffer 7 is further connected to the gate of a current source FET 41 of the source follower type buffer 2 via a speed up capacitor 12, and the gate of the current reduction FET 41 is connected to a bias resistor 13. It is connected to the source and the negative voltage power supply 11 through the power supply.

Next, the operation of this embodiment will be explained with reference to FIG. FIG. 2 shows the input waveform 21 of the inverter 1 and the current source FET of the source follower type buffer 2 in this embodiment.
Gate input waveform 23 of , and output waveform 22 of buffer 2
This is a simulation result showing. Further, for comparison, the output waveform of the buffer 2 in the conventional circuit is also shown by a dotted line 24.

The rising delay times of this embodiment and the conventional circuit are respectively indicated by T1' and t1', and the falling delay times are indicated by T2' and t2'. Figure 2
As is clear from the above, T1', t1'>T2', t2'
Therefore, the maximum operating frequency (fmax) of the frequency divider is T2
In this embodiment, an inverter input signal is applied to the gate of the current source FET 41 of the source follower type buffer 2, and by changing the buffer current when switching the input signal, T2'<t2' is satisfied. As a result, the maximum operating frequency fmax of the frequency divider can be increased.

For example, the speed-up capacitor 12
When the gate bias resistor 13 is set to 0.5 pF and the gate bias resistor 13 is set to 100Ω, T2' becomes about 27 ps, which is lower than the conventional example's t2.
'=33 ps, the inverter delay is approximately 0.8 times.

In the case of this type of frequency divider, the delay time (tpd) of the entire circuit is approximately 2·t2', so the maximum operating frequency fmax of the conventional circuit is approximately 15 GHz, whereas in this embodiment, the maximum operating frequency fmax is approximately 15 GHz. The maximum operating frequency fmax is approximately 16.
It can be increased up to 6GHz.

In the first embodiment, buffers 2 and 7 constitute the first stage and the last stage, respectively.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. Components that are the same as those in the first embodiment are given the same reference numerals. The output of the source follower type buffer 7 is input to the inverter 1 via a DC cut capacitor 14 and further via a high resistance bias circuit 15. Furthermore, in this embodiment, the inverter 1 and the source follower type buffer 2
, 5, and 7 are all grounded, so in a frequency divider that operates with a single power supply, the inverter input can be further input to the gate of the current source FET 41 of the buffer 2 via the speed-up capacitor 12. , the same effects as in the first embodiment can be obtained.

[0017]

[Effects of the Invention] As explained above, the present invention provides a dynamic frequency divider circuit in which the output signal of the final stage of the buffer circuit is input not only to the inverter circuit but also to the gate of the second transistor of the first stage source follower type buffer. As a result, the delay time from the inverter input to the buffer output can be reduced, and the maximum operating frequency of the frequency divider can be increased.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing the operation of the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional example.

[Explanation of symbols]

1 Inverter 2, 5, 7 Source follower type buffer 4, 6 Transfer gate FET 8 Input terminal 9 Complementary input terminal 10 Positive voltage power supply 11 Negative voltage power supply 12 Speed-up capacitor 13 Gate bias resistor 14 DC cut capacitor 15 High resistance bias circuit for

Claims (2)

[Claims] Claim 1: A ring oscillator is formed by an inverter circuit connected in parallel between a first power source and a second power source, a plurality of source follower type buffer circuits, and a transfer gate transistor connecting the plurality of source follower type buffer circuits. the transistors forming the ring oscillator are Schottky barrier field effect transistors formed of compound semiconductors, and the output of the final stage of the plurality of source follower type buffer circuits is supplied to the input of the inverter circuit;
In the dynamic frequency divider circuit, the first stage of the plurality of source follower type buffer circuits is constituted by a first transistor to which an output of an inverter circuit is supplied, and a second transistor connected in series to the first transistor; A dynamic frequency divider circuit, characterized in that the output of the above is supplied to the second transistor via a speed-up capacitor, and a bias resistance element is connected between the gate of the second transistor and a second power supply. . 2. A high resistance bias circuit is further connected between the first power source and the second power source, and the output of the final stage is supplied to the inverter via a DC component removal capacitor and the high resistance bias circuit. 2. The dynamic frequency divider circuit according to claim 1, wherein said second power supply is at ground level.